From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: [PATCH 13/22] drm/i915: update DPIO constants for VLV Date: Sat, 2 Feb 2013 13:56:17 +0100 Message-ID: <1359809786-26434-14-git-send-email-jbarnes@virtuousgeek.org> References: <1359809786-26434-1-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy6-pub.bluehost.com (oproxy6-pub.bluehost.com [67.222.54.6]) by gabe.freedesktop.org (Postfix) with SMTP id C2BCDE6201 for ; Sat, 2 Feb 2013 05:26:17 -0800 (PST) Received: from [151.216.70.136] (port=59537 helo=jbarnes-t420.intel.com) by box514.bluehost.com with esmtpsa (TLSv1:CAMELLIA256-SHA:256) (Exim 4.80) (envelope-from ) id 1U1ceI-0006Th-8T for intel-gfx@lists.freedesktop.org; Sat, 02 Feb 2013 05:56:50 -0700 In-Reply-To: <1359809786-26434-1-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Separate bits for HDMI and DP. Signed-off-by: Shobhit Kumar Signed-off-by: Vijay Purushothaman --- drivers/gpu/drm/i915/intel_display.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 83d629d..2bc8ce7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4307,15 +4307,26 @@ static void vlv_update_pll(struct drm_crtc *crtc, mdiv |= DPIO_ENABLE_CALIBRATION; intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); - intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000); + //intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000); pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) | (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) | (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT); - intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv); - intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b); + //intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv); + if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) + intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), 0x0d770000); + else + // for DP/eDP. We'll not worry about VGA + intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), 0x0d740000); + + intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01C00000); + + //intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b); + intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f0051); + + intel_dpio_write(dev_priv, 0x804C, 0x87871000); dpll |= DPLL_VCO_ENABLE; I915_WRITE(DPLL(pipe), dpll); -- 1.7.9.5