From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: [PATCH 14/22] drm/i915: add HMDI workarounds on VLV Date: Sat, 2 Feb 2013 13:56:18 +0100 Message-ID: <1359809786-26434-15-git-send-email-jbarnes@virtuousgeek.org> References: <1359809786-26434-1-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy6-pub.bluehost.com (oproxy6-pub.bluehost.com [67.222.54.6]) by gabe.freedesktop.org (Postfix) with SMTP id DA9AFE628B for ; Sat, 2 Feb 2013 05:26:17 -0800 (PST) Received: from [151.216.70.136] (port=59537 helo=jbarnes-t420.intel.com) by box514.bluehost.com with esmtpsa (TLSv1:CAMELLIA256-SHA:256) (Exim 4.80) (envelope-from ) id 1U1ceJ-0006Th-4d for intel-gfx@lists.freedesktop.org; Sat, 02 Feb 2013 05:56:51 -0700 In-Reply-To: <1359809786-26434-1-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Need to do some extra work at PLL disable time to allow HDMI to come back up on the next mode set. v2: take dpio lock around update - jbarnes only do WA on VLV -jbarnes Signed-off-by: Jesse Barnes Signed-off-by: Vijay Purushothaman --- drivers/gpu/drm/i915/intel_display.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2bc8ce7..c0cb254 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1492,6 +1492,14 @@ static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) int reg; u32 val; + if (IS_VALLEYVIEW(dev_priv->dev)) { + mutex_lock(&dev_priv->dpio_lock); + // Flicker WA for HDMI + intel_dpio_write(dev_priv, 0x8200, 0x00000000); + intel_dpio_write(dev_priv, 0x8204, 0x00e00060); + mutex_unlock(&dev_priv->dpio_lock); + } + /* Don't disable pipe A or pipe A PLLs if needed */ if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) return; @@ -4299,6 +4307,12 @@ static void vlv_update_pll(struct drm_crtc *crtc, * In Valleyview PLL and program lane counter registers are exposed * through DPIO interface */ + + // program DD1 Tx lane resets sets to default + // WA for HDMI flicker issue + intel_dpio_write(dev_priv, 0x8200, 0x10080); + intel_dpio_write(dev_priv, 0x8204, 0x00600060); + mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); mdiv |= ((bestn << DPIO_N_SHIFT)); -- 1.7.9.5