From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: [PATCH 18/22] drm/i915: add flush control reg to IS_DISPLAYREG check Date: Sat, 2 Feb 2013 13:56:22 +0100 Message-ID: <1359809786-26434-19-git-send-email-jbarnes@virtuousgeek.org> References: <1359809786-26434-1-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy7-pub.bluehost.com (oproxy7-pub.bluehost.com [67.222.55.9]) by gabe.freedesktop.org (Postfix) with SMTP id EA4EAE5C72 for ; Sat, 2 Feb 2013 05:26:22 -0800 (PST) Received: from [151.216.70.136] (port=59537 helo=jbarnes-t420.intel.com) by box514.bluehost.com with esmtpsa (TLSv1:CAMELLIA256-SHA:256) (Exim 4.80) (envelope-from ) id 1U1ceN-0006Th-4C for intel-gfx@lists.freedesktop.org; Sat, 02 Feb 2013 05:56:55 -0700 In-Reply-To: <1359809786-26434-1-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org With the PTE poking code pulled into i915, we need to make sure we don't add the display offset to our TLB flush writes. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 28d5992..dde54b1 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1212,6 +1212,7 @@ static bool IS_DISPLAYREG(u32 reg) case FORCEWAKE_VLV: case FORCEWAKE_ACK_VLV: case VLV_GTLC_WAKE_CTRL: + case GFX_FLSH_CNTL_GEN6: return false; default: break; -- 1.7.9.5