From: Ben Widawsky <ben@bwidawsk.net>
To: intel-gfx@lists.freedesktop.org
Cc: Ben Widawsky <ben@bwidawsk.net>
Subject: [PATCH 03/10] drm/i915: Map registers before GTT init
Date: Mon, 8 Apr 2013 18:43:49 -0700 [thread overview]
Message-ID: <1365471836-28304-3-git-send-email-ben@bwidawsk.net> (raw)
In-Reply-To: <1365471836-28304-1-git-send-email-ben@bwidawsk.net>
This will allow us to read/write registers in GTT init.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_dma.c | 48 ++++++++++++++++++++---------------------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 4a1a517..ad7f284 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1518,6 +1518,28 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
goto free_priv;
}
+ mmio_bar = IS_GEN2(dev) ? 1 : 0;
+ /* Before gen4, the registers and the GTT are behind different BARs.
+ * However, from gen4 onwards, the registers and the GTT are shared
+ * in the same BAR, so we want to restrict this ioremap from
+ * clobbering the GTT which we want ioremap_wc instead. Fortunately,
+ * the register BAR remains the same size for all the earlier
+ * generations up to Ironlake.
+ */
+ if (info->gen < 5)
+ mmio_size = 512*1024;
+ else
+ mmio_size = 2*1024*1024;
+
+ dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
+ if (!dev_priv->regs) {
+ DRM_ERROR("failed to map registers\n");
+ ret = -EIO;
+ goto put_gmch;
+ }
+
+ intel_early_sanitize_regs(dev);
+
ret = i915_gem_gtt_init(dev);
if (ret)
goto put_bridge;
@@ -1542,28 +1564,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
- mmio_bar = IS_GEN2(dev) ? 1 : 0;
- /* Before gen4, the registers and the GTT are behind different BARs.
- * However, from gen4 onwards, the registers and the GTT are shared
- * in the same BAR, so we want to restrict this ioremap from
- * clobbering the GTT which we want ioremap_wc instead. Fortunately,
- * the register BAR remains the same size for all the earlier
- * generations up to Ironlake.
- */
- if (info->gen < 5)
- mmio_size = 512*1024;
- else
- mmio_size = 2*1024*1024;
-
- dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
- if (!dev_priv->regs) {
- DRM_ERROR("failed to map registers\n");
- ret = -EIO;
- goto put_gmch;
- }
-
- intel_early_sanitize_regs(dev);
-
aperture_size = dev_priv->gtt.mappable_end;
dev_priv->gtt.mappable =
@@ -1686,10 +1686,10 @@ out_mtrrfree:
dev_priv->mm.gtt_mtrr = -1;
}
io_mapping_free(dev_priv->gtt.mappable);
-out_rmmap:
- pci_iounmap(dev->pdev, dev_priv->regs);
put_gmch:
dev_priv->gtt.gtt_remove(dev);
+out_rmmap:
+ pci_iounmap(dev->pdev, dev_priv->regs);
put_bridge:
pci_dev_put(dev_priv->bridge_dev);
free_priv:
--
1.8.2.1
next prev parent reply other threads:[~2013-04-09 1:41 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-09 1:43 [PATCH 01/10] drm/i915: generalize pte vs. register BAR allocation Ben Widawsky
2013-04-09 1:43 ` [PATCH 02/10] drm/i915: Call out GEN6 PTE specificity Ben Widawsky
2013-04-09 1:43 ` Ben Widawsky [this message]
2013-04-09 8:59 ` [PATCH 03/10] drm/i915: Map registers before GTT init Daniel Vetter
2013-04-09 1:43 ` [PATCH 04/10] drm/i915: random checkpatch fixes Ben Widawsky
2013-04-09 1:43 ` [PATCH 05/10] drm/i915/ppgtt: Set scratch page "globally" Ben Widawsky
2013-04-09 1:43 ` [PATCH 06/10] drm/i915: Conditionally carve out GGTT PDE Ben Widawsky
2013-04-09 1:43 ` [PATCH 07/10] drm/i915: Rework PPGTT init code Ben Widawsky
2013-04-09 1:43 ` [PATCH 08/10] drm/i915: Abstract PPGTT enabling Ben Widawsky
2013-04-09 1:43 ` [PATCH 09/10] drm/i915: NULL aliasing_ppgtt on cleanup Ben Widawsky
2013-04-09 1:43 ` [PATCH 10/10] drm/i915: Allow PPGTT enable to fail Ben Widawsky
2013-04-09 9:08 ` Daniel Vetter
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