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From: Chris Wilson <chris@chris-wilson.co.uk>
To: akeem.g.abodunrin@intel.com, d.scott.phillips@intel.com,
	daniel.vetter@intel.com, david.c.stewart@intel.com,
	dri-devel@lists.freedesktop.org, francesco.balestrieri@intel.com,
	intel-gfx@lists.freedesktop.org, jani.nikula@intel.com,
	jon.bloomfield@intel.com, joonas.lahtinen@linux.intel.com,
	mika.kuoppala@intel.com, omer.aran@intel.com,
	pragyansri.pathi@intel.com, prathap.kumar.valsan@intel.com,
	sudeep.dutt@intel.com, tony.luck@intel.com
Subject: Re: [Intel-gfx] [RFC PATCH v3 2/2] drm/i915/gen7: Clear all EU/L3 residual contexts
Date: Mon, 20 Jan 2020 09:54:33 +0000	[thread overview]
Message-ID: <157951407310.10361.13824742770612575826@skylake-alporthouse-com> (raw)
In-Reply-To: <20200116174655.85926-3-akeem.g.abodunrin@intel.com>

Quoting Akeem G Abodunrin (2020-01-16 17:46:55)
> +static u32
> +gen7_fill_interface_descriptor(struct batch_chunk *state,
> +                              const struct batch_vals *bv,
> +                              const struct cb_kernel *kernel,
> +                              unsigned int count)
> +{
> +       u32 *cs = batch_alloc_items(state, 32, 8 * count);
> +       u32 offset = batch_offset(state, cs);
> +
> +       *cs++ = gen7_fill_kernel_data(state, kernel->data, kernel->size);
> +       *cs++ = (1 << 7) | (1 << 13);
> +       *cs++ = 0;
> +       *cs++ = (gen7_fill_binding_table(state, bv) - state->offset) | 1;
> +       *cs++ = 0;
> +       *cs++ = 0;
> +       *cs++ = 0;
> +       *cs++ = 0;
> +       /* 1 - 63dummy idds */
> +       memset32(cs, 0x00, (count - 1) * 8);
> +       batch_advance(state, cs);

cs is not at the end of the pack here. [cs + (count - 1) * 8]

> +
> +       return offset;
> +}

All others look ok.
-Chris
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  reply	other threads:[~2020-01-20 10:11 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-16 17:46 [Intel-gfx] [RFC PATCH v3 0/2] Security mitigation for Intel Gen7 HWs Akeem G Abodunrin
2020-01-16 17:46 ` [Intel-gfx] [RFC PATCH v3 1/2] drm/i915: Add mechanism to submit a context WA on ring submission Akeem G Abodunrin
2020-01-16 17:46 ` [Intel-gfx] [RFC PATCH v3 2/2] drm/i915/gen7: Clear all EU/L3 residual contexts Akeem G Abodunrin
2020-01-20  9:54   ` Chris Wilson [this message]
2020-01-17  1:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Security mitigation for Intel Gen7 HWs (rev3) Patchwork
2020-01-17  2:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-01-17  2:40 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork
2020-01-20  9:22 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork

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