Re: [Intel-gfx] [PATCH 2/3] drm/i915: prefer FORCE_WC for the blitter routines

[Chris Wilson <chris@chris-wilson.co.uk>]

Quoting Matthew Auld (2021-01-18 14:17:31)
> From: CQ Tang <cq.tang@intel.com>
> 
> The pool is shared and so we might find that there is a pool object with
> an existing mapping, but is mapped with different underlying type, which
> will result in -EBUSY.
> 
> Signed-off-by: CQ Tang <cq.tang@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> ---
>  drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> index 10cac9fac79b..c6db745900b3 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> @@ -55,7 +55,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce,
>         if (unlikely(err))
>                 goto out_put;
>  
> -       cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_WC);
> +       cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
>         if (IS_ERR(cmd)) {
>                 err = PTR_ERR(cmd);
>                 goto out_unpin;
> @@ -277,7 +277,7 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce,
>         if (unlikely(err))
>                 goto out_put;
>  
> -       cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_WC);
> +       cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
>         if (IS_ERR(cmd)) {
>                 err = PTR_ERR(cmd);
>                 goto out_unpin;

FORCE is becoming meaningless.

In this case we pin the pages upon acquiring from the pool, which then
prevents us from changing the mapping type. The purpose of which was so
that we could cache the mapping between users, and here we are saying
that cache is made useless. The danger is that we are now thrashing the
cache, hurting ourselves with the vmap overhead.

Maybe we should move the mapping-type into the buffer-pool cache itself?
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx