From: Chris Wilson <chris@chris-wilson.co.uk>
To: Cooper Chiou <cooper.chiou@intel.com>,
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>,
William Tseng <william.tseng@intel.com>
Subject: Re: [Intel-gfx] [PATCH v3] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9
Date: Thu, 04 Mar 2021 09:19:24 +0000 [thread overview]
Message-ID: <161484956454.28586.15932692857365863465@build.alporthouse.com> (raw)
In-Reply-To: <0c8ef2fb-34b0-98ea-12bb-fc300172799c@linux.intel.com>
Quoting Tvrtko Ursulin (2021-03-04 09:12:26)
>
> On 02/03/2021 06:27, Cooper Chiou wrote:
> > WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Gen9 to
> > resolve VP8 hardware encoding system hang up on GT1 sku for
> > ChromiumOS projects
> >
> > Slice specific MMIO read inaccurate so MGSR needs to be programmed
> > appropriately to get correct reads from these slicet-related MMIOs.
> >
> > It dictates that before any MMIO read into Slice/Subslice specific
> > registers, MCR packet control register(0xFDC) needs to be programmed
> > to point to any enabled slice/subslice pair, especially GT1 fused sku
> > since this issue can be reproduced on VP8 hardware encoding via ffmpeg
> > on ChromiumOS devices.
> > When exit PC7, MGSR will reset so that we have to skip fused subslice ID.
> >
> > Reference: HSD#1508045018,1405586840, BSID#0575
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > Cc: William Tseng <william.tseng@intel.com>
> > Cc: Lee Shawn C <shawn.c.lee@intel.com>
> >
> > Signed-off-by: Cooper Chiou <cooper.chiou@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 38 +++++++++++++++++++++
> > 1 file changed, 38 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 3b4a7da60f0b..4ad598a727a6 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -878,9 +878,47 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> > wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
> > }
> >
> > +static void
> > +gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> > +{
> > + const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
> > + unsigned int slice, subslice;
> > + u32 mcr, mcr_mask;
> > +
> > + GEM_BUG_ON(INTEL_GEN(i915) < 9);
> > +
> > + /*
> > + * WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml
> > + * Before any MMIO read into slice/subslice specific registers, MCR
> > + * packet control register needs to be programmed to point to any
> > + * enabled s/ss pair. Otherwise, incorrect values will be returned.
> > + * This means each subsequent MMIO read will be forwarded to an
> > + * specific s/ss combination, but this is OK since these registers
> > + * are consistent across s/ss in almost all cases. In the rare
> > + * occasions, such as INSTDONE, where this value is dependent
> > + * on s/ss combo, the read should be done with read_subslice_reg.
> > + */
> > + slice = fls(sseu->slice_mask) - 1;
> > + GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
> > + subslice = fls(intel_sseu_get_subslices(sseu, slice));
> > + GEM_BUG_ON(!subslice);
> > + subslice--;
> > +
> > + mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
> > + mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
> > +
> > + drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr);
> > +
> > + wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
> > +}
>
> Have you considered reusing existing wa_init_mcr? Just needs the
> top-level assert changed and otherwise it looks it would do the right
> thing for Gen9. Advantage being a smaller patch and less code to carry.
That was the first patch, and fails for the same reason. The problem
would appear to be in the mcr_mask for gt3.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-03-04 9:19 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-16 18:07 [Intel-gfx] [PATCH] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 Cooper Chiou
2020-09-16 19:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
2020-09-21 9:22 ` [Intel-gfx] [drm/i915] 04ff178484: phoronix-test-suite.supertuxkart.1024x768.Fullscreen.Ultimate.1.GranParadisoIsland.frames_per_second -30.4% regression kernel test robot
2021-01-21 14:18 ` Chiou, Cooper
2021-02-08 0:45 ` kernel test robot
2021-02-17 6:56 ` Chiou, Cooper
2021-02-09 6:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev2) Patchwork
2021-02-09 7:12 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-02-09 11:37 ` Chiou, Cooper
2021-02-17 10:24 ` Tvrtko Ursulin
2021-03-04 18:37 ` Chiou, Cooper
2021-03-04 20:10 ` Matt Roper
2021-02-17 9:31 ` [Intel-gfx] [PATCH] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 Chiou, Cooper
2021-02-17 9:59 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev3) Patchwork
2021-03-02 3:55 ` [Intel-gfx] [PATCH] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 Cooper Chiou
2021-03-02 5:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev4) Patchwork
2021-03-02 6:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-03-02 6:23 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-03-02 6:27 ` [Intel-gfx] [PATCH v3] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 Cooper Chiou
2021-03-02 7:17 ` Chiou, Cooper
2021-03-04 9:12 ` Tvrtko Ursulin
2021-03-04 9:19 ` Chris Wilson [this message]
2021-03-04 11:56 ` Chris Wilson
2021-03-05 0:53 ` Chris Wilson
2021-03-05 9:23 ` Tvrtko Ursulin
2021-03-05 12:20 ` Chris Wilson
2021-03-05 15:23 ` Chris Wilson
2021-03-05 15:24 ` Chiou, Cooper
2021-03-05 16:01 ` Tvrtko Ursulin
2021-03-06 7:16 ` Chiou, Cooper
2021-03-08 17:32 ` Chiou, Cooper
2021-03-10 10:19 ` Tvrtko Ursulin
2021-03-10 10:54 ` Chris Wilson
2021-03-11 2:36 ` Chiou, Cooper
2021-03-11 1:27 ` Chiou, Cooper
2021-03-11 10:12 ` Tvrtko Ursulin
2021-03-11 10:47 ` Chiou, Cooper
2021-03-02 7:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev5) Patchwork
2021-03-02 7:28 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-03-03 18:09 ` [Intel-gfx] [PATCH v4] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 Cooper Chiou
2021-03-03 19:54 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev6) Patchwork
2021-03-05 12:58 ` [Intel-gfx] [PATCH v5] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 Cooper Chiou
2021-03-06 7:19 ` Chiou, Cooper
2021-03-10 3:09 ` Chiou, Cooper
2021-03-11 10:45 ` Tvrtko Ursulin
2021-03-11 11:11 ` Joonas Lahtinen
2021-03-23 16:30 ` Rodrigo Vivi
2021-03-05 14:44 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev7) Patchwork
2021-03-05 17:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-10-21 18:05 ` [Intel-gfx] [PATCH v6] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 Cooper Chiou
2021-10-21 22:15 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev8) Patchwork
2021-10-22 4:14 ` [Intel-gfx] [PATCH v7] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 Cooper Chiou
2021-10-22 13:23 ` Tvrtko Ursulin
2021-10-22 5:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev9) Patchwork
2021-10-22 9:05 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-10-25 4:26 ` [Intel-gfx] [PATCH v8] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 Cooper Chiou
2021-11-01 10:15 ` Tvrtko Ursulin
2021-11-01 10:40 ` Joonas Lahtinen
2021-11-01 10:49 ` Tvrtko Ursulin
2021-10-25 5:34 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev10) Patchwork
2021-10-25 9:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev11) Patchwork
2021-10-25 12:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=161484956454.28586.15932692857365863465@build.alporthouse.com \
--to=chris@chris-wilson.co.uk \
--cc=cooper.chiou@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jani.nikula@intel.com \
--cc=tvrtko.ursulin@linux.intel.com \
--cc=william.tseng@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).