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From: Patchwork <patchwork@emeril.freedesktop.org>
To: "Matthew Brost" <matthew.brost@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GuC submission support
Date: Thu, 24 Jun 2021 07:17:15 -0000	[thread overview]
Message-ID: <162451903517.1852.1773214721452379438@emeril.freedesktop.org> (raw)
In-Reply-To: <20210624070516.21893-1-matthew.brost@intel.com>

== Series Details ==

Series: GuC submission support
URL   : https://patchwork.freedesktop.org/series/91840/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
a582e9c666ff drm/i915/guc: Relax CTB response timeout
743d703ec315 drm/i915/guc: Improve error message for unsolicited CT response
beb15fc92c92 drm/i915/guc: Increase size of CTB buffers
3d4dab7e7c81 drm/i915/guc: Add non blocking CTB send function
c0779d6fc3b7 drm/i915/guc: Add stall timer to non blocking CTB send function
2c9efd827987 drm/i915/guc: Optimize CTB writes and reads
-:112: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#112: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:528:
+		CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u size=%u\n",
+			  ctb->desc->head, ctb->desc->tail, ctb->size);

total: 0 errors, 0 warnings, 1 checks, 184 lines checked
28324246d8aa drm/i915/guc: Module load failure test for CT buffer creation
-:38: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: John Harrison <John.C.Harrison@Intel.com>' != 'Signed-off-by: John Harrison <john.c.harrison@intel.com>'

total: 0 errors, 1 warnings, 0 checks, 20 lines checked
071d7fa76a91 drm/i915/guc: Add new GuC interface defines and structures
-:98: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#98: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h:275:
+	 * reset. (in micro seconds). */

total: 0 errors, 1 warnings, 0 checks, 83 lines checked
9cc26b390c65 drm/i915/guc: Remove GuC stage descriptor, add lrc descriptor
-:120: WARNING:PREFER_DEFINED_ATTRIBUTE_MACRO: __always_unused or __maybe_unused is preferred over __attribute__((__unused__))
#120: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:69:
+__attribute__ ((unused))

total: 0 errors, 1 warnings, 0 checks, 208 lines checked
dbd8df00f28f drm/i915/guc: Add lrc descriptor context lookup array
0478ac5fcc47 drm/i915/guc: Implement GuC submission tasklet
86db42bdbf1a drm/i915/guc: Add bypass tasklet submission path to GuC
b9faec389671 drm/i915/guc: Implement GuC context operations for new inteface
-:109: ERROR:POINTER_LOCATION: "foo* bar" should be "foo *bar"
#109: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc.h:113:
+static inline int intel_guc_send_busy_loop(struct intel_guc* guc,

-:117: ERROR:IN_ATOMIC: do not use in_atomic in drivers
#117: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc.h:121:
+	might_sleep_if(loop && (!in_atomic() && !irqs_disabled()));

-:122: ERROR:IN_ATOMIC: do not use in_atomic in drivers
#122: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc.h:126:
+		if (likely(!in_atomic() && !irqs_disabled()))

-:551: WARNING:REPEATED_WORD: Possible repeated word: 'from'
#551: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:784:
+	 * could be regisgered either the guc_id has been stole from from

-:789: WARNING:ONE_SEMICOLON: Statements terminations use 1 semicolon
#789: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:985:
+		return ret;;

total: 3 errors, 2 warnings, 0 checks, 887 lines checked
0ddf4a0e5ead drm/i915/guc: Insert fence on context when deregistering
-:7: WARNING:REPEATED_WORD: Possible repeated word: 'before'
#7: 
registered with the GuC. In this a case deregister must be before before

total: 0 errors, 1 warnings, 0 checks, 113 lines checked
53890c0d5072 drm/i915/guc: Defer context unpin until scheduling is disabled
9e9fc047e7c1 drm/i915/guc: Disable engine barriers with GuC during unpin
e7452c180185 drm/i915/guc: Extend deregistration fence to schedule disable
195129a34fbe drm/i915: Disable preempt busywait when using GuC scheduling
e53180c87b60 drm/i915/guc: Ensure request ordering via completion fences
-:90: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#90: FILE: drivers/gpu/drm/i915/i915_request.c:1675:
+		if ((!uses_guc && is_power_of_2(READ_ONCE(prev->engine)->mask | rq->engine->mask)) ||

total: 0 errors, 1 warnings, 0 checks, 64 lines checked
59c796b965e6 drm/i915/guc: Disable semaphores when using GuC scheduling
588df5bce44c drm/i915/guc: Ensure G2H response has space in buffer
-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'len' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc.h:100:
+#define MAKE_SEND_FLAGS(len) \
+	({GEM_BUG_ON(!FIELD_FIT(INTEL_GUC_SEND_G2H_DW_MASK, len)); \
+	(FIELD_PREP(INTEL_GUC_SEND_G2H_DW_MASK, len) | INTEL_GUC_SEND_NB);})

-:24: ERROR:SPACING: space required after that ';' (ctx:VxV)
#24: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc.h:102:
+	(FIELD_PREP(INTEL_GUC_SEND_G2H_DW_MASK, len) | INTEL_GUC_SEND_NB);})
 	                                                                 ^

-:202: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#202: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:597:
+#define G2H_LEN_DW(f) \
+	FIELD_GET(INTEL_GUC_SEND_G2H_DW_MASK, f) ? \
+	FIELD_GET(INTEL_GUC_SEND_G2H_DW_MASK, f) + GUC_CTB_HXG_MSG_MIN_LEN : 0

-:202: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'f' - possible side-effects?
#202: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:597:
+#define G2H_LEN_DW(f) \
+	FIELD_GET(INTEL_GUC_SEND_G2H_DW_MASK, f) ? \
+	FIELD_GET(INTEL_GUC_SEND_G2H_DW_MASK, f) + GUC_CTB_HXG_MSG_MIN_LEN : 0

total: 2 errors, 0 warnings, 2 checks, 296 lines checked
a03438ead8d3 drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC
-:218: ERROR:POINTER_LOCATION: "foo* bar" should be "foo *bar"
#218: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:257:
+static int guc_submission_busy_loop(struct intel_guc* guc,

total: 1 errors, 0 warnings, 0 checks, 333 lines checked
c84dc5dbebea drm/i915/guc: Update GuC debugfs to support new GuC
4adb7ce61e5f drm/i915/guc: Add several request trace points
37ebee77b9c2 drm/i915: Add intel_context tracing
-:152: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#152: FILE: drivers/gpu/drm/i915/i915_trace.h:909:
+DECLARE_EVENT_CLASS(intel_context,
+	    TP_PROTO(struct intel_context *ce),

-:155: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#155: FILE: drivers/gpu/drm/i915/i915_trace.h:912:
+	    TP_STRUCT__entry(

-:162: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#162: FILE: drivers/gpu/drm/i915/i915_trace.h:919:
+	    TP_fast_assign(

total: 0 errors, 0 warnings, 3 checks, 264 lines checked
351767d30288 drm/i915/guc: GuC virtual engines
-:122: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#122: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:285:
+		return intel_guc_virtual_engine_has_heartbeat(engine);
+	else

-:847: CHECK:LINE_SPACING: Please don't use multiple blank lines
#847: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1894:
+
+

total: 0 errors, 1 warnings, 1 checks, 785 lines checked
5ca8f1a503a8 drm/i915: Track 'serial' counts for virtual engines
81e0788642e7 drm/i915: Hold reference to intel_context over life of i915_request
2fca6597dcd8 drm/i915/guc: Disable bonding extension with GuC submission
7ae740c21ec4 drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs
-:346: ERROR:CODE_INDENT: code indent should use tabs where possible
#346: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1411:
+        * In GuC submission mode we do not know which physical engine a request$

-:347: ERROR:CODE_INDENT: code indent should use tabs where possible
#347: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1412:
+        * will be scheduled on, this creates a problem because the breadcrumb$

-:348: ERROR:CODE_INDENT: code indent should use tabs where possible
#348: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1413:
+        * interrupt is per physical engine. To work around this we attach$

-:349: ERROR:CODE_INDENT: code indent should use tabs where possible
#349: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1414:
+        * requests and direct all breadcrumb interrupts to the first instance$

-:350: ERROR:CODE_INDENT: code indent should use tabs where possible
#350: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1415:
+        * of an engine per class. In addition all breadcrumb interrupts are$

-:352: ERROR:CODE_INDENT: code indent should use tabs where possible
#352: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1417:
+        */$

total: 6 errors, 0 warnings, 0 checks, 329 lines checked
3c79abc34b26 drm/i915/guc: Reset implementation for new GuC interface
-:306: CHECK:LINE_SPACING: Please don't use multiple blank lines
#306: FILE: drivers/gpu/drm/i915/gt/mock_engine.c:266:
+
+

-:390: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "guc->lrc_desc_pool_vaddr"
#390: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:250:
+	return guc->lrc_desc_pool_vaddr != NULL;

-:545: ERROR:SPACING: spaces required around that '||' (ctx:VxW)
#545: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:540:
+			if (pending_enable|| deregister)
 			                  ^

-:585: WARNING:MEMORY_BARRIER: memory barrier without comment
#585: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:580:
+	wmb();

-:637: ERROR:CODE_INDENT: code indent should use tabs where possible
#637: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:622:
+ ^I */$

-:637: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#637: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:622:
+ ^I */$

-:1294: CHECK:LINE_SPACING: Please don't use multiple blank lines
#1294: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc.c:568:
 
+

total: 2 errors, 2 warnings, 3 checks, 1301 lines checked
848ca056fc3e drm/i915: Reset GPU immediately if submission is disabled
-:93: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#93: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:223:
+
+}

total: 0 errors, 0 warnings, 1 checks, 181 lines checked
17b20c0c8bd7 drm/i915/guc: Add disable interrupts to guc sanitize
-:11: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com'
#11: 
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com

total: 1 errors, 0 warnings, 0 checks, 70 lines checked
345f1eca0a86 drm/i915/guc: Suspend/resume implementation for new interface
a921fc062048 drm/i915/guc: Handle context reset notification
5560a36d3f00 drm/i915/guc: Handle engine reset failure notification
ee41dea700c0 drm/i915/guc: Enable the timer expired interrupt for GuC
adcd1418b513 drm/i915/guc: Provide mmio list to be saved/restored on engine reset
-:355: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#355: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:212:
+	temp_set.registers = kmalloc_array(temp_set.size,
+					  sizeof(*temp_set.registers),

-:384: CHECK:SPACING: No space is necessary after a cast
#384: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:241:
+	temp_set.registers = (struct guc_mmio_reg *) (((u8 *) blob) + offset);

total: 0 errors, 0 warnings, 2 checks, 400 lines checked
b7f2c290b8da drm/i915/guc: Don't complain about reset races
cf156af71348 drm/i915/guc: Enable GuC engine reset
d43f902c9f69 drm/i915/guc: Capture error state on context reset
c24a302b3409 drm/i915/guc: Fix for error capture after full GPU reset with GuC
-:119: CHECK:BRACES: braces {} should be used on all arms of this statement
#119: FILE: drivers/gpu/drm/i915/gt/intel_engine_cs.c:1701:
+	if (guc) {
[...]
+	} else
[...]

-:123: CHECK:BRACES: Unbalanced braces around else statement
#123: FILE: drivers/gpu/drm/i915/gt/intel_engine_cs.c:1705:
+	} else

-:408: ERROR:OPEN_BRACE: open brace '{' following enum go on the same line
#408: FILE: drivers/gpu/drm/i915/i915_request.h:655:
+enum i915_request_state
+{

-:418: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: John Harrison <John.C.Harrison@Intel.com>' != 'Signed-off-by: John Harrison <john.c.harrison@intel.com>'

total: 1 errors, 1 warnings, 2 checks, 348 lines checked
2529cfc15930 drm/i915/guc: Hook GuC scheduling policies up
-:80: WARNING:ENOTSUPP: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP
#80: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:113:
+		return -ENOTSUPP;

-:148: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: John Harrison <John.C.Harrison@Intel.com>' != 'Signed-off-by: John Harrison <john.c.harrison@intel.com>'

total: 0 errors, 2 warnings, 0 checks, 113 lines checked
055c438902ea drm/i915/guc: Connect reset modparam updates to GuC policy flags
-:49: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#49: FILE: drivers/gpu/drm/i915/i915_debugfs_params.c:14:
+#define MATCH_DEBUGFS_NODE_NAME(_file, _name)	(strcmp((_file)->f_path.dentry->d_name.name, (_name)) == 0)

-:51: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#51: FILE: drivers/gpu/drm/i915/i915_debugfs_params.c:16:
+#define GET_I915(i915, name, ptr)	\
+	do {	\
+		struct i915_params *params;	\
+		params = container_of(((void *) (ptr)), typeof(*params), name);	\
+		(i915) = container_of(params, typeof(*(i915)), params);	\
+	} while(0)

-:54: CHECK:SPACING: No space is necessary after a cast
#54: FILE: drivers/gpu/drm/i915/i915_debugfs_params.c:19:
+		params = container_of(((void *) (ptr)), typeof(*params), name);	\

-:56: ERROR:SPACING: space required before the open parenthesis '('
#56: FILE: drivers/gpu/drm/i915/i915_debugfs_params.c:21:
+	} while(0)

-:103: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: John Harrison <John.C.Harrison@Intel.com>' != 'Signed-off-by: John Harrison <john.c.harrison@intel.com>'

total: 1 errors, 2 warnings, 2 checks, 68 lines checked
9bedfd84c9e8 drm/i915/guc: Include scheduling policies in the debugfs state dump
-:72: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: John Harrison <John.C.Harrison@Intel.com>' != 'Signed-off-by: John Harrison <john.c.harrison@intel.com>'

total: 0 errors, 1 warnings, 0 checks, 44 lines checked
b49edbcc9280 drm/i915/guc: Add golden context to GuC ADS
-:254: CHECK:SPACING: No space is necessary after a cast
#254: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:453:
+	ptr = ((u8 *) blob) + offset;

-:279: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#279: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:470:
+			drm_err(&gt->i915->drm, "No engine state recorded for class %d!\n", engine_class);

total: 0 errors, 1 warnings, 1 checks, 342 lines checked
8a320e973471 drm/i915/guc: Unblock GuC submission on Gen11+


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  parent reply	other threads:[~2021-06-24  7:17 UTC|newest]

Thread overview: 170+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-24  7:04 [Intel-gfx] [PATCH 00/47] GuC submission support Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 01/47] drm/i915/guc: Relax CTB response timeout Matthew Brost
2021-06-24 17:23   ` Michal Wajdeczko
2021-06-24  7:04 ` [Intel-gfx] [PATCH 02/47] drm/i915/guc: Improve error message for unsolicited CT response Matthew Brost
2021-06-25 11:58   ` Michal Wajdeczko
2021-06-24  7:04 ` [Intel-gfx] [PATCH 03/47] drm/i915/guc: Increase size of CTB buffers Matthew Brost
2021-06-24 13:49   ` Michal Wajdeczko
2021-06-24 15:41     ` Matthew Brost
2021-06-25 12:03       ` Michal Wajdeczko
2021-06-24  7:04 ` [Intel-gfx] [PATCH 04/47] drm/i915/guc: Add non blocking CTB send function Matthew Brost
2021-06-24 14:48   ` Michal Wajdeczko
2021-06-24 15:49     ` Matthew Brost
2021-06-24 17:02       ` Michal Wajdeczko
2021-06-24 22:41         ` Matthew Brost
2021-06-25 11:50           ` Michal Wajdeczko
2021-06-25 17:53             ` Matthew Brost
2021-06-24 22:47         ` Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 05/47] drm/i915/guc: Add stall timer to " Matthew Brost
2021-06-24 17:37   ` Michal Wajdeczko
2021-06-24 23:01     ` Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 06/47] drm/i915/guc: Optimize CTB writes and reads Matthew Brost
2021-06-25 13:09   ` Michal Wajdeczko
2021-06-25 18:26     ` Matthew Brost
2021-06-25 20:28     ` Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 07/47] drm/i915/guc: Module load failure test for CT buffer creation Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 08/47] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost
2021-06-29 21:11   ` John Harrison
2021-06-30  0:30     ` Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 09/47] drm/i915/guc: Remove GuC stage descriptor, add lrc descriptor Matthew Brost
2021-06-25 19:44   ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 10/47] drm/i915/guc: Add lrc descriptor context lookup array Matthew Brost
2021-06-25 13:17   ` Michal Wajdeczko
2021-06-25 17:26     ` Matthew Brost
2021-06-29 21:20       ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 11/47] drm/i915/guc: Implement GuC submission tasklet Matthew Brost
2021-06-29 22:04   ` John Harrison
2021-06-30  0:41     ` Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 12/47] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost
2021-06-29 22:09   ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 13/47] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost
2021-06-25 13:25   ` Michal Wajdeczko
2021-06-25 17:46     ` Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 14/47] drm/i915/guc: Insert fence on context when deregistering Matthew Brost
2021-07-09 22:39   ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 15/47] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost
2021-07-09 22:48   ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 16/47] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost
2021-07-09 22:53   ` John Harrison
2021-07-10  3:00     ` Matthew Brost
2021-07-12 17:57       ` John Harrison
2021-07-12 18:11         ` Daniel Vetter
2021-06-24  7:04 ` [Intel-gfx] [PATCH 17/47] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost
2021-07-09 22:59   ` John Harrison
2021-07-10  3:36     ` Matthew Brost
2021-07-12 17:54       ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 18/47] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost
2021-07-09 23:03   ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 19/47] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost
2021-07-15  1:51   ` Daniele Ceraolo Spurio
2021-06-24  7:04 ` [Intel-gfx] [PATCH 20/47] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost
2021-07-09 23:53   ` John Harrison
2021-07-15  0:07     ` Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 21/47] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost
2021-07-13 18:36   ` John Harrison
2021-07-15  0:06     ` Matthew Brost
2021-07-15  0:12       ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 22/47] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost
2021-07-10  0:16   ` John Harrison
2021-07-10  3:55     ` Matthew Brost
2021-07-17  4:09       ` Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 23/47] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost
2021-07-12 18:05   ` John Harrison
2021-07-12 20:59     ` Matthew Brost
2021-07-12 21:37       ` John Harrison
2021-07-13  8:51   ` Michal Wajdeczko
2021-07-14 23:56     ` Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 24/47] drm/i915/guc: Add several request trace points Matthew Brost
2021-07-12 18:08   ` John Harrison
2021-07-13  9:06   ` Tvrtko Ursulin
2021-07-20  1:59     ` Matthew Brost
2021-07-22 13:55       ` Tvrtko Ursulin
2021-06-24  7:04 ` [Intel-gfx] [PATCH 25/47] drm/i915: Add intel_context tracing Matthew Brost
2021-07-12 18:10   ` John Harrison
2021-07-12 21:47     ` Matthew Brost
2021-07-12 21:51       ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 26/47] drm/i915/guc: GuC virtual engines Matthew Brost
2021-07-15  1:21   ` Daniele Ceraolo Spurio
2021-06-24  7:04 ` [Intel-gfx] [PATCH 27/47] drm/i915: Track 'serial' counts for " Matthew Brost
2021-07-12 18:11   ` John Harrison
2021-07-12 20:06     ` Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 28/47] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost
2021-07-12 18:23   ` John Harrison
2021-07-12 20:05     ` Matthew Brost
2021-07-12 21:36       ` Matthew Brost
2021-07-12 21:48         ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 29/47] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost
2021-07-12 18:23   ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 30/47] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost
2021-07-12 19:19   ` John Harrison
2021-06-24  7:05 ` [Intel-gfx] [PATCH 31/47] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost
2021-07-12 19:58   ` John Harrison
2021-07-15  0:53     ` Matthew Brost
2021-07-15  9:36   ` Tvrtko Ursulin
2021-07-26 22:48     ` Matthew Brost
2021-07-27  8:56       ` Tvrtko Ursulin
2021-07-27 18:30         ` Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 32/47] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost
2021-07-12 20:01   ` John Harrison
2021-06-24  7:05 ` [Intel-gfx] [PATCH 33/47] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost
2021-07-12 20:11   ` John Harrison
2021-06-24  7:05 ` [Intel-gfx] [PATCH 34/47] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost
2021-07-12 22:56   ` John Harrison
2021-06-24  7:05 ` [Intel-gfx] [PATCH 35/47] drm/i915/guc: Handle context reset notification Matthew Brost
2021-07-12 22:58   ` John Harrison
2021-07-15  0:32     ` Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 36/47] drm/i915/guc: Handle engine reset failure notification Matthew Brost
2021-07-12 22:59   ` John Harrison
2021-06-24  7:05 ` [Intel-gfx] [PATCH 37/47] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost
2021-07-12 23:00   ` John Harrison
2021-06-24  7:05 ` [Intel-gfx] [PATCH 38/47] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 39/47] drm/i915/guc: Don't complain about reset races Matthew Brost
2021-06-24 15:55   ` Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 40/47] drm/i915/guc: Enable GuC engine reset Matthew Brost
2021-06-24 16:19   ` Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 41/47] drm/i915/guc: Capture error state on context reset Matthew Brost
2021-07-12 23:05   ` John Harrison
2021-06-24  7:05 ` [Intel-gfx] [PATCH 42/47] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost
2021-07-15  0:43   ` Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 43/47] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost
2021-06-25  0:59   ` Matthew Brost
2021-06-25 19:10     ` John Harrison
2021-07-10 18:56       ` Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 44/47] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost
2021-06-25  1:10   ` Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 45/47] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost
2021-06-24 16:34   ` Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 46/47] drm/i915/guc: Add golden context to GuC ADS Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 47/47] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost
2021-06-30  8:22   ` Martin Peres
2021-06-30 18:00     ` Matthew Brost
2021-07-01 18:24       ` Martin Peres
2021-07-02  8:13         ` Martin Peres
2021-07-02 13:06           ` Michal Wajdeczko
2021-07-02 13:12             ` Martin Peres
2021-07-02 14:08               ` Michal Wajdeczko
2021-06-30 18:58     ` John Harrison
2021-07-01  8:14       ` Pekka Paalanen
2021-07-01 18:27         ` Martin Peres
2021-07-01 19:28           ` Daniel Vetter
2021-07-02  7:29             ` Pekka Paalanen
2021-07-02  8:09               ` Martin Peres
2021-07-02 15:07                 ` Michal Wajdeczko
2021-07-03  8:21                   ` Martin Peres
2021-07-07  0:57                     ` John Harrison
2021-07-07  7:47                       ` Pekka Paalanen
2021-07-07 10:11                       ` Michal Wajdeczko
2021-07-15  0:49   ` Matthew Brost
2021-06-24  7:17 ` Patchwork [this message]
2021-06-24  7:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for GuC submission support Patchwork
2021-06-24  7:47 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-07-12 19:23 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for GuC submission support (rev2) Patchwork
2021-10-22  9:35 ` [Intel-gfx] [PATCH 00/47] GuC submission support Joonas Lahtinen
2021-10-22 16:42   ` Matthew Brost
2021-10-25  9:37     ` Joonas Lahtinen
2021-10-25 15:15       ` Matthew Brost
2021-10-26  8:59         ` Joonas Lahtinen
2021-10-26 15:43           ` Matthew Brost
2021-10-26 15:51           ` Matthew Brost
2021-10-27  9:21             ` Joonas Lahtinen
2021-10-25 17:06       ` John Harrison

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