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* [Intel-gfx] [PATCH 0/6] Forcewake and shadowed register updates
@ 2021-07-29  5:41 Matt Roper
  2021-07-29  5:41 ` [Intel-gfx] [PATCH 1/6] drm/i915: correct name of GT forcewake domain in error messages Matt Roper
                   ` (11 more replies)
  0 siblings, 12 replies; 22+ messages in thread
From: Matt Roper @ 2021-07-29  5:41 UTC (permalink / raw)
  To: intel-gfx

Update the way we handle shadowed registers (i.e., registers that we can
write to without grabbing forcewake first) to support register ranges
rather than just single registers, and add some missing registers for
gen11, gen12, and Xe_HP.

While we're working in this area of the code, let's also adjust the
description of the GT domain in error messages (referring to it as
'blitter' just confuses people) and eliminate some unnecessary
duplication of forcewake read functions.


Matt Roper (6):
  drm/i915: correct name of GT forcewake domain in error messages
  drm/i915: Re-use gen11 forcewake read functions on gen12
  drm/i915: Make shadow tables range-based
  drm/i915/gen11: Update shadowed register table
  drm/i915/gen12: Update shadowed register table
  drm/i915/xehp: Xe_HP shadowed registers are a strict superset of gen12

 drivers/gpu/drm/i915/gt/intel_workarounds.c   |  13 +-
 drivers/gpu/drm/i915/intel_uncore.c           | 185 ++++++++----------
 drivers/gpu/drm/i915/intel_uncore.h           |   6 +
 drivers/gpu/drm/i915/selftests/intel_uncore.c |  33 ++--
 4 files changed, 111 insertions(+), 126 deletions(-)

-- 
2.25.4

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^ permalink raw reply	[flat|nested] 22+ messages in thread

* [Intel-gfx] [PATCH 1/6] drm/i915: correct name of GT forcewake domain in error messages
  2021-07-29  5:41 [Intel-gfx] [PATCH 0/6] Forcewake and shadowed register updates Matt Roper
@ 2021-07-29  5:41 ` Matt Roper
  2021-07-29 14:13   ` Yokoyama, Caz
  2021-07-29  5:41 ` [Intel-gfx] [PATCH 2/6] drm/i915: Re-use gen11 forcewake read functions on gen12 Matt Roper
                   ` (10 subsequent siblings)
  11 siblings, 1 reply; 22+ messages in thread
From: Matt Roper @ 2021-07-29  5:41 UTC (permalink / raw)
  To: intel-gfx

For historical reasons, the GT forcewake domain used to be referred to
as the "blitter" domain; that name is no longer accurate since the GT
domain contains a lot of additional registers and functionality besides
just the blitter.  Although we renamed the domain in the driver in
commit 55e3c170950f ("drm/i915: Rename FORCEWAKE_BLITTER to
FORCEWAKE_GT"), we neglected to update the string that gets printed in
driver error messages; let's do that now to avoid confusion.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 8cf53f54559d..bca548c81572 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -64,7 +64,7 @@ static void mmio_debug_resume(struct intel_uncore_mmio_debug *mmio_debug)
 
 static const char * const forcewake_domain_names[] = {
 	"render",
-	"blitter",
+	"gt",
 	"media",
 	"vdbox0",
 	"vdbox1",
-- 
2.25.4

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^ permalink raw reply	[flat|nested] 22+ messages in thread

* [Intel-gfx] [PATCH 2/6] drm/i915: Re-use gen11 forcewake read functions on gen12
  2021-07-29  5:41 [Intel-gfx] [PATCH 0/6] Forcewake and shadowed register updates Matt Roper
  2021-07-29  5:41 ` [Intel-gfx] [PATCH 1/6] drm/i915: correct name of GT forcewake domain in error messages Matt Roper
@ 2021-07-29  5:41 ` Matt Roper
  2021-07-29 21:02   ` Yokoyama, Caz
  2021-07-29  5:41 ` [Intel-gfx] [PATCH 3/6] drm/i915: Make shadow tables range-based Matt Roper
                   ` (9 subsequent siblings)
  11 siblings, 1 reply; 22+ messages in thread
From: Matt Roper @ 2021-07-29  5:41 UTC (permalink / raw)
  To: intel-gfx

The forcewake read logic is identical between gen11 and gen12, only the
forcewake table data (which is tracked separately) differs; there's no
need to generate a separate set of gen12 read functions when the gen11
functions will work just as well.

We'll keep the separate write functions for now since the generated code
directly references different shadow tables between the two platforms.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index bca548c81572..ea910f7ee635 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -945,9 +945,6 @@ static const struct intel_forcewake_range __vlv_fw_ranges[] = {
 #define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
 	find_fw_domain(uncore, offset)
 
-#define __gen12_fwtable_reg_read_fw_domains(uncore, offset) \
-	find_fw_domain(uncore, offset)
-
 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
 static const i915_reg_t gen8_shadowed_regs[] = {
 	RING_TAIL(RENDER_RING_BASE),	/* 0x2000 (base) */
@@ -1617,7 +1614,6 @@ __gen_read(func, 16) \
 __gen_read(func, 32) \
 __gen_read(func, 64)
 
-__gen_reg_read_funcs(gen12_fwtable);
 __gen_reg_read_funcs(gen11_fwtable);
 __gen_reg_read_funcs(fwtable);
 __gen_reg_read_funcs(gen6);
@@ -2091,7 +2087,7 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
 	} else if (GRAPHICS_VER(i915) >= 12) {
 		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);
-		ASSIGN_READ_MMIO_VFUNCS(uncore, gen12_fwtable);
+		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
 	} else if (GRAPHICS_VER(i915) == 11) {
 		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable);
-- 
2.25.4

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^ permalink raw reply	[flat|nested] 22+ messages in thread

* [Intel-gfx] [PATCH 3/6] drm/i915: Make shadow tables range-based
  2021-07-29  5:41 [Intel-gfx] [PATCH 0/6] Forcewake and shadowed register updates Matt Roper
  2021-07-29  5:41 ` [Intel-gfx] [PATCH 1/6] drm/i915: correct name of GT forcewake domain in error messages Matt Roper
  2021-07-29  5:41 ` [Intel-gfx] [PATCH 2/6] drm/i915: Re-use gen11 forcewake read functions on gen12 Matt Roper
@ 2021-07-29  5:41 ` Matt Roper
  2021-07-29 15:21   ` [Intel-gfx] [PATCH v2 " Matt Roper
  2021-07-29  5:41 ` [Intel-gfx] [PATCH 4/6] drm/i915/gen11: Update shadowed register table Matt Roper
                   ` (8 subsequent siblings)
  11 siblings, 1 reply; 22+ messages in thread
From: Matt Roper @ 2021-07-29  5:41 UTC (permalink / raw)
  To: intel-gfx

Rather than defining our shadow tables as a list of individual
registers, provide them as a list of register ranges; we'll have some
ranges of multiple registers being added soon (and we already have a
couple adjacent registers that we can squash into a single range now).

This change also defines the table with hex literal values rather than
symbolic register names; since that's how the tables are defined in the
bspec, this change should make it easier to review the tables overall.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |  13 +-
 drivers/gpu/drm/i915/intel_uncore.c           | 160 +++++++++---------
 drivers/gpu/drm/i915/intel_uncore.h           |   6 +
 drivers/gpu/drm/i915/selftests/intel_uncore.c |  32 ++--
 4 files changed, 108 insertions(+), 103 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 9173df59821a..7558414bafb2 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1963,12 +1963,7 @@ void intel_engine_apply_workarounds(struct intel_engine_cs *engine)
 	wa_list_apply(engine->gt, &engine->wa_list);
 }
 
-struct mcr_range {
-	u32 start;
-	u32 end;
-};
-
-static const struct mcr_range mcr_ranges_gen8[] = {
+static const struct i915_range mcr_ranges_gen8[] = {
 	{ .start = 0x5500, .end = 0x55ff },
 	{ .start = 0x7000, .end = 0x7fff },
 	{ .start = 0x9400, .end = 0x97ff },
@@ -1977,7 +1972,7 @@ static const struct mcr_range mcr_ranges_gen8[] = {
 	{},
 };
 
-static const struct mcr_range mcr_ranges_gen12[] = {
+static const struct i915_range mcr_ranges_gen12[] = {
 	{ .start =  0x8150, .end =  0x815f },
 	{ .start =  0x9520, .end =  0x955f },
 	{ .start =  0xb100, .end =  0xb3ff },
@@ -1986,7 +1981,7 @@ static const struct mcr_range mcr_ranges_gen12[] = {
 	{},
 };
 
-static const struct mcr_range mcr_ranges_xehp[] = {
+static const struct i915_range mcr_ranges_xehp[] = {
 	{ .start =  0x4000, .end =  0x4aff },
 	{ .start =  0x5200, .end =  0x52ff },
 	{ .start =  0x5400, .end =  0x7fff },
@@ -2004,7 +1999,7 @@ static const struct mcr_range mcr_ranges_xehp[] = {
 
 static bool mcr_range(struct drm_i915_private *i915, u32 offset)
 {
-	const struct mcr_range *mcr_ranges;
+	const struct i915_range *mcr_ranges;
 	int i;
 
 	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index ea910f7ee635..2cfbc16f7dee 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -946,101 +946,95 @@ static const struct intel_forcewake_range __vlv_fw_ranges[] = {
 	find_fw_domain(uncore, offset)
 
 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
-static const i915_reg_t gen8_shadowed_regs[] = {
-	RING_TAIL(RENDER_RING_BASE),	/* 0x2000 (base) */
-	GEN6_RPNSWREQ,			/* 0xA008 */
-	GEN6_RC_VIDEO_FREQ,		/* 0xA00C */
-	RING_TAIL(GEN6_BSD_RING_BASE),	/* 0x12000 (base) */
-	RING_TAIL(VEBOX_RING_BASE),	/* 0x1a000 (base) */
-	RING_TAIL(BLT_RING_BASE),	/* 0x22000 (base) */
+static const struct i915_range gen8_shadowed_regs[] = {
+	{ .start =  0x2030, .end =  0x2030 },
+	{ .start =  0xA008, .end =  0xA00C },
+	{ .start = 0x12030, .end = 0x12030 },
+	{ .start = 0x1a030, .end = 0x1a030 },
+	{ .start = 0x22030, .end = 0x22030 },
 	/* TODO: Other registers are not yet used */
 };
 
-static const i915_reg_t gen11_shadowed_regs[] = {
-	RING_TAIL(RENDER_RING_BASE),			/* 0x2000 (base) */
-	RING_EXECLIST_CONTROL(RENDER_RING_BASE),        /* 0x2550 */
-	GEN6_RPNSWREQ,					/* 0xA008 */
-	GEN6_RC_VIDEO_FREQ,				/* 0xA00C */
-	RING_TAIL(BLT_RING_BASE),			/* 0x22000 (base) */
-	RING_EXECLIST_CONTROL(BLT_RING_BASE),		/* 0x22550 */
-	RING_TAIL(GEN11_BSD_RING_BASE),			/* 0x1C0000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE),	/* 0x1C0550 */
-	RING_TAIL(GEN11_BSD2_RING_BASE),		/* 0x1C4000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE),	/* 0x1C4550 */
-	RING_TAIL(GEN11_VEBOX_RING_BASE),		/* 0x1C8000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE),	/* 0x1C8550 */
-	RING_TAIL(GEN11_BSD3_RING_BASE),		/* 0x1D0000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE),	/* 0x1D0550 */
-	RING_TAIL(GEN11_BSD4_RING_BASE),		/* 0x1D4000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE),	/* 0x1D4550 */
-	RING_TAIL(GEN11_VEBOX2_RING_BASE),		/* 0x1D8000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE),	/* 0x1D8550 */
+static const struct i915_range gen11_shadowed_regs[] = {
+	{ .start =   0x2030, .end =   0x2030 },
+	{ .start =   0x2550, .end =   0x2550 },
+	{ .start =   0xA008, .end =   0xA00C },
+	{ .start =  0x22030, .end =  0x22030 },
+	{ .start =  0x22550, .end =  0x22550 },
+	{ .start = 0x1C0030, .end = 0x1C0030 },
+	{ .start = 0x1C0550, .end = 0x1C0550 },
+	{ .start = 0x1C4030, .end = 0x1C4030 },
+	{ .start = 0x1C4550, .end = 0x1C4550 },
+	{ .start = 0x1C8030, .end = 0x1C8030 },
+	{ .start = 0x1C8550, .end = 0x1C8550 },
+	{ .start = 0x1D0030, .end = 0x1D0030 },
+	{ .start = 0x1D0550, .end = 0x1D0550 },
+	{ .start = 0x1D4030, .end = 0x1D4030 },
+	{ .start = 0x1D4550, .end = 0x1D4550 },
+	{ .start = 0x1D8030, .end = 0x1D8030 },
+	{ .start = 0x1D8550, .end = 0x1D8550 },
 	/* TODO: Other registers are not yet used */
 };
 
-static const i915_reg_t gen12_shadowed_regs[] = {
-	RING_TAIL(RENDER_RING_BASE),			/* 0x2000 (base) */
-	RING_EXECLIST_CONTROL(RENDER_RING_BASE),	/* 0x2550 */
-	GEN6_RPNSWREQ,					/* 0xA008 */
-	GEN6_RC_VIDEO_FREQ,				/* 0xA00C */
-	RING_TAIL(BLT_RING_BASE),			/* 0x22000 (base) */
-	RING_EXECLIST_CONTROL(BLT_RING_BASE),		/* 0x22550 */
-	RING_TAIL(GEN11_BSD_RING_BASE),			/* 0x1C0000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE),	/* 0x1C0550 */
-	RING_TAIL(GEN11_BSD2_RING_BASE),		/* 0x1C4000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE),	/* 0x1C4550 */
-	RING_TAIL(GEN11_VEBOX_RING_BASE),		/* 0x1C8000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE),	/* 0x1C8550 */
-	RING_TAIL(GEN11_BSD3_RING_BASE),		/* 0x1D0000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE),	/* 0x1D0550 */
-	RING_TAIL(GEN11_BSD4_RING_BASE),		/* 0x1D4000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE),	/* 0x1D4550 */
-	RING_TAIL(GEN11_VEBOX2_RING_BASE),		/* 0x1D8000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE),	/* 0x1D8550 */
+static const struct i915_range gen12_shadowed_regs[] = {
+	{ .start =   0x2030, .end =   0x2030 },
+	{ .start =   0x2550, .end =   0x2550 },
+	{ .start =   0xA008, .end =   0xA00C },
+	{ .start =  0x22030, .end =  0x22030 },
+	{ .start =  0x22550, .end =  0x22550 },
+	{ .start = 0x1C0030, .end = 0x1C0030 },
+	{ .start = 0x1C0550, .end = 0x1C0550 },
+	{ .start = 0x1C4030, .end = 0x1C4030 },
+	{ .start = 0x1C4550, .end = 0x1C4550 },
+	{ .start = 0x1C8030, .end = 0x1C8030 },
+	{ .start = 0x1C8550, .end = 0x1C8550 },
+	{ .start = 0x1D0030, .end = 0x1D0030 },
+	{ .start = 0x1D0550, .end = 0x1D0550 },
+	{ .start = 0x1D4030, .end = 0x1D4030 },
+	{ .start = 0x1D4550, .end = 0x1D4550 },
+	{ .start = 0x1D8030, .end = 0x1D8030 },
+	{ .start = 0x1D8550, .end = 0x1D8550 },
 	/* TODO: Other registers are not yet used */
 };
 
-static const i915_reg_t xehp_shadowed_regs[] = {
-	RING_TAIL(RENDER_RING_BASE),			/* 0x2000 (base) */
-	RING_EXECLIST_CONTROL(RENDER_RING_BASE),        /* 0x2550 */
-	GEN6_RPNSWREQ,					/* 0xA008 */
-	GEN6_RC_VIDEO_FREQ,				/* 0xA00C */
-	RING_TAIL(BLT_RING_BASE),			/* 0x22000 (base) */
-	RING_EXECLIST_CONTROL(BLT_RING_BASE),		/* 0x22550 */
-	RING_TAIL(GEN11_BSD_RING_BASE),			/* 0x1C0000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE),	/* 0x1C0550 */
-	RING_TAIL(GEN11_BSD2_RING_BASE),		/* 0x1C4000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE),	/* 0x1C4550 */
-	RING_TAIL(GEN11_VEBOX_RING_BASE),		/* 0x1C8000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE),	/* 0x1C8550 */
-	RING_TAIL(GEN11_BSD3_RING_BASE),		/* 0x1D0000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE),	/* 0x1D0550 */
-	RING_TAIL(GEN11_BSD4_RING_BASE),		/* 0x1D4000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE),	/* 0x1D4550 */
-	RING_TAIL(GEN11_VEBOX2_RING_BASE),		/* 0x1D8000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE),	/* 0x1D8550 */
-	RING_TAIL(XEHP_BSD5_RING_BASE),			/* 0x1E0000 (base) */
-	RING_EXECLIST_CONTROL(XEHP_BSD5_RING_BASE),	/* 0x1E0550 */
-	RING_TAIL(XEHP_BSD6_RING_BASE),			/* 0x1E4000 (base) */
-	RING_EXECLIST_CONTROL(XEHP_BSD6_RING_BASE),	/* 0x1E4550 */
-	RING_TAIL(XEHP_VEBOX3_RING_BASE),		/* 0x1E8000 (base) */
-	RING_EXECLIST_CONTROL(XEHP_VEBOX3_RING_BASE),	/* 0x1E8550 */
-	RING_TAIL(XEHP_BSD7_RING_BASE),			/* 0x1F0000 (base) */
-	RING_EXECLIST_CONTROL(XEHP_BSD7_RING_BASE),	/* 0x1F0550 */
-	RING_TAIL(XEHP_BSD8_RING_BASE),			/* 0x1F4000 (base) */
-	RING_EXECLIST_CONTROL(XEHP_BSD8_RING_BASE),	/* 0x1F4550 */
-	RING_TAIL(XEHP_VEBOX4_RING_BASE),		/* 0x1F8000 (base) */
-	RING_EXECLIST_CONTROL(XEHP_VEBOX4_RING_BASE),	/* 0x1F8550 */
+static const struct i915_range xehp_shadowed_regs[] = {
+	{ .start =   0x2000, .end =   0x2030 },
+	{ .start =   0x2550, .end =   0x2550 },
+	{ .start =   0xA008, .end =   0xA00C },
+	{ .start =  0x22030, .end =  0x22030 },
+	{ .start =  0x22550, .end =  0x22550 },
+	{ .start = 0x1C0030, .end = 0x1C0030 },
+	{ .start = 0x1C0550, .end = 0x1C0550 },
+	{ .start = 0x1C4030, .end = 0x1C4030 },
+	{ .start = 0x1C4550, .end = 0x1C4550 },
+	{ .start = 0x1C8030, .end = 0x1C8030 },
+	{ .start = 0x1C8550, .end = 0x1C8550 },
+	{ .start = 0x1D0030, .end = 0x1D0030 },
+	{ .start = 0x1D0550, .end = 0x1D0550 },
+	{ .start = 0x1D4030, .end = 0x1D4030 },
+	{ .start = 0x1D4550, .end = 0x1D4550 },
+	{ .start = 0x1D8030, .end = 0x1D8030 },
+	{ .start = 0x1D8550, .end = 0x1D8550 },
+	{ .start = 0x1E0030, .end = 0x1E0030 },
+	{ .start = 0x1E0550, .end = 0x1E0550 },
+	{ .start = 0x1E4030, .end = 0x1E4030 },
+	{ .start = 0x1E4550, .end = 0x1E4550 },
+	{ .start = 0x1E8030, .end = 0x1E8030 },
+	{ .start = 0x1E8550, .end = 0x1E8550 },
+	{ .start = 0x1F0030, .end = 0x1F0030 },
+	{ .start = 0x1F0550, .end = 0x1F0550 },
+	{ .start = 0x1F4030, .end = 0x1F4030 },
+	{ .start = 0x1F4550, .end = 0x1F4550 },
+	{ .start = 0x1F8030, .end = 0x1F8030 },
+	{ .start = 0x1F8550, .end = 0x1F8550 },
 	/* TODO: Other registers are not yet used */
 };
 
-static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
+static int mmio_range_cmp(u32 key, const struct i915_range *range)
 {
-	u32 offset = i915_mmio_reg_offset(*reg);
-
-	if (key < offset)
+	if (key < range->start)
 		return -1;
-	else if (key > offset)
+	else if (key > range->end)
 		return 1;
 	else
 		return 0;
@@ -1049,9 +1043,9 @@ static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
 #define __is_X_shadowed(x) \
 static bool is_##x##_shadowed(u32 offset) \
 { \
-	const i915_reg_t *regs = x##_shadowed_regs; \
+	const struct i915_range *regs = x##_shadowed_regs; \
 	return BSEARCH(offset, regs, ARRAY_SIZE(x##_shadowed_regs), \
-		       mmio_reg_cmp); \
+		       mmio_range_cmp); \
 }
 
 __is_X_shadowed(gen8)
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 3c0b0a8b5250..531665b08039 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -119,6 +119,12 @@ struct intel_forcewake_range {
 	enum forcewake_domains domains;
 };
 
+/* Other register ranges (e.g., shadow tables, MCR tables, etc.) */
+struct i915_range {
+	u32 start;
+	u32 end;
+};
+
 struct intel_uncore {
 	void __iomem *regs;
 
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index 720b60853f8b..d3e36ed32646 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -62,30 +62,40 @@ static int intel_fw_table_check(const struct intel_forcewake_range *ranges,
 static int intel_shadow_table_check(void)
 {
 	struct {
-		const i915_reg_t *regs;
+		const struct i915_range *regs;
 		unsigned int size;
-	} reg_lists[] = {
+	} range_lists[] = {
 		{ gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) },
 		{ gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
 		{ gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs) },
 		{ xehp_shadowed_regs, ARRAY_SIZE(xehp_shadowed_regs) },
 	};
-	const i915_reg_t *reg;
+	const struct i915_range *range;
 	unsigned int i, j;
 	s32 prev;
 
-	for (j = 0; j < ARRAY_SIZE(reg_lists); ++j) {
-		reg = reg_lists[j].regs;
-		for (i = 0, prev = -1; i < reg_lists[j].size; i++, reg++) {
-			u32 offset = i915_mmio_reg_offset(*reg);
+	for (j = 0; j < ARRAY_SIZE(range_lists); ++j) {
+		range = range_lists[j].regs;
+		for (i = 0, prev = -1; i < range_lists[j].size; i++, range++) {
+			if (range->end < range->start) {
+				pr_err("%s: range[%d]:(%06x-%06x) has end before start\n",
+				       __func__, i, range->start, range->end);
+				return -EINVAL;
+			}
+
+			if (prev >= range->start) {
+				pr_err("%s: range[%d]:(%06x-%06x) is before end of previous (%06x)\n",
+				       __func__, i, range->start, range->end, prev);
+				return -EINVAL;
+			}
 
-			if (prev >= (s32)offset) {
-				pr_err("%s: entry[%d]:(%x) is before previous (%x)\n",
-				       __func__, i, offset, prev);
+			if (range->start % 4) {
+				pr_err("%s: range[%d]:(%06x-%06x) has non-dword-aligned start\n",
+				       __func__, i, range->start, range->end);
 				return -EINVAL;
 			}
 
-			prev = offset;
+			prev = range->end;
 		}
 	}
 
-- 
2.25.4

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^ permalink raw reply	[flat|nested] 22+ messages in thread

* [Intel-gfx] [PATCH 4/6] drm/i915/gen11: Update shadowed register table
  2021-07-29  5:41 [Intel-gfx] [PATCH 0/6] Forcewake and shadowed register updates Matt Roper
                   ` (2 preceding siblings ...)
  2021-07-29  5:41 ` [Intel-gfx] [PATCH 3/6] drm/i915: Make shadow tables range-based Matt Roper
@ 2021-07-29  5:41 ` Matt Roper
  2021-08-10 22:03   ` Yokoyama, Caz
  2021-07-29  5:41 ` [Intel-gfx] [PATCH 5/6] drm/i915/gen12: " Matt Roper
                   ` (7 subsequent siblings)
  11 siblings, 1 reply; 22+ messages in thread
From: Matt Roper @ 2021-07-29  5:41 UTC (permalink / raw)
  To: intel-gfx

The bspec lists many shadowed registers (i.e., registers for which we
don't need to grab forcewake when writing) that we weren't tracking in
the driver.  Although we may not actually use all of these registers
right now, it's best to just match the bspec list exactly.

Note that the bspec also lists registers that are shadowed for various
HW-internal accesses; we can ignore those and just list the ones that
are shadowed for accesses from the IA/CPU.

Bspec: 18333
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 2cfbc16f7dee..31e0456dce5a 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -960,20 +960,26 @@ static const struct i915_range gen11_shadowed_regs[] = {
 	{ .start =   0x2550, .end =   0x2550 },
 	{ .start =   0xA008, .end =   0xA00C },
 	{ .start =  0x22030, .end =  0x22030 },
-	{ .start =  0x22550, .end =  0x22550 },
+	{ .start =  0x22230, .end =  0x22230 },
+	{ .start =  0x22510, .end =  0x22550 },
 	{ .start = 0x1C0030, .end = 0x1C0030 },
-	{ .start = 0x1C0550, .end = 0x1C0550 },
+	{ .start = 0x1C0230, .end = 0x1C0230 },
+	{ .start = 0x1C0510, .end = 0x1C0550 },
 	{ .start = 0x1C4030, .end = 0x1C4030 },
-	{ .start = 0x1C4550, .end = 0x1C4550 },
+	{ .start = 0x1C4230, .end = 0x1C4230 },
+	{ .start = 0x1C4510, .end = 0x1C4550 },
 	{ .start = 0x1C8030, .end = 0x1C8030 },
-	{ .start = 0x1C8550, .end = 0x1C8550 },
+	{ .start = 0x1C8230, .end = 0x1C8230 },
+	{ .start = 0x1C8510, .end = 0x1C8550 },
 	{ .start = 0x1D0030, .end = 0x1D0030 },
-	{ .start = 0x1D0550, .end = 0x1D0550 },
+	{ .start = 0x1D0230, .end = 0x1D0230 },
+	{ .start = 0x1D0510, .end = 0x1D0550 },
 	{ .start = 0x1D4030, .end = 0x1D4030 },
-	{ .start = 0x1D4550, .end = 0x1D4550 },
+	{ .start = 0x1D4230, .end = 0x1D4230 },
+	{ .start = 0x1D4510, .end = 0x1D4550 },
 	{ .start = 0x1D8030, .end = 0x1D8030 },
-	{ .start = 0x1D8550, .end = 0x1D8550 },
-	/* TODO: Other registers are not yet used */
+	{ .start = 0x1D8230, .end = 0x1D8230 },
+	{ .start = 0x1D8510, .end = 0x1D8550 },
 };
 
 static const struct i915_range gen12_shadowed_regs[] = {
-- 
2.25.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 22+ messages in thread

* [Intel-gfx] [PATCH 5/6] drm/i915/gen12: Update shadowed register table
  2021-07-29  5:41 [Intel-gfx] [PATCH 0/6] Forcewake and shadowed register updates Matt Roper
                   ` (3 preceding siblings ...)
  2021-07-29  5:41 ` [Intel-gfx] [PATCH 4/6] drm/i915/gen11: Update shadowed register table Matt Roper
@ 2021-07-29  5:41 ` Matt Roper
  2021-08-10 22:04   ` Yokoyama, Caz
  2021-07-29  5:41 ` [Intel-gfx] [PATCH 6/6] drm/i915/xehp: Xe_HP shadowed registers are a strict superset of gen12 Matt Roper
                   ` (6 subsequent siblings)
  11 siblings, 1 reply; 22+ messages in thread
From: Matt Roper @ 2021-07-29  5:41 UTC (permalink / raw)
  To: intel-gfx

The bspec lists many shadowed registers (i.e., registers for which we
don't need to grab forcewake when writing) that we weren't tracking in
the driver.  Although we may not actually use all of these registers
right now, it's best to just match the bspec list exactly.

Note that the bspec also lists registers that are shadowed for various
HW-internal accesses; we can ignore those and just list the ones that
are shadowed for accesses from the IA/CPU.

Bspec: 52077
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 23 ++++++++++++++---------
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 31e0456dce5a..42acf106a6df 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -984,23 +984,28 @@ static const struct i915_range gen11_shadowed_regs[] = {
 
 static const struct i915_range gen12_shadowed_regs[] = {
 	{ .start =   0x2030, .end =   0x2030 },
-	{ .start =   0x2550, .end =   0x2550 },
+	{ .start =   0x2510, .end =   0x2550 },
 	{ .start =   0xA008, .end =   0xA00C },
+	{ .start =   0xA188, .end =   0xA188 },
+	{ .start =   0xA278, .end =   0xA278 },
+	{ .start =   0xA540, .end =   0xA56C },
+	{ .start =   0xC4C8, .end =   0xC4C8 },
+	{ .start =   0xC4D4, .end =   0xC4D4 },
+	{ .start =   0xC600, .end =   0xC600 },
 	{ .start =  0x22030, .end =  0x22030 },
-	{ .start =  0x22550, .end =  0x22550 },
+	{ .start =  0x22510, .end =  0x22550 },
 	{ .start = 0x1C0030, .end = 0x1C0030 },
-	{ .start = 0x1C0550, .end = 0x1C0550 },
+	{ .start = 0x1C0510, .end = 0x1C0550 },
 	{ .start = 0x1C4030, .end = 0x1C4030 },
-	{ .start = 0x1C4550, .end = 0x1C4550 },
+	{ .start = 0x1C4510, .end = 0x1C4550 },
 	{ .start = 0x1C8030, .end = 0x1C8030 },
-	{ .start = 0x1C8550, .end = 0x1C8550 },
+	{ .start = 0x1C8510, .end = 0x1C8550 },
 	{ .start = 0x1D0030, .end = 0x1D0030 },
-	{ .start = 0x1D0550, .end = 0x1D0550 },
+	{ .start = 0x1D0510, .end = 0x1D0550 },
 	{ .start = 0x1D4030, .end = 0x1D4030 },
-	{ .start = 0x1D4550, .end = 0x1D4550 },
+	{ .start = 0x1D4510, .end = 0x1D4550 },
 	{ .start = 0x1D8030, .end = 0x1D8030 },
-	{ .start = 0x1D8550, .end = 0x1D8550 },
-	/* TODO: Other registers are not yet used */
+	{ .start = 0x1D8510, .end = 0x1D8550 },
 };
 
 static const struct i915_range xehp_shadowed_regs[] = {
-- 
2.25.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 22+ messages in thread

* [Intel-gfx] [PATCH 6/6] drm/i915/xehp: Xe_HP shadowed registers are a strict superset of gen12
  2021-07-29  5:41 [Intel-gfx] [PATCH 0/6] Forcewake and shadowed register updates Matt Roper
                   ` (4 preceding siblings ...)
  2021-07-29  5:41 ` [Intel-gfx] [PATCH 5/6] drm/i915/gen12: " Matt Roper
@ 2021-07-29  5:41 ` Matt Roper
  2021-07-29 23:36   ` Yokoyama, Caz
  2021-07-29  6:09 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Forcewake and shadowed register updates Patchwork
                   ` (5 subsequent siblings)
  11 siblings, 1 reply; 22+ messages in thread
From: Matt Roper @ 2021-07-29  5:41 UTC (permalink / raw)
  To: intel-gfx

The list of shadowed registers on XeHP is identical to the set for
earlier gen12 platforms, with additional ranges added for the new VCS
and VECS engines.  Since those register ranges were reserved on earlier
gen12 platforms, it's safe to consolidate to a single gen12 table
rather than tracking Xe_HP separately.

Bspec: 52077
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c           | 50 +++++--------------
 drivers/gpu/drm/i915/selftests/intel_uncore.c |  1 -
 2 files changed, 12 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 42acf106a6df..4abe9df5fb76 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1006,39 +1006,24 @@ static const struct i915_range gen12_shadowed_regs[] = {
 	{ .start = 0x1D4510, .end = 0x1D4550 },
 	{ .start = 0x1D8030, .end = 0x1D8030 },
 	{ .start = 0x1D8510, .end = 0x1D8550 },
-};
 
-static const struct i915_range xehp_shadowed_regs[] = {
-	{ .start =   0x2000, .end =   0x2030 },
-	{ .start =   0x2550, .end =   0x2550 },
-	{ .start =   0xA008, .end =   0xA00C },
-	{ .start =  0x22030, .end =  0x22030 },
-	{ .start =  0x22550, .end =  0x22550 },
-	{ .start = 0x1C0030, .end = 0x1C0030 },
-	{ .start = 0x1C0550, .end = 0x1C0550 },
-	{ .start = 0x1C4030, .end = 0x1C4030 },
-	{ .start = 0x1C4550, .end = 0x1C4550 },
-	{ .start = 0x1C8030, .end = 0x1C8030 },
-	{ .start = 0x1C8550, .end = 0x1C8550 },
-	{ .start = 0x1D0030, .end = 0x1D0030 },
-	{ .start = 0x1D0550, .end = 0x1D0550 },
-	{ .start = 0x1D4030, .end = 0x1D4030 },
-	{ .start = 0x1D4550, .end = 0x1D4550 },
-	{ .start = 0x1D8030, .end = 0x1D8030 },
-	{ .start = 0x1D8550, .end = 0x1D8550 },
+	/*
+	 * The rest of these ranges are specific to Xe_HP and beyond, but
+	 * are reserved/unused ranges on earlier gen12 platforms, so they can
+	 * be safely added to the gen12 table.
+	 */
 	{ .start = 0x1E0030, .end = 0x1E0030 },
-	{ .start = 0x1E0550, .end = 0x1E0550 },
+	{ .start = 0x1E0510, .end = 0x1E0550 },
 	{ .start = 0x1E4030, .end = 0x1E4030 },
-	{ .start = 0x1E4550, .end = 0x1E4550 },
+	{ .start = 0x1E4510, .end = 0x1E4550 },
 	{ .start = 0x1E8030, .end = 0x1E8030 },
-	{ .start = 0x1E8550, .end = 0x1E8550 },
+	{ .start = 0x1E8510, .end = 0x1E8550 },
 	{ .start = 0x1F0030, .end = 0x1F0030 },
-	{ .start = 0x1F0550, .end = 0x1F0550 },
+	{ .start = 0x1F0510, .end = 0x1F0550 },
 	{ .start = 0x1F4030, .end = 0x1F4030 },
-	{ .start = 0x1F4550, .end = 0x1F4550 },
+	{ .start = 0x1F4510, .end = 0x1F4550 },
 	{ .start = 0x1F8030, .end = 0x1F8030 },
-	{ .start = 0x1F8550, .end = 0x1F8550 },
-	/* TODO: Other registers are not yet used */
+	{ .start = 0x1F8510, .end = 0x1F8550 },
 };
 
 static int mmio_range_cmp(u32 key, const struct i915_range *range)
@@ -1062,7 +1047,6 @@ static bool is_##x##_shadowed(u32 offset) \
 __is_X_shadowed(gen8)
 __is_X_shadowed(gen11)
 __is_X_shadowed(gen12)
-__is_X_shadowed(xehp)
 
 static enum forcewake_domains
 gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
@@ -1126,15 +1110,6 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = {
 	__fwd; \
 })
 
-#define __xehp_fwtable_reg_write_fw_domains(uncore, offset) \
-({ \
-	enum forcewake_domains __fwd = 0; \
-	const u32 __offset = (offset); \
-	if (!is_xehp_shadowed(__offset)) \
-		__fwd = find_fw_domain(uncore, __offset); \
-	__fwd; \
-})
-
 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
 	GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT),
@@ -1710,7 +1685,6 @@ __gen_write(func, 8) \
 __gen_write(func, 16) \
 __gen_write(func, 32)
 
-__gen_reg_write_funcs(xehp_fwtable);
 __gen_reg_write_funcs(gen12_fwtable);
 __gen_reg_write_funcs(gen11_fwtable);
 __gen_reg_write_funcs(fwtable);
@@ -2087,7 +2061,7 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
 
 	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
 		ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);
-		ASSIGN_WRITE_MMIO_VFUNCS(uncore, xehp_fwtable);
+		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);
 		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
 	} else if (GRAPHICS_VER(i915) >= 12) {
 		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index d3e36ed32646..63b75585865f 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -68,7 +68,6 @@ static int intel_shadow_table_check(void)
 		{ gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) },
 		{ gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
 		{ gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs) },
-		{ xehp_shadowed_regs, ARRAY_SIZE(xehp_shadowed_regs) },
 	};
 	const struct i915_range *range;
 	unsigned int i, j;
-- 
2.25.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 22+ messages in thread

* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Forcewake and shadowed register updates
  2021-07-29  5:41 [Intel-gfx] [PATCH 0/6] Forcewake and shadowed register updates Matt Roper
                   ` (5 preceding siblings ...)
  2021-07-29  5:41 ` [Intel-gfx] [PATCH 6/6] drm/i915/xehp: Xe_HP shadowed registers are a strict superset of gen12 Matt Roper
@ 2021-07-29  6:09 ` Patchwork
  2021-07-29  6:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
                   ` (4 subsequent siblings)
  11 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2021-07-29  6:09 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

== Series Details ==

Series: Forcewake and shadowed register updates
URL   : https://patchwork.freedesktop.org/series/93158/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/intel_display.c:1900:21:    expected struct i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1900:21:    got void [noderef] __iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1900:21: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1410:34:    expected struct i915_address_space *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1410:34:    got struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1410:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:    expected struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:    got struct i915_address_space *
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:    expected struct i915_address_space *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:    got struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1268:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/i915_perf.c:1443:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1497:15: warning: memset with byte count of 16777216
-./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
-./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
-./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
-./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
-./include/linux/spinlock.h:409:9: warning: context imbalance in 'xehp_fwtable_write16' - different lock contexts for basic block
-./include/linux/spinlock.h:409:9: warning: context imbalance in 'xehp_fwtable_write32' - different lock contexts for basic block
-./include/linux/spinlock.h:409:9: warning: context imbalance in 'xehp_fwtable_write8' - different lock contexts for basic block
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 22+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for Forcewake and shadowed register updates
  2021-07-29  5:41 [Intel-gfx] [PATCH 0/6] Forcewake and shadowed register updates Matt Roper
                   ` (6 preceding siblings ...)
  2021-07-29  6:09 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Forcewake and shadowed register updates Patchwork
@ 2021-07-29  6:36 ` Patchwork
  2021-07-29 13:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
                   ` (3 subsequent siblings)
  11 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2021-07-29  6:36 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 3707 bytes --]

== Series Details ==

Series: Forcewake and shadowed register updates
URL   : https://patchwork.freedesktop.org/series/93158/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10416 -> Patchwork_20736
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/index.html

Known issues
------------

  Here are the changes found in Patchwork_20736 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@semaphore:
    - fi-bdw-5557u:       NOTRUN -> [SKIP][1] ([fdo#109271]) +29 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/fi-bdw-5557u/igt@amdgpu/amd_basic@semaphore.html

  * igt@core_hotunplug@unbind-rebind:
    - fi-bdw-5557u:       NOTRUN -> [WARN][2] ([i915#3718])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/fi-bdw-5557u/igt@core_hotunplug@unbind-rebind.html

  * igt@i915_pm_rpm@basic-rte:
    - fi-bdw-5557u:       NOTRUN -> [FAIL][3] ([i915#579])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/fi-bdw-5557u/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_selftest@live@late_gt_pm:
    - fi-bsw-nick:        [PASS][4] -> [DMESG-FAIL][5] ([i915#2927])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-bdw-5557u:       NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html

  * igt@runner@aborted:
    - fi-bsw-nick:        NOTRUN -> [FAIL][7] ([fdo#109271] / [i915#1436])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/fi-bsw-nick/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3718]: https://gitlab.freedesktop.org/drm/intel/issues/3718
  [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579


Participating hosts (40 -> 35)
------------------------------

  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_10416 -> Patchwork_20736

  CI-20190529: 20190529
  CI_DRM_10416: 68506f9070522fa084cb3a8e5e0de44ee63b61ca @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6155: 4b51398dcd7559012b85776e7353d516ff1e6ce6 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20736: 6f65d9de01bf32edbe7cfef1c8e405685ea3cf40 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

6f65d9de01bf drm/i915/xehp: Xe_HP shadowed registers are a strict superset of gen12
490ac23b9af9 drm/i915/gen12: Update shadowed register table
0a7b44dd5dd6 drm/i915/gen11: Update shadowed register table
13ee96857911 drm/i915: Make shadow tables range-based
91dc5afff480 drm/i915: Re-use gen11 forcewake read functions on gen12
6ce756ba709e drm/i915: correct name of GT forcewake domain in error messages

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/index.html

[-- Attachment #1.2: Type: text/html, Size: 4547 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 22+ messages in thread

* [Intel-gfx] ✗ Fi.CI.IGT: failure for Forcewake and shadowed register updates
  2021-07-29  5:41 [Intel-gfx] [PATCH 0/6] Forcewake and shadowed register updates Matt Roper
                   ` (7 preceding siblings ...)
  2021-07-29  6:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-07-29 13:00 ` Patchwork
  2021-07-29 20:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Forcewake and shadowed register updates (rev2) Patchwork
                   ` (2 subsequent siblings)
  11 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2021-07-29 13:00 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 30262 bytes --]

== Series Details ==

Series: Forcewake and shadowed register updates
URL   : https://patchwork.freedesktop.org/series/93158/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10416_full -> Patchwork_20736_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_20736_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20736_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_20736_full:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@mock@uncore:
    - shard-glk:          [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-glk1/igt@i915_selftest@mock@uncore.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-glk1/igt@i915_selftest@mock@uncore.html
    - shard-iclb:         [PASS][3] -> [DMESG-WARN][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-iclb1/igt@i915_selftest@mock@uncore.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb4/igt@i915_selftest@mock@uncore.html
    - shard-kbl:          [PASS][5] -> [DMESG-WARN][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-kbl3/igt@i915_selftest@mock@uncore.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl4/igt@i915_selftest@mock@uncore.html
    - shard-tglb:         [PASS][7] -> [DMESG-WARN][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-tglb2/igt@i915_selftest@mock@uncore.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-tglb3/igt@i915_selftest@mock@uncore.html
    - shard-skl:          [PASS][9] -> [DMESG-WARN][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-skl5/igt@i915_selftest@mock@uncore.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-skl9/igt@i915_selftest@mock@uncore.html
    - shard-apl:          [PASS][11] -> [DMESG-WARN][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-apl7/igt@i915_selftest@mock@uncore.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-apl8/igt@i915_selftest@mock@uncore.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@mock@uncore:
    - {shard-rkl}:        [PASS][13] -> [DMESG-WARN][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-rkl-6/igt@i915_selftest@mock@uncore.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-rkl-2/igt@i915_selftest@mock@uncore.html

  
Known issues
------------

  Here are the changes found in Patchwork_20736_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_create@create-massive:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][15] ([i915#3002])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl2/igt@gem_create@create-massive.html
    - shard-apl:          NOTRUN -> [DMESG-WARN][16] ([i915#3002])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-apl3/igt@gem_create@create-massive.html

  * igt@gem_ctx_persistence@process:
    - shard-snb:          NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#1099]) +2 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-snb5/igt@gem_ctx_persistence@process.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-glk:          [PASS][18] -> [FAIL][19] ([i915#2842]) +1 similar issue
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-glk6/igt@gem_exec_fair@basic-throttle@rcs0.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-glk1/igt@gem_exec_fair@basic-throttle@rcs0.html
    - shard-iclb:         [PASS][20] -> [FAIL][21] ([i915#2849])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_mmap_gtt@cpuset-big-copy-xy:
    - shard-iclb:         [PASS][22] -> [FAIL][23] ([i915#2428])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-iclb4/igt@gem_mmap_gtt@cpuset-big-copy-xy.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb4/igt@gem_mmap_gtt@cpuset-big-copy-xy.html

  * igt@gem_pread@exhaustion:
    - shard-apl:          NOTRUN -> [WARN][24] ([i915#2658])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-apl8/igt@gem_pread@exhaustion.html

  * igt@gem_render_copy@linear-to-vebox-y-tiled:
    - shard-iclb:         NOTRUN -> [SKIP][25] ([i915#768])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb4/igt@gem_render_copy@linear-to-vebox-y-tiled.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-apl:          NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3323])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-apl7/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@input-checking:
    - shard-snb:          NOTRUN -> [DMESG-WARN][27] ([i915#3002])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-snb5/igt@gem_userptr_blits@input-checking.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-iclb:         NOTRUN -> [SKIP][28] ([i915#2856])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb4/igt@gen9_exec_parse@bb-start-far.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-skl:          [PASS][29] -> [DMESG-WARN][30] ([i915#1982])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-skl4/igt@i915_module_load@reload-with-fault-injection.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-skl6/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [PASS][31] -> [FAIL][32] ([i915#454])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-iclb1/igt@i915_pm_dc@dc6-psr.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb6/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rpm@basic-rte:
    - shard-kbl:          NOTRUN -> [FAIL][33] ([i915#579])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl1/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_pm_rpm@pm-caching:
    - shard-iclb:         NOTRUN -> [SKIP][34] ([i915#579])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb4/igt@i915_pm_rpm@pm-caching.html

  * igt@i915_suspend@forcewake:
    - shard-apl:          [PASS][35] -> [DMESG-WARN][36] ([i915#180]) +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-apl7/igt@i915_suspend@forcewake.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-apl6/igt@i915_suspend@forcewake.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-apl:          NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3777]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-apl8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-kbl:          NOTRUN -> [SKIP][38] ([fdo#109271]) +79 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-apl:          NOTRUN -> [SKIP][39] ([fdo#109271]) +303 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-apl7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-iclb:         NOTRUN -> [SKIP][40] ([fdo#110723])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb4/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_chamelium@dp-mode-timings:
    - shard-iclb:         NOTRUN -> [SKIP][41] ([fdo#109284] / [fdo#111827])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb4/igt@kms_chamelium@dp-mode-timings.html

  * igt@kms_chamelium@hdmi-edid-change-during-suspend:
    - shard-apl:          NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +25 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-apl8/igt@kms_chamelium@hdmi-edid-change-during-suspend.html

  * igt@kms_chamelium@vga-hpd-for-each-pipe:
    - shard-kbl:          NOTRUN -> [SKIP][43] ([fdo#109271] / [fdo#111827]) +5 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl3/igt@kms_chamelium@vga-hpd-for-each-pipe.html
    - shard-skl:          NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-skl5/igt@kms_chamelium@vga-hpd-for-each-pipe.html

  * igt@kms_color_chamelium@pipe-c-ctm-red-to-blue:
    - shard-snb:          NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +10 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-snb5/igt@kms_color_chamelium@pipe-c-ctm-red-to-blue.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-tglb:         NOTRUN -> [SKIP][46] ([i915#3116])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-tglb6/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@legacy:
    - shard-kbl:          NOTRUN -> [TIMEOUT][47] ([i915#1319])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl1/igt@kms_content_protection@legacy.html

  * igt@kms_cursor_crc@pipe-a-cursor-max-size-sliding:
    - shard-iclb:         NOTRUN -> [SKIP][48] ([fdo#109278]) +9 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb4/igt@kms_cursor_crc@pipe-a-cursor-max-size-sliding.html

  * igt@kms_cursor_crc@pipe-c-cursor-max-size-sliding:
    - shard-tglb:         NOTRUN -> [SKIP][49] ([i915#3359]) +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-tglb6/igt@kms_cursor_crc@pipe-c-cursor-max-size-sliding.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
    - shard-iclb:         NOTRUN -> [SKIP][50] ([fdo#109274] / [fdo#109278])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb4/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
    - shard-skl:          [PASS][51] -> [FAIL][52] ([i915#2346])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][53] ([i915#180]) +2 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl1/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
    - shard-skl:          [PASS][54] -> [FAIL][55] ([i915#2122]) +1 similar issue
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-skl5/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html

  * igt@kms_force_connector_basic@force-load-detect:
    - shard-tglb:         NOTRUN -> [SKIP][56] ([fdo#109285])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-tglb7/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-iclb:         NOTRUN -> [SKIP][57] ([fdo#109280]) +2 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
    - shard-skl:          NOTRUN -> [SKIP][58] ([fdo#109271]) +39 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-skl5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
    - shard-snb:          NOTRUN -> [SKIP][59] ([fdo#109271]) +202 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-snb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite:
    - shard-tglb:         NOTRUN -> [SKIP][60] ([fdo#111825])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-tglb6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-kbl:          [PASS][61] -> [DMESG-WARN][62] ([i915#180]) +7 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-kbl3/igt@kms_hdr@bpc-switch-suspend.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl4/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
    - shard-apl:          NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#533]) +2 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-apl2/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][64] ([i915#265]) +1 similar issue
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
    - shard-apl:          NOTRUN -> [FAIL][65] ([fdo#108145] / [i915#265]) +1 similar issue
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html

  * igt@kms_plane_scaling@2x-scaler-multi-pipe:
    - shard-iclb:         NOTRUN -> [SKIP][66] ([fdo#109274]) +1 similar issue
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb4/igt@kms_plane_scaling@2x-scaler-multi-pipe.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
    - shard-apl:          NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#658]) +5 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-apl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
    - shard-kbl:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#658]) +1 similar issue
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
    - shard-skl:          NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#658])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-skl2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [PASS][70] -> [SKIP][71] ([fdo#109642] / [fdo#111068] / [i915#658])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb1/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         NOTRUN -> [SKIP][72] ([fdo#109441]) +1 similar issue
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb4/igt@kms_psr@psr2_cursor_blt.html
    - shard-tglb:         NOTRUN -> [FAIL][73] ([i915#132] / [i915#3467])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-tglb6/igt@kms_psr@psr2_cursor_blt.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [PASS][74] -> [SKIP][75] ([fdo#109441]) +1 similar issue
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb1/igt@kms_psr@psr2_primary_page_flip.html

  * igt@kms_selftest@all@damage_iter_no_damage:
    - shard-kbl:          NOTRUN -> [INCOMPLETE][76] ([i915#3871])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl7/igt@kms_selftest@all@damage_iter_no_damage.html

  * igt@perf@gen12-mi-rpc:
    - shard-iclb:         NOTRUN -> [SKIP][77] ([fdo#109289]) +1 similar issue
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb4/igt@perf@gen12-mi-rpc.html

  * igt@perf@polling-small-buf:
    - shard-skl:          [PASS][78] -> [FAIL][79] ([i915#1722])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-skl2/igt@perf@polling-small-buf.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-skl9/igt@perf@polling-small-buf.html

  * igt@prime_vgem@sync@vcs1:
    - shard-tglb:         [PASS][80] -> [INCOMPLETE][81] ([i915#409])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-tglb8/igt@prime_vgem@sync@vcs1.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-tglb6/igt@prime_vgem@sync@vcs1.html

  * igt@sysfs_clients@create:
    - shard-apl:          NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#2994]) +2 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-apl2/igt@sysfs_clients@create.html
    - shard-skl:          NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#2994])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-skl5/igt@sysfs_clients@create.html

  * igt@sysfs_clients@split-50:
    - shard-kbl:          NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#2994]) +1 similar issue
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl3/igt@sysfs_clients@split-50.html

  
#### Possible fixes ####

  * igt@feature_discovery@psr1:
    - {shard-rkl}:        [SKIP][85] ([i915#658]) -> [PASS][86] +1 similar issue
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-rkl-5/igt@feature_discovery@psr1.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-rkl-6/igt@feature_discovery@psr1.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [FAIL][87] ([i915#2842]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
    - shard-kbl:          [FAIL][89] ([i915#2842]) -> [PASS][90] +1 similar issue
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-kbl2/igt@gem_exec_fair@basic-none-vip@rcs0.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl1/igt@gem_exec_fair@basic-none-vip@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][91] ([i915#2842]) -> [PASS][92] +1 similar issue
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-kbl:          [DMESG-WARN][93] ([i915#1436] / [i915#716]) -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-kbl1/igt@gen9_exec_parse@allowed-all.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl2/igt@gen9_exec_parse@allowed-all.html

  * igt@kms_big_fb@linear-32bpp-rotate-0:
    - shard-iclb:         [DMESG-WARN][95] ([i915#3621]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-iclb1/igt@kms_big_fb@linear-32bpp-rotate-0.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb4/igt@kms_big_fb@linear-32bpp-rotate-0.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-180:
    - {shard-rkl}:        [SKIP][97] ([i915#3638]) -> [PASS][98] +1 similar issue
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-rkl-5/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-rkl-6/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - {shard-rkl}:        [SKIP][99] ([i915#3721]) -> [PASS][100] +2 similar issues
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-rkl-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_color@pipe-c-degamma:
    - {shard-rkl}:        [SKIP][101] ([i915#1149] / [i915#1849]) -> [PASS][102] +3 similar issues
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-rkl-5/igt@kms_color@pipe-c-degamma.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-rkl-6/igt@kms_color@pipe-c-degamma.html

  * igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen:
    - shard-skl:          [FAIL][103] ([i915#3444]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-skl1/igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-skl2/igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen:
    - {shard-rkl}:        [SKIP][105] ([fdo#112022]) -> [PASS][106] +7 similar issues
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-rkl-2/igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-rkl-6/igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
    - {shard-rkl}:        [SKIP][107] ([fdo#111825]) -> [PASS][108] +2 similar issues
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-rkl-2/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-rkl-6/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html

  * igt@kms_draw_crc@draw-method-rgb565-blt-untiled:
    - {shard-rkl}:        [SKIP][109] ([fdo#111314]) -> [PASS][110] +1 similar issue
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-rkl-5/igt@kms_draw_crc@draw-method-rgb565-blt-untiled.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-rkl-6/igt@kms_draw_crc@draw-method-rgb565-blt-untiled.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [DMESG-WARN][111] ([i915#180]) -> [PASS][112] +3 similar issues
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite:
    - {shard-rkl}:        [SKIP][113] ([i915#1849]) -> [PASS][114] +19 similar issues
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [FAIL][115] ([i915#1188]) -> [PASS][116] +1 similar issue
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_plane@pixel-format-source-clamping@pipe-b-planes:
    - {shard-rkl}:        [SKIP][117] ([i915#3558]) -> [PASS][118] +1 similar issue
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-rkl-2/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-rkl-6/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][119] ([fdo#108145] / [i915#265]) -> [PASS][120] +3 similar issues
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
    - {shard-rkl}:        [SKIP][121] ([i915#1849] / [i915#3558]) -> [PASS][122]
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-rkl-5/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-rkl-6/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html

  * igt@kms_plane_scaling@scaler-with-rotation@pipe-a-scaler-with-rotation:
    - shard-skl:          [DMESG-WARN][123] ([i915#1982]) -> [PASS][124]
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-skl8/igt@kms_plane_scaling@scaler-with-rotation@pipe-a-scaler-with-rotation.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-skl1/igt@kms_plane_scaling@scaler-with-rotation@pipe-a-scaler-with-rotation.html

  * igt@kms_psr@cursor_mmap_cpu:
    - {shard-rkl}:        [SKIP][125] ([i915#1072]) -> [PASS][126] +1 similar issue
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-rkl-2/igt@kms_psr@cursor_mmap_cpu.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-rkl-6/igt@kms_psr@cursor_mmap_cpu.html

  * igt@kms_vblank@pipe-c-wait-busy:
    - {shard-rkl}:        [SKIP][127] ([i915#1845]) -> [PASS][128] +15 similar issues
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-rkl-5/igt@kms_vblank@pipe-c-wait-busy.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-rkl-6/igt@kms_vblank@pipe-c-wait-busy.html

  * igt@perf@blocking:
    - {shard-rkl}:        [FAIL][129] ([i915#1542]) -> [PASS][130]
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-rkl-2/igt@perf@blocking.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-rkl-6/igt@perf@blocking.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-iclb:         [SKIP][131] ([i915#588]) -> [SKIP][132] ([i915#658])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb1/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-iclb:         [WARN][133] ([i915#1804] / [i915#2684]) -> [FAIL][134] ([i915#2680])
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-iclb7/igt@i915_pm_rc6_residency@rc6-idle.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb6/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
    - shard-iclb:         [SKIP][135] ([i915#658]) -> [SKIP][136] ([i915#2920]) +1 similar issue
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-iclb6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-0:
    - shard-iclb:         [SKIP][137] ([i915#2920]) -> [SKIP][138] ([i915#658])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb1/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142]) ([fdo#109271] / [i915#1436] / [i915#180] / [i915#3002] / [i915#3363] / [i915#716]) -> ([FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149], [FAIL][150]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2426] / [i915#3002] / [i915#3363])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-kbl2/igt@runner@aborted.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-kbl1/igt@runner@aborted.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-kbl1/igt@runner@aborted.html
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-kbl1/igt@runner@aborted.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl1/igt@runner@aborted.html
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl7/igt@runner@aborted.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl1/igt@runner@aborted.html
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl2/igt@runner@aborted.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl4/i

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/index.html

[-- Attachment #1.2: Type: text/html, Size: 33869 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [Intel-gfx] [PATCH 1/6] drm/i915: correct name of GT forcewake domain in error messages
  2021-07-29  5:41 ` [Intel-gfx] [PATCH 1/6] drm/i915: correct name of GT forcewake domain in error messages Matt Roper
@ 2021-07-29 14:13   ` Yokoyama, Caz
  0 siblings, 0 replies; 22+ messages in thread
From: Yokoyama, Caz @ 2021-07-29 14:13 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx

Reviewed-by: Caz Yokoyama <caz.yokoyama@intel.com>
-caz

On Wed, 2021-07-28 at 22:41 -0700, Matt Roper wrote:
> For historical reasons, the GT forcewake domain used to be referred
> to
> as the "blitter" domain; that name is no longer accurate since the GT
> domain contains a lot of additional registers and functionality
> besides
> just the blitter.  Although we renamed the domain in the driver in
> commit 55e3c170950f ("drm/i915: Rename FORCEWAKE_BLITTER to
> FORCEWAKE_GT"), we neglected to update the string that gets printed
> in
> driver error messages; let's do that now to avoid confusion.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 8cf53f54559d..bca548c81572 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -64,7 +64,7 @@ static void mmio_debug_resume(struct
> intel_uncore_mmio_debug *mmio_debug)
>  
>  static const char * const forcewake_domain_names[] = {
>  	"render",
> -	"blitter",
> +	"gt",
>  	"media",
>  	"vdbox0",
>  	"vdbox1",
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 22+ messages in thread

* [Intel-gfx] [PATCH v2 3/6] drm/i915: Make shadow tables range-based
  2021-07-29  5:41 ` [Intel-gfx] [PATCH 3/6] drm/i915: Make shadow tables range-based Matt Roper
@ 2021-07-29 15:21   ` Matt Roper
  2021-07-29 21:55     ` Yokoyama, Caz
  0 siblings, 1 reply; 22+ messages in thread
From: Matt Roper @ 2021-07-29 15:21 UTC (permalink / raw)
  To: intel-gfx

Rather than defining our shadow tables as a list of individual
registers, provide them as a list of register ranges; we'll have some
ranges of multiple registers being added soon (and we already have a
couple adjacent registers that we can squash into a single range now).

This change also defines the table with hex literal values rather than
symbolic register names; since that's how the tables are defined in the
bspec, this change will make it easier to review the tables overall.

v2:
 - Force signed comparison on range overlap sanity check

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |  13 +-
 drivers/gpu/drm/i915/intel_uncore.c           | 160 +++++++++---------
 drivers/gpu/drm/i915/intel_uncore.h           |   6 +
 drivers/gpu/drm/i915/selftests/intel_uncore.c |  32 ++--
 4 files changed, 108 insertions(+), 103 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 9173df59821a..7558414bafb2 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1963,12 +1963,7 @@ void intel_engine_apply_workarounds(struct intel_engine_cs *engine)
 	wa_list_apply(engine->gt, &engine->wa_list);
 }
 
-struct mcr_range {
-	u32 start;
-	u32 end;
-};
-
-static const struct mcr_range mcr_ranges_gen8[] = {
+static const struct i915_range mcr_ranges_gen8[] = {
 	{ .start = 0x5500, .end = 0x55ff },
 	{ .start = 0x7000, .end = 0x7fff },
 	{ .start = 0x9400, .end = 0x97ff },
@@ -1977,7 +1972,7 @@ static const struct mcr_range mcr_ranges_gen8[] = {
 	{},
 };
 
-static const struct mcr_range mcr_ranges_gen12[] = {
+static const struct i915_range mcr_ranges_gen12[] = {
 	{ .start =  0x8150, .end =  0x815f },
 	{ .start =  0x9520, .end =  0x955f },
 	{ .start =  0xb100, .end =  0xb3ff },
@@ -1986,7 +1981,7 @@ static const struct mcr_range mcr_ranges_gen12[] = {
 	{},
 };
 
-static const struct mcr_range mcr_ranges_xehp[] = {
+static const struct i915_range mcr_ranges_xehp[] = {
 	{ .start =  0x4000, .end =  0x4aff },
 	{ .start =  0x5200, .end =  0x52ff },
 	{ .start =  0x5400, .end =  0x7fff },
@@ -2004,7 +1999,7 @@ static const struct mcr_range mcr_ranges_xehp[] = {
 
 static bool mcr_range(struct drm_i915_private *i915, u32 offset)
 {
-	const struct mcr_range *mcr_ranges;
+	const struct i915_range *mcr_ranges;
 	int i;
 
 	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index ea910f7ee635..2cfbc16f7dee 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -946,101 +946,95 @@ static const struct intel_forcewake_range __vlv_fw_ranges[] = {
 	find_fw_domain(uncore, offset)
 
 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
-static const i915_reg_t gen8_shadowed_regs[] = {
-	RING_TAIL(RENDER_RING_BASE),	/* 0x2000 (base) */
-	GEN6_RPNSWREQ,			/* 0xA008 */
-	GEN6_RC_VIDEO_FREQ,		/* 0xA00C */
-	RING_TAIL(GEN6_BSD_RING_BASE),	/* 0x12000 (base) */
-	RING_TAIL(VEBOX_RING_BASE),	/* 0x1a000 (base) */
-	RING_TAIL(BLT_RING_BASE),	/* 0x22000 (base) */
+static const struct i915_range gen8_shadowed_regs[] = {
+	{ .start =  0x2030, .end =  0x2030 },
+	{ .start =  0xA008, .end =  0xA00C },
+	{ .start = 0x12030, .end = 0x12030 },
+	{ .start = 0x1a030, .end = 0x1a030 },
+	{ .start = 0x22030, .end = 0x22030 },
 	/* TODO: Other registers are not yet used */
 };
 
-static const i915_reg_t gen11_shadowed_regs[] = {
-	RING_TAIL(RENDER_RING_BASE),			/* 0x2000 (base) */
-	RING_EXECLIST_CONTROL(RENDER_RING_BASE),        /* 0x2550 */
-	GEN6_RPNSWREQ,					/* 0xA008 */
-	GEN6_RC_VIDEO_FREQ,				/* 0xA00C */
-	RING_TAIL(BLT_RING_BASE),			/* 0x22000 (base) */
-	RING_EXECLIST_CONTROL(BLT_RING_BASE),		/* 0x22550 */
-	RING_TAIL(GEN11_BSD_RING_BASE),			/* 0x1C0000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE),	/* 0x1C0550 */
-	RING_TAIL(GEN11_BSD2_RING_BASE),		/* 0x1C4000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE),	/* 0x1C4550 */
-	RING_TAIL(GEN11_VEBOX_RING_BASE),		/* 0x1C8000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE),	/* 0x1C8550 */
-	RING_TAIL(GEN11_BSD3_RING_BASE),		/* 0x1D0000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE),	/* 0x1D0550 */
-	RING_TAIL(GEN11_BSD4_RING_BASE),		/* 0x1D4000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE),	/* 0x1D4550 */
-	RING_TAIL(GEN11_VEBOX2_RING_BASE),		/* 0x1D8000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE),	/* 0x1D8550 */
+static const struct i915_range gen11_shadowed_regs[] = {
+	{ .start =   0x2030, .end =   0x2030 },
+	{ .start =   0x2550, .end =   0x2550 },
+	{ .start =   0xA008, .end =   0xA00C },
+	{ .start =  0x22030, .end =  0x22030 },
+	{ .start =  0x22550, .end =  0x22550 },
+	{ .start = 0x1C0030, .end = 0x1C0030 },
+	{ .start = 0x1C0550, .end = 0x1C0550 },
+	{ .start = 0x1C4030, .end = 0x1C4030 },
+	{ .start = 0x1C4550, .end = 0x1C4550 },
+	{ .start = 0x1C8030, .end = 0x1C8030 },
+	{ .start = 0x1C8550, .end = 0x1C8550 },
+	{ .start = 0x1D0030, .end = 0x1D0030 },
+	{ .start = 0x1D0550, .end = 0x1D0550 },
+	{ .start = 0x1D4030, .end = 0x1D4030 },
+	{ .start = 0x1D4550, .end = 0x1D4550 },
+	{ .start = 0x1D8030, .end = 0x1D8030 },
+	{ .start = 0x1D8550, .end = 0x1D8550 },
 	/* TODO: Other registers are not yet used */
 };
 
-static const i915_reg_t gen12_shadowed_regs[] = {
-	RING_TAIL(RENDER_RING_BASE),			/* 0x2000 (base) */
-	RING_EXECLIST_CONTROL(RENDER_RING_BASE),	/* 0x2550 */
-	GEN6_RPNSWREQ,					/* 0xA008 */
-	GEN6_RC_VIDEO_FREQ,				/* 0xA00C */
-	RING_TAIL(BLT_RING_BASE),			/* 0x22000 (base) */
-	RING_EXECLIST_CONTROL(BLT_RING_BASE),		/* 0x22550 */
-	RING_TAIL(GEN11_BSD_RING_BASE),			/* 0x1C0000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE),	/* 0x1C0550 */
-	RING_TAIL(GEN11_BSD2_RING_BASE),		/* 0x1C4000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE),	/* 0x1C4550 */
-	RING_TAIL(GEN11_VEBOX_RING_BASE),		/* 0x1C8000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE),	/* 0x1C8550 */
-	RING_TAIL(GEN11_BSD3_RING_BASE),		/* 0x1D0000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE),	/* 0x1D0550 */
-	RING_TAIL(GEN11_BSD4_RING_BASE),		/* 0x1D4000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE),	/* 0x1D4550 */
-	RING_TAIL(GEN11_VEBOX2_RING_BASE),		/* 0x1D8000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE),	/* 0x1D8550 */
+static const struct i915_range gen12_shadowed_regs[] = {
+	{ .start =   0x2030, .end =   0x2030 },
+	{ .start =   0x2550, .end =   0x2550 },
+	{ .start =   0xA008, .end =   0xA00C },
+	{ .start =  0x22030, .end =  0x22030 },
+	{ .start =  0x22550, .end =  0x22550 },
+	{ .start = 0x1C0030, .end = 0x1C0030 },
+	{ .start = 0x1C0550, .end = 0x1C0550 },
+	{ .start = 0x1C4030, .end = 0x1C4030 },
+	{ .start = 0x1C4550, .end = 0x1C4550 },
+	{ .start = 0x1C8030, .end = 0x1C8030 },
+	{ .start = 0x1C8550, .end = 0x1C8550 },
+	{ .start = 0x1D0030, .end = 0x1D0030 },
+	{ .start = 0x1D0550, .end = 0x1D0550 },
+	{ .start = 0x1D4030, .end = 0x1D4030 },
+	{ .start = 0x1D4550, .end = 0x1D4550 },
+	{ .start = 0x1D8030, .end = 0x1D8030 },
+	{ .start = 0x1D8550, .end = 0x1D8550 },
 	/* TODO: Other registers are not yet used */
 };
 
-static const i915_reg_t xehp_shadowed_regs[] = {
-	RING_TAIL(RENDER_RING_BASE),			/* 0x2000 (base) */
-	RING_EXECLIST_CONTROL(RENDER_RING_BASE),        /* 0x2550 */
-	GEN6_RPNSWREQ,					/* 0xA008 */
-	GEN6_RC_VIDEO_FREQ,				/* 0xA00C */
-	RING_TAIL(BLT_RING_BASE),			/* 0x22000 (base) */
-	RING_EXECLIST_CONTROL(BLT_RING_BASE),		/* 0x22550 */
-	RING_TAIL(GEN11_BSD_RING_BASE),			/* 0x1C0000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE),	/* 0x1C0550 */
-	RING_TAIL(GEN11_BSD2_RING_BASE),		/* 0x1C4000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE),	/* 0x1C4550 */
-	RING_TAIL(GEN11_VEBOX_RING_BASE),		/* 0x1C8000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE),	/* 0x1C8550 */
-	RING_TAIL(GEN11_BSD3_RING_BASE),		/* 0x1D0000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE),	/* 0x1D0550 */
-	RING_TAIL(GEN11_BSD4_RING_BASE),		/* 0x1D4000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE),	/* 0x1D4550 */
-	RING_TAIL(GEN11_VEBOX2_RING_BASE),		/* 0x1D8000 (base) */
-	RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE),	/* 0x1D8550 */
-	RING_TAIL(XEHP_BSD5_RING_BASE),			/* 0x1E0000 (base) */
-	RING_EXECLIST_CONTROL(XEHP_BSD5_RING_BASE),	/* 0x1E0550 */
-	RING_TAIL(XEHP_BSD6_RING_BASE),			/* 0x1E4000 (base) */
-	RING_EXECLIST_CONTROL(XEHP_BSD6_RING_BASE),	/* 0x1E4550 */
-	RING_TAIL(XEHP_VEBOX3_RING_BASE),		/* 0x1E8000 (base) */
-	RING_EXECLIST_CONTROL(XEHP_VEBOX3_RING_BASE),	/* 0x1E8550 */
-	RING_TAIL(XEHP_BSD7_RING_BASE),			/* 0x1F0000 (base) */
-	RING_EXECLIST_CONTROL(XEHP_BSD7_RING_BASE),	/* 0x1F0550 */
-	RING_TAIL(XEHP_BSD8_RING_BASE),			/* 0x1F4000 (base) */
-	RING_EXECLIST_CONTROL(XEHP_BSD8_RING_BASE),	/* 0x1F4550 */
-	RING_TAIL(XEHP_VEBOX4_RING_BASE),		/* 0x1F8000 (base) */
-	RING_EXECLIST_CONTROL(XEHP_VEBOX4_RING_BASE),	/* 0x1F8550 */
+static const struct i915_range xehp_shadowed_regs[] = {
+	{ .start =   0x2000, .end =   0x2030 },
+	{ .start =   0x2550, .end =   0x2550 },
+	{ .start =   0xA008, .end =   0xA00C },
+	{ .start =  0x22030, .end =  0x22030 },
+	{ .start =  0x22550, .end =  0x22550 },
+	{ .start = 0x1C0030, .end = 0x1C0030 },
+	{ .start = 0x1C0550, .end = 0x1C0550 },
+	{ .start = 0x1C4030, .end = 0x1C4030 },
+	{ .start = 0x1C4550, .end = 0x1C4550 },
+	{ .start = 0x1C8030, .end = 0x1C8030 },
+	{ .start = 0x1C8550, .end = 0x1C8550 },
+	{ .start = 0x1D0030, .end = 0x1D0030 },
+	{ .start = 0x1D0550, .end = 0x1D0550 },
+	{ .start = 0x1D4030, .end = 0x1D4030 },
+	{ .start = 0x1D4550, .end = 0x1D4550 },
+	{ .start = 0x1D8030, .end = 0x1D8030 },
+	{ .start = 0x1D8550, .end = 0x1D8550 },
+	{ .start = 0x1E0030, .end = 0x1E0030 },
+	{ .start = 0x1E0550, .end = 0x1E0550 },
+	{ .start = 0x1E4030, .end = 0x1E4030 },
+	{ .start = 0x1E4550, .end = 0x1E4550 },
+	{ .start = 0x1E8030, .end = 0x1E8030 },
+	{ .start = 0x1E8550, .end = 0x1E8550 },
+	{ .start = 0x1F0030, .end = 0x1F0030 },
+	{ .start = 0x1F0550, .end = 0x1F0550 },
+	{ .start = 0x1F4030, .end = 0x1F4030 },
+	{ .start = 0x1F4550, .end = 0x1F4550 },
+	{ .start = 0x1F8030, .end = 0x1F8030 },
+	{ .start = 0x1F8550, .end = 0x1F8550 },
 	/* TODO: Other registers are not yet used */
 };
 
-static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
+static int mmio_range_cmp(u32 key, const struct i915_range *range)
 {
-	u32 offset = i915_mmio_reg_offset(*reg);
-
-	if (key < offset)
+	if (key < range->start)
 		return -1;
-	else if (key > offset)
+	else if (key > range->end)
 		return 1;
 	else
 		return 0;
@@ -1049,9 +1043,9 @@ static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
 #define __is_X_shadowed(x) \
 static bool is_##x##_shadowed(u32 offset) \
 { \
-	const i915_reg_t *regs = x##_shadowed_regs; \
+	const struct i915_range *regs = x##_shadowed_regs; \
 	return BSEARCH(offset, regs, ARRAY_SIZE(x##_shadowed_regs), \
-		       mmio_reg_cmp); \
+		       mmio_range_cmp); \
 }
 
 __is_X_shadowed(gen8)
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 3c0b0a8b5250..531665b08039 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -119,6 +119,12 @@ struct intel_forcewake_range {
 	enum forcewake_domains domains;
 };
 
+/* Other register ranges (e.g., shadow tables, MCR tables, etc.) */
+struct i915_range {
+	u32 start;
+	u32 end;
+};
+
 struct intel_uncore {
 	void __iomem *regs;
 
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index 720b60853f8b..d6a9c11afa23 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -62,30 +62,40 @@ static int intel_fw_table_check(const struct intel_forcewake_range *ranges,
 static int intel_shadow_table_check(void)
 {
 	struct {
-		const i915_reg_t *regs;
+		const struct i915_range *regs;
 		unsigned int size;
-	} reg_lists[] = {
+	} range_lists[] = {
 		{ gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) },
 		{ gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
 		{ gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs) },
 		{ xehp_shadowed_regs, ARRAY_SIZE(xehp_shadowed_regs) },
 	};
-	const i915_reg_t *reg;
+	const struct i915_range *range;
 	unsigned int i, j;
 	s32 prev;
 
-	for (j = 0; j < ARRAY_SIZE(reg_lists); ++j) {
-		reg = reg_lists[j].regs;
-		for (i = 0, prev = -1; i < reg_lists[j].size; i++, reg++) {
-			u32 offset = i915_mmio_reg_offset(*reg);
+	for (j = 0; j < ARRAY_SIZE(range_lists); ++j) {
+		range = range_lists[j].regs;
+		for (i = 0, prev = -1; i < range_lists[j].size; i++, range++) {
+			if (range->end < range->start) {
+				pr_err("%s: range[%d]:(%06x-%06x) has end before start\n",
+				       __func__, i, range->start, range->end);
+				return -EINVAL;
+			}
+
+			if (prev >= (s32)range->start) {
+				pr_err("%s: range[%d]:(%06x-%06x) is before end of previous (%06x)\n",
+				       __func__, i, range->start, range->end, prev);
+				return -EINVAL;
+			}
 
-			if (prev >= (s32)offset) {
-				pr_err("%s: entry[%d]:(%x) is before previous (%x)\n",
-				       __func__, i, offset, prev);
+			if (range->start % 4) {
+				pr_err("%s: range[%d]:(%06x-%06x) has non-dword-aligned start\n",
+				       __func__, i, range->start, range->end);
 				return -EINVAL;
 			}
 
-			prev = offset;
+			prev = range->end;
 		}
 	}
 
-- 
2.25.4

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^ permalink raw reply	[flat|nested] 22+ messages in thread

* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Forcewake and shadowed register updates (rev2)
  2021-07-29  5:41 [Intel-gfx] [PATCH 0/6] Forcewake and shadowed register updates Matt Roper
                   ` (8 preceding siblings ...)
  2021-07-29 13:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2021-07-29 20:33 ` Patchwork
  2021-07-29 20:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
  2021-07-30  8:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  11 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2021-07-29 20:33 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

== Series Details ==

Series: Forcewake and shadowed register updates (rev2)
URL   : https://patchwork.freedesktop.org/series/93158/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/intel_display.c:1901:21:    expected struct i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1901:21:    got void [noderef] __iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1901:21: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1410:34:    expected struct i915_address_space *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1410:34:    got struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1410:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:    expected struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:    got struct i915_address_space *
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:    expected struct i915_address_space *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:    got struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1268:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/i915_perf.c:1443:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1497:15: warning: memset with byte count of 16777216
-./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
-./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
-./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
-./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
-./include/linux/spinlock.h:409:9: warning: context imbalance in 'xehp_fwtable_write16' - different lock contexts for basic block
-./include/linux/spinlock.h:409:9: warning: context imbalance in 'xehp_fwtable_write32' - different lock contexts for basic block
-./include/linux/spinlock.h:409:9: warning: context imbalance in 'xehp_fwtable_write8' - different lock contexts for basic block
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined


_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 22+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for Forcewake and shadowed register updates (rev2)
  2021-07-29  5:41 [Intel-gfx] [PATCH 0/6] Forcewake and shadowed register updates Matt Roper
                   ` (9 preceding siblings ...)
  2021-07-29 20:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Forcewake and shadowed register updates (rev2) Patchwork
@ 2021-07-29 20:58 ` Patchwork
  2021-07-30  8:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  11 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2021-07-29 20:58 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 4585 bytes --]

== Series Details ==

Series: Forcewake and shadowed register updates (rev2)
URL   : https://patchwork.freedesktop.org/series/93158/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10420 -> Patchwork_20742
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/index.html

Known issues
------------

  Here are the changes found in Patchwork_20742 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_fence@basic-busy@bcs0:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][1] ([fdo#109271]) +26 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-tgl-1115g4:      [PASS][2] -> [FAIL][3] ([i915#1888])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html

  * igt@i915_pm_rpm@basic-rte:
    - fi-kbl-soraka:      NOTRUN -> [FAIL][5] ([i915#579])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/fi-kbl-soraka/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_selftest@live@gt_pm:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][6] ([i915#1886] / [i915#2291])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gt_heartbeat:
    - {fi-tgl-dsi}:       [DMESG-FAIL][9] ([i915#541]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
  [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579


Participating hosts (39 -> 34)
------------------------------

  Additional (1): fi-kbl-soraka 
  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus bat-jsl-1 


Build changes
-------------

  * Linux: CI_DRM_10420 -> Patchwork_20742

  CI-20190529: 20190529
  CI_DRM_10420: 863957775825d20952875034f22937aec4a71a23 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6158: bb1c96b29234f86cd71d9cbd019aafada9097f24 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20742: 3a2f554722e7d0e7647f92a15261b050db56cdf7 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3a2f554722e7 drm/i915/xehp: Xe_HP shadowed registers are a strict superset of gen12
4dc7a69ce015 drm/i915/gen12: Update shadowed register table
d4c8c1f86808 drm/i915/gen11: Update shadowed register table
c5be365b37c9 drm/i915: Make shadow tables range-based
7e96fc94addf drm/i915: Re-use gen11 forcewake read functions on gen12
32ceffc23e74 drm/i915: correct name of GT forcewake domain in error messages

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/index.html

[-- Attachment #1.2: Type: text/html, Size: 5614 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [Intel-gfx] [PATCH 2/6] drm/i915: Re-use gen11 forcewake read functions on gen12
  2021-07-29  5:41 ` [Intel-gfx] [PATCH 2/6] drm/i915: Re-use gen11 forcewake read functions on gen12 Matt Roper
@ 2021-07-29 21:02   ` Yokoyama, Caz
  0 siblings, 0 replies; 22+ messages in thread
From: Yokoyama, Caz @ 2021-07-29 21:02 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx

Reviewed-by: Caz Yokoyama <caz.yokoyama@intel.com>
-caz

On Wed, 2021-07-28 at 22:41 -0700, Matt Roper wrote:
> The forcewake read logic is identical between gen11 and gen12, only
> the
> forcewake table data (which is tracked separately) differs; there's
> no
> need to generate a separate set of gen12 read functions when the
> gen11
> functions will work just as well.
> 
> We'll keep the separate write functions for now since the generated
> code
> directly references different shadow tables between the two
> platforms.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 6 +-----
>  1 file changed, 1 insertion(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index bca548c81572..ea910f7ee635 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -945,9 +945,6 @@ static const struct intel_forcewake_range
> __vlv_fw_ranges[] = {
>  #define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
>  	find_fw_domain(uncore, offset)
>  
> -#define __gen12_fwtable_reg_read_fw_domains(uncore, offset) \
> -	find_fw_domain(uncore, offset)
> -
>  /* *Must* be sorted by offset! See intel_shadow_table_check(). */
>  static const i915_reg_t gen8_shadowed_regs[] = {
>  	RING_TAIL(RENDER_RING_BASE),	/* 0x2000 (base) */
> @@ -1617,7 +1614,6 @@ __gen_read(func, 16) \
>  __gen_read(func, 32) \
>  __gen_read(func, 64)
>  
> -__gen_reg_read_funcs(gen12_fwtable);
>  __gen_reg_read_funcs(gen11_fwtable);
>  __gen_reg_read_funcs(fwtable);
>  __gen_reg_read_funcs(gen6);
> @@ -2091,7 +2087,7 @@ static int uncore_forcewake_init(struct
> intel_uncore *uncore)
>  	} else if (GRAPHICS_VER(i915) >= 12) {
>  		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
>  		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);
> -		ASSIGN_READ_MMIO_VFUNCS(uncore, gen12_fwtable);
> +		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
>  	} else if (GRAPHICS_VER(i915) == 11) {
>  		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
>  		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable);
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^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [Intel-gfx] [PATCH v2 3/6] drm/i915: Make shadow tables range-based
  2021-07-29 15:21   ` [Intel-gfx] [PATCH v2 " Matt Roper
@ 2021-07-29 21:55     ` Yokoyama, Caz
  2021-07-29 21:59       ` Matt Roper
  0 siblings, 1 reply; 22+ messages in thread
From: Yokoyama, Caz @ 2021-07-29 21:55 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx

On Thu, 2021-07-29 at 08:21 -0700, Matt Roper wrote:
> Rather than defining our shadow tables as a list of individual
> registers, provide them as a list of register ranges; we'll have some
> ranges of multiple registers being added soon (and we already have a
> couple adjacent registers that we can squash into a single range
> now).
> 
> This change also defines the table with hex literal values rather
> than
> symbolic register names; since that's how the tables are defined in
> the
> bspec, this change will make it easier to review the tables overall.
> 
> v2:
>  - Force signed comparison on range overlap sanity check
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   |  13 +-
>  drivers/gpu/drm/i915/intel_uncore.c           | 160 +++++++++-------
> --
>  drivers/gpu/drm/i915/intel_uncore.h           |   6 +
>  drivers/gpu/drm/i915/selftests/intel_uncore.c |  32 ++--
>  4 files changed, 108 insertions(+), 103 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 9173df59821a..7558414bafb2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1963,12 +1963,7 @@ void intel_engine_apply_workarounds(struct
> intel_engine_cs *engine)
>  	wa_list_apply(engine->gt, &engine->wa_list);
>  }
>  
> -struct mcr_range {
> -	u32 start;
> -	u32 end;
> -};
> -
> -static const struct mcr_range mcr_ranges_gen8[] = {
> +static const struct i915_range mcr_ranges_gen8[] = {
>  	{ .start = 0x5500, .end = 0x55ff },
>  	{ .start = 0x7000, .end = 0x7fff },
>  	{ .start = 0x9400, .end = 0x97ff },
> @@ -1977,7 +1972,7 @@ static const struct mcr_range mcr_ranges_gen8[]
> = {
>  	{},
>  };
>  
> -static const struct mcr_range mcr_ranges_gen12[] = {
> +static const struct i915_range mcr_ranges_gen12[] = {
>  	{ .start =  0x8150, .end =  0x815f },
>  	{ .start =  0x9520, .end =  0x955f },
>  	{ .start =  0xb100, .end =  0xb3ff },
> @@ -1986,7 +1981,7 @@ static const struct mcr_range
> mcr_ranges_gen12[] = {
>  	{},
>  };
>  
> -static const struct mcr_range mcr_ranges_xehp[] = {
> +static const struct i915_range mcr_ranges_xehp[] = {
>  	{ .start =  0x4000, .end =  0x4aff },
>  	{ .start =  0x5200, .end =  0x52ff },
>  	{ .start =  0x5400, .end =  0x7fff },
> @@ -2004,7 +1999,7 @@ static const struct mcr_range mcr_ranges_xehp[]
> = {
>  
>  static bool mcr_range(struct drm_i915_private *i915, u32 offset)
>  {
> -	const struct mcr_range *mcr_ranges;
> +	const struct i915_range *mcr_ranges;
>  	int i;
>  
>  	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index ea910f7ee635..2cfbc16f7dee 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -946,101 +946,95 @@ static const struct intel_forcewake_range
> __vlv_fw_ranges[] = {
>  	find_fw_domain(uncore, offset)
>  
>  /* *Must* be sorted by offset! See intel_shadow_table_check(). */
> -static const i915_reg_t gen8_shadowed_regs[] = {
> -	RING_TAIL(RENDER_RING_BASE),	/* 0x2000 (base) */
> -	GEN6_RPNSWREQ,			/* 0xA008 *
> -	GEN6_RC_VIDEO_FREQ,		/* 0xA00C */
> -	RING_TAIL(GEN6_BSD_RING_BASE),	/* 0x12000 (base) */
> -	RING_TAIL(VEBOX_RING_BASE),	/* 0x1a000 (base) */
> -	RING_TAIL(BLT_RING_BASE),	/* 0x22000 (base) */
> +static const struct i915_range gen8_shadowed_regs[] = {
> +	{ .start =  0x2030, .end =  0x2030 },
> +	{ .start =  0xA008, .end =  0xA00C },
> +	{ .start = 0x12030, .end = 0x12030 },
> +	{ .start = 0x1a030, .end = 0x1a030 },
> +	{ .start = 0x22030, .end = 0x22030 },
You are replacing macro defined values by literal values. These macro
defined values are no longer used in this patch, but used in other
places such as intel_rps.c:gen6_rps_set(). What plan do you have about
the same address is defined in 2 ways, i.e. macro and literal value?
-caz

>  	/* TODO: Other registers are not yet used */
>  };
>  
> -static const i915_reg_t gen11_shadowed_regs[] = {
> -	RING_TAIL(RENDER_RING_BASE),			/* 0x2000
> (base) */
> -	RING_EXECLIST_CONTROL(RENDER_RING_BASE),        /* 0x2550 */
> -	GEN6_RPNSWREQ,					/* 0xA008 */
> -	GEN6_RC_VIDEO_FREQ,				/* 0xA00C */
> -	RING_TAIL(BLT_RING_BASE),			/* 0x22000 (base) */
> -	RING_EXECLIST_CONTROL(BLT_RING_BASE),		/* 0x22550 */
> -	RING_TAIL(GEN11_BSD_RING_BASE),			/* 0x1C0000
> (base) */
> -	RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE),	/* 0x1C0550
> */
> -	RING_TAIL(GEN11_BSD2_RING_BASE),		/* 0x1C4000 (base) */
> -	RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE),	/* 0x1C4550
> */
> -	RING_TAIL(GEN11_VEBOX_RING_BASE),		/* 0x1C8000 (base) */
> -	RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE),	/* 0x1C8550
> */
> -	RING_TAIL(GEN11_BSD3_RING_BASE),		/* 0x1D0000 (base) */
> -	RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE),	/* 0x1D0550
> */
> -	RING_TAIL(GEN11_BSD4_RING_BASE),		/* 0x1D4000 (base) */
> -	RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE),	/* 0x1D4550
> */
> -	RING_TAIL(GEN11_VEBOX2_RING_BASE),		/* 0x1D8000
> (base) */
> -	RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE),	/* 0x1D8550
> */
> +static const struct i915_range gen11_shadowed_regs[] = {
> +	{ .start =   0x2030, .end =   0x2030 },
> +	{ .start =   0x2550, .end =   0x2550 },
> +	{ .start =   0xA008, .end =   0xA00C },
> +	{ .start =  0x22030, .end =  0x22030 },
> +	{ .start =  0x22550, .end =  0x22550 },
> +	{ .start = 0x1C0030, .end = 0x1C0030 },
> +	{ .start = 0x1C0550, .end = 0x1C0550 },
> +	{ .start = 0x1C4030, .end = 0x1C4030 },
> +	{ .start = 0x1C4550, .end = 0x1C4550 },
> +	{ .start = 0x1C8030, .end = 0x1C8030 },
> +	{ .start = 0x1C8550, .end = 0x1C8550 },
> +	{ .start = 0x1D0030, .end = 0x1D0030 },
> +	{ .start = 0x1D0550, .end = 0x1D0550 },
> +	{ .start = 0x1D4030, .end = 0x1D4030 },
> +	{ .start = 0x1D4550, .end = 0x1D4550 },
> +	{ .start = 0x1D8030, .end = 0x1D8030 },
> +	{ .start = 0x1D8550, .end = 0x1D8550 },
>  	/* TODO: Other registers are not yet used */
>  };
>  
> -static const i915_reg_t gen12_shadowed_regs[] = {
> -	RING_TAIL(RENDER_RING_BASE),			/* 0x2000
> (base) */
> -	RING_EXECLIST_CONTROL(RENDER_RING_BASE),	/* 0x2550 */
> -	GEN6_RPNSWREQ,					/* 0xA008 */
> -	GEN6_RC_VIDEO_FREQ,				/* 0xA00C */
> -	RING_TAIL(BLT_RING_BASE),			/* 0x22000 (base) */
> -	RING_EXECLIST_CONTROL(BLT_RING_BASE),		/* 0x22550 */
> -	RING_TAIL(GEN11_BSD_RING_BASE),			/* 0x1C0000
> (base) */
> -	RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE),	/* 0x1C0550
> */
> -	RING_TAIL(GEN11_BSD2_RING_BASE),		/* 0x1C4000 (base) */
> -	RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE),	/* 0x1C4550
> */
> -	RING_TAIL(GEN11_VEBOX_RING_BASE),		/* 0x1C8000 (base) */
> -	RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE),	/* 0x1C8550
> */
> -	RING_TAIL(GEN11_BSD3_RING_BASE),		/* 0x1D0000 (base) */
> -	RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE),	/* 0x1D0550
> */
> -	RING_TAIL(GEN11_BSD4_RING_BASE),		/* 0x1D4000 (base) */
> -	RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE),	/* 0x1D4550
> */
> -	RING_TAIL(GEN11_VEBOX2_RING_BASE),		/* 0x1D8000
> (base) */
> -	RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE),	/* 0x1D8550
> */
> +static const struct i915_range gen12_shadowed_regs[] = {
> +	{ .start =   0x2030, .end =   0x2030 },
> +	{ .start =   0x2550, .end =   0x2550 },
> +	{ .start =   0xA008, .end =   0xA00C },
> +	{ .start =  0x22030, .end =  0x22030 },
> +	{ .start =  0x22550, .end =  0x22550 },
> +	{ .start = 0x1C0030, .end = 0x1C0030 },
> +	{ .start = 0x1C0550, .end = 0x1C0550 },
> +	{ .start = 0x1C4030, .end = 0x1C4030 },
> +	{ .start = 0x1C4550, .end = 0x1C4550 },
> +	{ .start = 0x1C8030, .end = 0x1C8030 },
> +	{ .start = 0x1C8550, .end = 0x1C8550 },
> +	{ .start = 0x1D0030, .end = 0x1D0030 },
> +	{ .start = 0x1D0550, .end = 0x1D0550 },
> +	{ .start = 0x1D4030, .end = 0x1D4030 },
> +	{ .start = 0x1D4550, .end = 0x1D4550 },
> +	{ .start = 0x1D8030, .end = 0x1D8030 },
> +	{ .start = 0x1D8550, .end = 0x1D8550 },
>  	/* TODO: Other registers are not yet used */
>  };
>  
> -static const i915_reg_t xehp_shadowed_regs[] = {
> -	RING_TAIL(RENDER_RING_BASE),			/* 0x2000
> (base) */
> -	RING_EXECLIST_CONTROL(RENDER_RING_BASE),        /* 0x2550 */
> -	GEN6_RPNSWREQ,					/* 0xA008 */
> -	GEN6_RC_VIDEO_FREQ,				/* 0xA00C */
> -	RING_TAIL(BLT_RING_BASE),			/* 0x22000 (base) */
> -	RING_EXECLIST_CONTROL(BLT_RING_BASE),		/* 0x22550 */
> -	RING_TAIL(GEN11_BSD_RING_BASE),			/* 0x1C0000
> (base) */
> -	RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE),	/* 0x1C0550
> */
> -	RING_TAIL(GEN11_BSD2_RING_BASE),		/* 0x1C4000 (base) */
> -	RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE),	/* 0x1C4550
> */
> -	RING_TAIL(GEN11_VEBOX_RING_BASE),		/* 0x1C8000 (base) */
> -	RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE),	/* 0x1C8550
> */
> -	RING_TAIL(GEN11_BSD3_RING_BASE),		/* 0x1D0000 (base) */
> -	RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE),	/* 0x1D0550
> */
> -	RING_TAIL(GEN11_BSD4_RING_BASE),		/* 0x1D4000 (base) */
> -	RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE),	/* 0x1D4550
> */
> -	RING_TAIL(GEN11_VEBOX2_RING_BASE),		/* 0x1D8000
> (base) */
> -	RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE),	/* 0x1D8550
> */
> -	RING_TAIL(XEHP_BSD5_RING_BASE),			/* 0x1E0000
> (base) */
> -	RING_EXECLIST_CONTROL(XEHP_BSD5_RING_BASE),	/* 0x1E0550
> */
> -	RING_TAIL(XEHP_BSD6_RING_BASE),			/* 0x1E4000
> (base) */
> -	RING_EXECLIST_CONTROL(XEHP_BSD6_RING_BASE),	/* 0x1E4550
> */
> -	RING_TAIL(XEHP_VEBOX3_RING_BASE),		/* 0x1E8000 (base) */
> -	RING_EXECLIST_CONTROL(XEHP_VEBOX3_RING_BASE),	/* 0x1E8550
> */
> -	RING_TAIL(XEHP_BSD7_RING_BASE),			/* 0x1F0000
> (base) */
> -	RING_EXECLIST_CONTROL(XEHP_BSD7_RING_BASE),	/* 0x1F0550
> */
> -	RING_TAIL(XEHP_BSD8_RING_BASE),			/* 0x1F4000
> (base) */
> -	RING_EXECLIST_CONTROL(XEHP_BSD8_RING_BASE),	/* 0x1F4550
> */
> -	RING_TAIL(XEHP_VEBOX4_RING_BASE),		/* 0x1F8000 (base) */
> -	RING_EXECLIST_CONTROL(XEHP_VEBOX4_RING_BASE),	/* 0x1F8550
> */
> +static const struct i915_range xehp_shadowed_regs[] = {
> +	{ .start =   0x2000, .end =   0x2030 },
> +	{ .start =   0x2550, .end =   0x2550 },
> +	{ .start =   0xA008, .end =   0xA00C },
> +	{ .start =  0x22030, .end =  0x22030 },
> +	{ .start =  0x22550, .end =  0x22550 },
> +	{ .start = 0x1C0030, .end = 0x1C0030 },
> +	{ .start = 0x1C0550, .end = 0x1C0550 },
> +	{ .start = 0x1C4030, .end = 0x1C4030 },
> +	{ .start = 0x1C4550, .end = 0x1C4550 },
> +	{ .start = 0x1C8030, .end = 0x1C8030 },
> +	{ .start = 0x1C8550, .end = 0x1C8550 },
> +	{ .start = 0x1D0030, .end = 0x1D0030 },
> +	{ .start = 0x1D0550, .end = 0x1D0550 },
> +	{ .start = 0x1D4030, .end = 0x1D4030 },
> +	{ .start = 0x1D4550, .end = 0x1D4550 },
> +	{ .start = 0x1D8030, .end = 0x1D8030 },
> +	{ .start = 0x1D8550, .end = 0x1D8550 },
> +	{ .start = 0x1E0030, .end = 0x1E0030 },
> +	{ .start = 0x1E0550, .end = 0x1E0550 },
> +	{ .start = 0x1E4030, .end = 0x1E4030 },
> +	{ .start = 0x1E4550, .end = 0x1E4550 },
> +	{ .start = 0x1E8030, .end = 0x1E8030 },
> +	{ .start = 0x1E8550, .end = 0x1E8550 },
> +	{ .start = 0x1F0030, .end = 0x1F0030 },
> +	{ .start = 0x1F0550, .end = 0x1F0550 },
> +	{ .start = 0x1F4030, .end = 0x1F4030 },
> +	{ .start = 0x1F4550, .end = 0x1F4550 },
> +	{ .start = 0x1F8030, .end = 0x1F8030 },
> +	{ .start = 0x1F8550, .end = 0x1F8550 },
>  	/* TODO: Other registers are not yet used */
>  };
>  
> -static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
> +static int mmio_range_cmp(u32 key, const struct i915_range *range)
>  {
> -	u32 offset = i915_mmio_reg_offset(*reg);
> -
> -	if (key < offset)
> +	if (key < range->start)
>  		return -1;
> -	else if (key > offset)
> +	else if (key > range->end)
>  		return 1;
>  	else
>  		return 0;
> @@ -1049,9 +1043,9 @@ static int mmio_reg_cmp(u32 key, const
> i915_reg_t *reg)
>  #define __is_X_shadowed(x) \
>  static bool is_##x##_shadowed(u32 offset) \
>  { \
> -	const i915_reg_t *regs = x##_shadowed_regs; \
> +	const struct i915_range *regs = x##_shadowed_regs; \
>  	return BSEARCH(offset, regs, ARRAY_SIZE(x##_shadowed_regs), \
> -		       mmio_reg_cmp); \
> +		       mmio_range_cmp); \
>  }
>  
>  __is_X_shadowed(gen8)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h
> b/drivers/gpu/drm/i915/intel_uncore.h
> index 3c0b0a8b5250..531665b08039 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -119,6 +119,12 @@ struct intel_forcewake_range {
>  	enum forcewake_domains domains;
>  };
>  
> +/* Other register ranges (e.g., shadow tables, MCR tables, etc.) */
> +struct i915_range {
> +	u32 start;
> +	u32 end;
> +};
> +
>  struct intel_uncore {
>  	void __iomem *regs;
>  
> diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> index 720b60853f8b..d6a9c11afa23 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> @@ -62,30 +62,40 @@ static int intel_fw_table_check(const struct
> intel_forcewake_range *ranges,
>  static int intel_shadow_table_check(void)
>  {
>  	struct {
> -		const i915_reg_t *regs;
> +		const struct i915_range *regs;
>  		unsigned int size;
> -	} reg_lists[] = {
> +	} range_lists[] = {
>  		{ gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) },
>  		{ gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs)
> },
>  		{ gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs)
> },
>  		{ xehp_shadowed_regs, ARRAY_SIZE(xehp_shadowed_regs) },
>  	};
> -	const i915_reg_t *reg;
> +	const struct i915_range *range;
>  	unsigned int i, j;
>  	s32 prev;
>  
> -	for (j = 0; j < ARRAY_SIZE(reg_lists); ++j) {
> -		reg = reg_lists[j].regs;
> -		for (i = 0, prev = -1; i < reg_lists[j].size; i++,
> reg++) {
> -			u32 offset = i915_mmio_reg_offset(*reg);
> +	for (j = 0; j < ARRAY_SIZE(range_lists); ++j) {
> +		range = range_lists[j].regs;
> +		for (i = 0, prev = -1; i < range_lists[j].size; i++,
> range++) {
> +			if (range->end < range->start) {
> +				pr_err("%s: range[%d]:(%06x-%06x) has
> end before start\n",
> +				       __func__, i, range->start,
> range->end);
> +				return -EINVAL;
> +			}
> +
> +			if (prev >= (s32)range->start) {
> +				pr_err("%s: range[%d]:(%06x-%06x) is
> before end of previous (%06x)\n",
> +				       __func__, i, range->start,
> range->end, prev);
> +				return -EINVAL;
> +			}
>  
> -			if (prev >= (s32)offset) {
> -				pr_err("%s: entry[%d]:(%x) is before
> previous (%x)\n",
> -				       __func__, i, offset, prev);
> +			if (range->start % 4) {
> +				pr_err("%s: range[%d]:(%06x-%06x) has
> non-dword-aligned start\n",
> +				       __func__, i, range->start,
> range->end);
>  				return -EINVAL;
>  			}
>  
> -			prev = offset;
> +			prev = range->end;
>  		}
>  	}
>  
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^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [Intel-gfx] [PATCH v2 3/6] drm/i915: Make shadow tables range-based
  2021-07-29 21:55     ` Yokoyama, Caz
@ 2021-07-29 21:59       ` Matt Roper
  2021-08-10 22:02         ` Yokoyama, Caz
  0 siblings, 1 reply; 22+ messages in thread
From: Matt Roper @ 2021-07-29 21:59 UTC (permalink / raw)
  To: Yokoyama, Caz; +Cc: intel-gfx

On Thu, Jul 29, 2021 at 02:55:17PM -0700, Yokoyama, Caz wrote:
> On Thu, 2021-07-29 at 08:21 -0700, Matt Roper wrote:
> > Rather than defining our shadow tables as a list of individual
> > registers, provide them as a list of register ranges; we'll have some
> > ranges of multiple registers being added soon (and we already have a
> > couple adjacent registers that we can squash into a single range
> > now).
> >
> > This change also defines the table with hex literal values rather
> > than
> > symbolic register names; since that's how the tables are defined in
> > the
> > bspec, this change will make it easier to review the tables overall.
> >
> > v2:
> >  - Force signed comparison on range overlap sanity check
> >
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c   |  13 +-
> >  drivers/gpu/drm/i915/intel_uncore.c           | 160 +++++++++-------
> > --
> >  drivers/gpu/drm/i915/intel_uncore.h           |   6 +
> >  drivers/gpu/drm/i915/selftests/intel_uncore.c |  32 ++--
> >  4 files changed, 108 insertions(+), 103 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 9173df59821a..7558414bafb2 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -1963,12 +1963,7 @@ void intel_engine_apply_workarounds(struct
> > intel_engine_cs *engine)
> >       wa_list_apply(engine->gt, &engine->wa_list);
> >  }
> >
> > -struct mcr_range {
> > -     u32 start;
> > -     u32 end;
> > -};
> > -
> > -static const struct mcr_range mcr_ranges_gen8[] = {
> > +static const struct i915_range mcr_ranges_gen8[] = {
> >       { .start = 0x5500, .end = 0x55ff },
> >       { .start = 0x7000, .end = 0x7fff },
> >       { .start = 0x9400, .end = 0x97ff },
> > @@ -1977,7 +1972,7 @@ static const struct mcr_range mcr_ranges_gen8[]
> > = {
> >       {},
> >  };
> >
> > -static const struct mcr_range mcr_ranges_gen12[] = {
> > +static const struct i915_range mcr_ranges_gen12[] = {
> >       { .start =  0x8150, .end =  0x815f },
> >       { .start =  0x9520, .end =  0x955f },
> >       { .start =  0xb100, .end =  0xb3ff },
> > @@ -1986,7 +1981,7 @@ static const struct mcr_range
> > mcr_ranges_gen12[] = {
> >       {},
> >  };
> >
> > -static const struct mcr_range mcr_ranges_xehp[] = {
> > +static const struct i915_range mcr_ranges_xehp[] = {
> >       { .start =  0x4000, .end =  0x4aff },
> >       { .start =  0x5200, .end =  0x52ff },
> >       { .start =  0x5400, .end =  0x7fff },
> > @@ -2004,7 +1999,7 @@ static const struct mcr_range mcr_ranges_xehp[]
> > = {
> >
> >  static bool mcr_range(struct drm_i915_private *i915, u32 offset)
> >  {
> > -     const struct mcr_range *mcr_ranges;
> > +     const struct i915_range *mcr_ranges;
> >       int i;
> >
> >       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> > b/drivers/gpu/drm/i915/intel_uncore.c
> > index ea910f7ee635..2cfbc16f7dee 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -946,101 +946,95 @@ static const struct intel_forcewake_range
> > __vlv_fw_ranges[] = {
> >       find_fw_domain(uncore, offset)
> >
> >  /* *Must* be sorted by offset! See intel_shadow_table_check(). */
> > -static const i915_reg_t gen8_shadowed_regs[] = {
> > -     RING_TAIL(RENDER_RING_BASE),    /* 0x2000 (base) */
> > -     GEN6_RPNSWREQ,                  /* 0xA008 *
> > -     GEN6_RC_VIDEO_FREQ,             /* 0xA00C */
> > -     RING_TAIL(GEN6_BSD_RING_BASE),  /* 0x12000 (base) */
> > -     RING_TAIL(VEBOX_RING_BASE),     /* 0x1a000 (base) */
> > -     RING_TAIL(BLT_RING_BASE),       /* 0x22000 (base) */
> > +static const struct i915_range gen8_shadowed_regs[] = {
> > +     { .start =  0x2030, .end =  0x2030 },
> > +     { .start =  0xA008, .end =  0xA00C },
> > +     { .start = 0x12030, .end = 0x12030 },
> > +     { .start = 0x1a030, .end = 0x1a030 },
> > +     { .start = 0x22030, .end = 0x22030 },
> You are replacing macro defined values by literal values. These macro
> defined values are no longer used in this patch, but used in other
> places such as intel_rps.c:gen6_rps_set(). What plan do you have about
> the same address is defined in 2 ways, i.e. macro and literal value?

These are ranges of registers offsets (similar to what we already do
elsewhere in the driver for multicast ranges, forcewake ranges, etc.),
whereas individual registers used throughout the driver are still
defined in i915_reg.h.  Some of these wind up being single-register
ranges, but that's fine/expected, and some of those single-register
ranges also get extended to cover a larger range by later patches in
this series.


Matt

> -caz
> 
> >       /* TODO: Other registers are not yet used */
> >  };
> >
> > -static const i915_reg_t gen11_shadowed_regs[] = {
> > -     RING_TAIL(RENDER_RING_BASE),                    /* 0x2000
> > (base) */
> > -     RING_EXECLIST_CONTROL(RENDER_RING_BASE),        /* 0x2550 */
> > -     GEN6_RPNSWREQ,                                  /* 0xA008 */
> > -     GEN6_RC_VIDEO_FREQ,                             /* 0xA00C */
> > -     RING_TAIL(BLT_RING_BASE),                       /* 0x22000 (base) */
> > -     RING_EXECLIST_CONTROL(BLT_RING_BASE),           /* 0x22550 */
> > -     RING_TAIL(GEN11_BSD_RING_BASE),                 /* 0x1C0000
> > (base) */
> > -     RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE),     /* 0x1C0550
> > */
> > -     RING_TAIL(GEN11_BSD2_RING_BASE),                /* 0x1C4000 (base) */
> > -     RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE),    /* 0x1C4550
> > */
> > -     RING_TAIL(GEN11_VEBOX_RING_BASE),               /* 0x1C8000 (base) */
> > -     RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE),   /* 0x1C8550
> > */
> > -     RING_TAIL(GEN11_BSD3_RING_BASE),                /* 0x1D0000 (base) */
> > -     RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE),    /* 0x1D0550
> > */
> > -     RING_TAIL(GEN11_BSD4_RING_BASE),                /* 0x1D4000 (base) */
> > -     RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE),    /* 0x1D4550
> > */
> > -     RING_TAIL(GEN11_VEBOX2_RING_BASE),              /* 0x1D8000
> > (base) */
> > -     RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE),  /* 0x1D8550
> > */
> > +static const struct i915_range gen11_shadowed_regs[] = {
> > +     { .start =   0x2030, .end =   0x2030 },
> > +     { .start =   0x2550, .end =   0x2550 },
> > +     { .start =   0xA008, .end =   0xA00C },
> > +     { .start =  0x22030, .end =  0x22030 },
> > +     { .start =  0x22550, .end =  0x22550 },
> > +     { .start = 0x1C0030, .end = 0x1C0030 },
> > +     { .start = 0x1C0550, .end = 0x1C0550 },
> > +     { .start = 0x1C4030, .end = 0x1C4030 },
> > +     { .start = 0x1C4550, .end = 0x1C4550 },
> > +     { .start = 0x1C8030, .end = 0x1C8030 },
> > +     { .start = 0x1C8550, .end = 0x1C8550 },
> > +     { .start = 0x1D0030, .end = 0x1D0030 },
> > +     { .start = 0x1D0550, .end = 0x1D0550 },
> > +     { .start = 0x1D4030, .end = 0x1D4030 },
> > +     { .start = 0x1D4550, .end = 0x1D4550 },
> > +     { .start = 0x1D8030, .end = 0x1D8030 },
> > +     { .start = 0x1D8550, .end = 0x1D8550 },
> >       /* TODO: Other registers are not yet used */
> >  };
> >
> > -static const i915_reg_t gen12_shadowed_regs[] = {
> > -     RING_TAIL(RENDER_RING_BASE),                    /* 0x2000
> > (base) */
> > -     RING_EXECLIST_CONTROL(RENDER_RING_BASE),        /* 0x2550 */
> > -     GEN6_RPNSWREQ,                                  /* 0xA008 */
> > -     GEN6_RC_VIDEO_FREQ,                             /* 0xA00C */
> > -     RING_TAIL(BLT_RING_BASE),                       /* 0x22000 (base) */
> > -     RING_EXECLIST_CONTROL(BLT_RING_BASE),           /* 0x22550 */
> > -     RING_TAIL(GEN11_BSD_RING_BASE),                 /* 0x1C0000
> > (base) */
> > -     RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE),     /* 0x1C0550
> > */
> > -     RING_TAIL(GEN11_BSD2_RING_BASE),                /* 0x1C4000 (base) */
> > -     RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE),    /* 0x1C4550
> > */
> > -     RING_TAIL(GEN11_VEBOX_RING_BASE),               /* 0x1C8000 (base) */
> > -     RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE),   /* 0x1C8550
> > */
> > -     RING_TAIL(GEN11_BSD3_RING_BASE),                /* 0x1D0000 (base) */
> > -     RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE),    /* 0x1D0550
> > */
> > -     RING_TAIL(GEN11_BSD4_RING_BASE),                /* 0x1D4000 (base) */
> > -     RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE),    /* 0x1D4550
> > */
> > -     RING_TAIL(GEN11_VEBOX2_RING_BASE),              /* 0x1D8000
> > (base) */
> > -     RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE),  /* 0x1D8550
> > */
> > +static const struct i915_range gen12_shadowed_regs[] = {
> > +     { .start =   0x2030, .end =   0x2030 },
> > +     { .start =   0x2550, .end =   0x2550 },
> > +     { .start =   0xA008, .end =   0xA00C },
> > +     { .start =  0x22030, .end =  0x22030 },
> > +     { .start =  0x22550, .end =  0x22550 },
> > +     { .start = 0x1C0030, .end = 0x1C0030 },
> > +     { .start = 0x1C0550, .end = 0x1C0550 },
> > +     { .start = 0x1C4030, .end = 0x1C4030 },
> > +     { .start = 0x1C4550, .end = 0x1C4550 },
> > +     { .start = 0x1C8030, .end = 0x1C8030 },
> > +     { .start = 0x1C8550, .end = 0x1C8550 },
> > +     { .start = 0x1D0030, .end = 0x1D0030 },
> > +     { .start = 0x1D0550, .end = 0x1D0550 },
> > +     { .start = 0x1D4030, .end = 0x1D4030 },
> > +     { .start = 0x1D4550, .end = 0x1D4550 },
> > +     { .start = 0x1D8030, .end = 0x1D8030 },
> > +     { .start = 0x1D8550, .end = 0x1D8550 },
> >       /* TODO: Other registers are not yet used */
> >  };
> >
> > -static const i915_reg_t xehp_shadowed_regs[] = {
> > -     RING_TAIL(RENDER_RING_BASE),                    /* 0x2000
> > (base) */
> > -     RING_EXECLIST_CONTROL(RENDER_RING_BASE),        /* 0x2550 */
> > -     GEN6_RPNSWREQ,                                  /* 0xA008 */
> > -     GEN6_RC_VIDEO_FREQ,                             /* 0xA00C */
> > -     RING_TAIL(BLT_RING_BASE),                       /* 0x22000 (base) */
> > -     RING_EXECLIST_CONTROL(BLT_RING_BASE),           /* 0x22550 */
> > -     RING_TAIL(GEN11_BSD_RING_BASE),                 /* 0x1C0000
> > (base) */
> > -     RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE),     /* 0x1C0550
> > */
> > -     RING_TAIL(GEN11_BSD2_RING_BASE),                /* 0x1C4000 (base) */
> > -     RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE),    /* 0x1C4550
> > */
> > -     RING_TAIL(GEN11_VEBOX_RING_BASE),               /* 0x1C8000 (base) */
> > -     RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE),   /* 0x1C8550
> > */
> > -     RING_TAIL(GEN11_BSD3_RING_BASE),                /* 0x1D0000 (base) */
> > -     RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE),    /* 0x1D0550
> > */
> > -     RING_TAIL(GEN11_BSD4_RING_BASE),                /* 0x1D4000 (base) */
> > -     RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE),    /* 0x1D4550
> > */
> > -     RING_TAIL(GEN11_VEBOX2_RING_BASE),              /* 0x1D8000
> > (base) */
> > -     RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE),  /* 0x1D8550
> > */
> > -     RING_TAIL(XEHP_BSD5_RING_BASE),                 /* 0x1E0000
> > (base) */
> > -     RING_EXECLIST_CONTROL(XEHP_BSD5_RING_BASE),     /* 0x1E0550
> > */
> > -     RING_TAIL(XEHP_BSD6_RING_BASE),                 /* 0x1E4000
> > (base) */
> > -     RING_EXECLIST_CONTROL(XEHP_BSD6_RING_BASE),     /* 0x1E4550
> > */
> > -     RING_TAIL(XEHP_VEBOX3_RING_BASE),               /* 0x1E8000 (base) */
> > -     RING_EXECLIST_CONTROL(XEHP_VEBOX3_RING_BASE),   /* 0x1E8550
> > */
> > -     RING_TAIL(XEHP_BSD7_RING_BASE),                 /* 0x1F0000
> > (base) */
> > -     RING_EXECLIST_CONTROL(XEHP_BSD7_RING_BASE),     /* 0x1F0550
> > */
> > -     RING_TAIL(XEHP_BSD8_RING_BASE),                 /* 0x1F4000
> > (base) */
> > -     RING_EXECLIST_CONTROL(XEHP_BSD8_RING_BASE),     /* 0x1F4550
> > */
> > -     RING_TAIL(XEHP_VEBOX4_RING_BASE),               /* 0x1F8000 (base) */
> > -     RING_EXECLIST_CONTROL(XEHP_VEBOX4_RING_BASE),   /* 0x1F8550
> > */
> > +static const struct i915_range xehp_shadowed_regs[] = {
> > +     { .start =   0x2000, .end =   0x2030 },
> > +     { .start =   0x2550, .end =   0x2550 },
> > +     { .start =   0xA008, .end =   0xA00C },
> > +     { .start =  0x22030, .end =  0x22030 },
> > +     { .start =  0x22550, .end =  0x22550 },
> > +     { .start = 0x1C0030, .end = 0x1C0030 },
> > +     { .start = 0x1C0550, .end = 0x1C0550 },
> > +     { .start = 0x1C4030, .end = 0x1C4030 },
> > +     { .start = 0x1C4550, .end = 0x1C4550 },
> > +     { .start = 0x1C8030, .end = 0x1C8030 },
> > +     { .start = 0x1C8550, .end = 0x1C8550 },
> > +     { .start = 0x1D0030, .end = 0x1D0030 },
> > +     { .start = 0x1D0550, .end = 0x1D0550 },
> > +     { .start = 0x1D4030, .end = 0x1D4030 },
> > +     { .start = 0x1D4550, .end = 0x1D4550 },
> > +     { .start = 0x1D8030, .end = 0x1D8030 },
> > +     { .start = 0x1D8550, .end = 0x1D8550 },
> > +     { .start = 0x1E0030, .end = 0x1E0030 },
> > +     { .start = 0x1E0550, .end = 0x1E0550 },
> > +     { .start = 0x1E4030, .end = 0x1E4030 },
> > +     { .start = 0x1E4550, .end = 0x1E4550 },
> > +     { .start = 0x1E8030, .end = 0x1E8030 },
> > +     { .start = 0x1E8550, .end = 0x1E8550 },
> > +     { .start = 0x1F0030, .end = 0x1F0030 },
> > +     { .start = 0x1F0550, .end = 0x1F0550 },
> > +     { .start = 0x1F4030, .end = 0x1F4030 },
> > +     { .start = 0x1F4550, .end = 0x1F4550 },
> > +     { .start = 0x1F8030, .end = 0x1F8030 },
> > +     { .start = 0x1F8550, .end = 0x1F8550 },
> >       /* TODO: Other registers are not yet used */
> >  };
> >
> > -static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
> > +static int mmio_range_cmp(u32 key, const struct i915_range *range)
> >  {
> > -     u32 offset = i915_mmio_reg_offset(*reg);
> > -
> > -     if (key < offset)
> > +     if (key < range->start)
> >               return -1;
> > -     else if (key > offset)
> > +     else if (key > range->end)
> >               return 1;
> >       else
> >               return 0;
> > @@ -1049,9 +1043,9 @@ static int mmio_reg_cmp(u32 key, const
> > i915_reg_t *reg)
> >  #define __is_X_shadowed(x) \
> >  static bool is_##x##_shadowed(u32 offset) \
> >  { \
> > -     const i915_reg_t *regs = x##_shadowed_regs; \
> > +     const struct i915_range *regs = x##_shadowed_regs; \
> >       return BSEARCH(offset, regs, ARRAY_SIZE(x##_shadowed_regs), \
> > -                    mmio_reg_cmp); \
> > +                    mmio_range_cmp); \
> >  }
> >
> >  __is_X_shadowed(gen8)
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.h
> > b/drivers/gpu/drm/i915/intel_uncore.h
> > index 3c0b0a8b5250..531665b08039 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.h
> > +++ b/drivers/gpu/drm/i915/intel_uncore.h
> > @@ -119,6 +119,12 @@ struct intel_forcewake_range {
> >       enum forcewake_domains domains;
> >  };
> >
> > +/* Other register ranges (e.g., shadow tables, MCR tables, etc.) */
> > +struct i915_range {
> > +     u32 start;
> > +     u32 end;
> > +};
> > +
> >  struct intel_uncore {
> >       void __iomem *regs;
> >
> > diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> > b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> > index 720b60853f8b..d6a9c11afa23 100644
> > --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> > @@ -62,30 +62,40 @@ static int intel_fw_table_check(const struct
> > intel_forcewake_range *ranges,
> >  static int intel_shadow_table_check(void)
> >  {
> >       struct {
> > -             const i915_reg_t *regs;
> > +             const struct i915_range *regs;
> >               unsigned int size;
> > -     } reg_lists[] = {
> > +     } range_lists[] = {
> >               { gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) },
> >               { gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs)
> > },
> >               { gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs)
> > },
> >               { xehp_shadowed_regs, ARRAY_SIZE(xehp_shadowed_regs) },
> >       };
> > -     const i915_reg_t *reg;
> > +     const struct i915_range *range;
> >       unsigned int i, j;
> >       s32 prev;
> >
> > -     for (j = 0; j < ARRAY_SIZE(reg_lists); ++j) {
> > -             reg = reg_lists[j].regs;
> > -             for (i = 0, prev = -1; i < reg_lists[j].size; i++,
> > reg++) {
> > -                     u32 offset = i915_mmio_reg_offset(*reg);
> > +     for (j = 0; j < ARRAY_SIZE(range_lists); ++j) {
> > +             range = range_lists[j].regs;
> > +             for (i = 0, prev = -1; i < range_lists[j].size; i++,
> > range++) {
> > +                     if (range->end < range->start) {
> > +                             pr_err("%s: range[%d]:(%06x-%06x) has
> > end before start\n",
> > +                                    __func__, i, range->start,
> > range->end);
> > +                             return -EINVAL;
> > +                     }
> > +
> > +                     if (prev >= (s32)range->start) {
> > +                             pr_err("%s: range[%d]:(%06x-%06x) is
> > before end of previous (%06x)\n",
> > +                                    __func__, i, range->start,
> > range->end, prev);
> > +                             return -EINVAL;
> > +                     }
> >
> > -                     if (prev >= (s32)offset) {
> > -                             pr_err("%s: entry[%d]:(%x) is before
> > previous (%x)\n",
> > -                                    __func__, i, offset, prev);
> > +                     if (range->start % 4) {
> > +                             pr_err("%s: range[%d]:(%06x-%06x) has
> > non-dword-aligned start\n",
> > +                                    __func__, i, range->start,
> > range->end);
> >                               return -EINVAL;
> >                       }
> >
> > -                     prev = offset;
> > +                     prev = range->end;
> >               }
> >       }
> >

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [Intel-gfx] [PATCH 6/6] drm/i915/xehp: Xe_HP shadowed registers are a strict superset of gen12
  2021-07-29  5:41 ` [Intel-gfx] [PATCH 6/6] drm/i915/xehp: Xe_HP shadowed registers are a strict superset of gen12 Matt Roper
@ 2021-07-29 23:36   ` Yokoyama, Caz
  0 siblings, 0 replies; 22+ messages in thread
From: Yokoyama, Caz @ 2021-07-29 23:36 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx

Reviewed-by: az Yokoyama <caz.yokoyama@intel.com>
-caz

On Wed, 2021-07-28 at 22:41 -0700, Matt Roper wrote:
> The list of shadowed registers on XeHP is identical to the set for
> earlier gen12 platforms, with additional ranges added for the new VCS
> and VECS engines.  Since those register ranges were reserved on
> earlier
> gen12 platforms, it's safe to consolidate to a single gen12 table
> rather than tracking Xe_HP separately.
> 
> Bspec: 52077
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_uncore.c           | 50 +++++----------
> ----
>  drivers/gpu/drm/i915/selftests/intel_uncore.c |  1 -
>  2 files changed, 12 insertions(+), 39 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 42acf106a6df..4abe9df5fb76 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1006,39 +1006,24 @@ static const struct i915_range
> gen12_shadowed_regs[] = {
>  	{ .start = 0x1D4510, .end = 0x1D4550 },
>  	{ .start = 0x1D8030, .end = 0x1D8030 },
>  	{ .start = 0x1D8510, .end = 0x1D8550 },
> -};
>  
> -static const struct i915_range xehp_shadowed_regs[] = {
> -	{ .start =   0x2000, .end =   0x2030 },
> -	{ .start =   0x2550, .end =   0x2550 },
> -	{ .start =   0xA008, .end =   0xA00C },
> -	{ .start =  0x22030, .end =  0x22030 },
> -	{ .start =  0x22550, .end =  0x22550 },
> -	{ .start = 0x1C0030, .end = 0x1C0030 },
> -	{ .start = 0x1C0550, .end = 0x1C0550 },
> -	{ .start = 0x1C4030, .end = 0x1C4030 },
> -	{ .start = 0x1C4550, .end = 0x1C4550 },
> -	{ .start = 0x1C8030, .end = 0x1C8030 },
> -	{ .start = 0x1C8550, .end = 0x1C8550 },
> -	{ .start = 0x1D0030, .end = 0x1D0030 },
> -	{ .start = 0x1D0550, .end = 0x1D0550 },
> -	{ .start = 0x1D4030, .end = 0x1D4030 },
> -	{ .start = 0x1D4550, .end = 0x1D4550 },
> -	{ .start = 0x1D8030, .end = 0x1D8030 },
> -	{ .start = 0x1D8550, .end = 0x1D8550 },
> +	/*
> +	 * The rest of these ranges are specific to Xe_HP and beyond,
> but
> +	 * are reserved/unused ranges on earlier gen12 platforms, so
> they can
> +	 * be safely added to the gen12 table.
> +	 */
>  	{ .start = 0x1E0030, .end = 0x1E0030 },
> -	{ .start = 0x1E0550, .end = 0x1E0550 },
> +	{ .start = 0x1E0510, .end = 0x1E0550 },
>  	{ .start = 0x1E4030, .end = 0x1E4030 },
> -	{ .start = 0x1E4550, .end = 0x1E4550 },
> +	{ .start = 0x1E4510, .end = 0x1E4550 },
>  	{ .start = 0x1E8030, .end = 0x1E8030 },
> -	{ .start = 0x1E8550, .end = 0x1E8550 },
> +	{ .start = 0x1E8510, .end = 0x1E8550 },
>  	{ .start = 0x1F0030, .end = 0x1F0030 },
> -	{ .start = 0x1F0550, .end = 0x1F0550 },
> +	{ .start = 0x1F0510, .end = 0x1F0550 },
>  	{ .start = 0x1F4030, .end = 0x1F4030 },
> -	{ .start = 0x1F4550, .end = 0x1F4550 },
> +	{ .start = 0x1F4510, .end = 0x1F4550 },
>  	{ .start = 0x1F8030, .end = 0x1F8030 },
> -	{ .start = 0x1F8550, .end = 0x1F8550 },
> -	/* TODO: Other registers are not yet used */
> +	{ .start = 0x1F8510, .end = 0x1F8550 },
>  };
>  
>  static int mmio_range_cmp(u32 key, const struct i915_range *range)
> @@ -1062,7 +1047,6 @@ static bool is_##x##_shadowed(u32 offset) \
>  __is_X_shadowed(gen8)
>  __is_X_shadowed(gen11)
>  __is_X_shadowed(gen12)
> -__is_X_shadowed(xehp)
>  
>  static enum forcewake_domains
>  gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t
> reg)
> @@ -1126,15 +1110,6 @@ static const struct intel_forcewake_range
> __chv_fw_ranges[] = {
>  	__fwd; \
>  })
>  
> -#define __xehp_fwtable_reg_write_fw_domains(uncore, offset) \
> -({ \
> -	enum forcewake_domains __fwd = 0; \
> -	const u32 __offset = (offset); \
> -	if (!is_xehp_shadowed(__offset)) \
> -		__fwd = find_fw_domain(uncore, __offset); \
> -	__fwd; \
> -})
> -
>  /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
>  static const struct intel_forcewake_range __gen9_fw_ranges[] = {
>  	GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT),
> @@ -1710,7 +1685,6 @@ __gen_write(func, 8) \
>  __gen_write(func, 16) \
>  __gen_write(func, 32)
>  
> -__gen_reg_write_funcs(xehp_fwtable);
>  __gen_reg_write_funcs(gen12_fwtable);
>  __gen_reg_write_funcs(gen11_fwtable);
>  __gen_reg_write_funcs(fwtable);
> @@ -2087,7 +2061,7 @@ static int uncore_forcewake_init(struct
> intel_uncore *uncore)
>  
>  	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
>  		ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);
> -		ASSIGN_WRITE_MMIO_VFUNCS(uncore, xehp_fwtable);
> +		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);
>  		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
>  	} else if (GRAPHICS_VER(i915) >= 12) {
>  		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
> diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> index d3e36ed32646..63b75585865f 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> @@ -68,7 +68,6 @@ static int intel_shadow_table_check(void)
>  		{ gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) },
>  		{ gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs)
> },
>  		{ gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs)
> },
> -		{ xehp_shadowed_regs, ARRAY_SIZE(xehp_shadowed_regs) },
>  	};
>  	const struct i915_range *range;
>  	unsigned int i, j;
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 22+ messages in thread

* [Intel-gfx] ✓ Fi.CI.IGT: success for Forcewake and shadowed register updates (rev2)
  2021-07-29  5:41 [Intel-gfx] [PATCH 0/6] Forcewake and shadowed register updates Matt Roper
                   ` (10 preceding siblings ...)
  2021-07-29 20:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-07-30  8:36 ` Patchwork
  11 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2021-07-30  8:36 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 30269 bytes --]

== Series Details ==

Series: Forcewake and shadowed register updates (rev2)
URL   : https://patchwork.freedesktop.org/series/93158/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10420_full -> Patchwork_20742_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_20742_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@display-3x:
    - shard-tglb:         NOTRUN -> [SKIP][1] ([i915#1839])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-tglb3/igt@feature_discovery@display-3x.html

  * igt@gem_ctx_persistence@legacy-engines-mixed:
    - shard-snb:          NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +1 similar issue
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-snb6/igt@gem_ctx_persistence@legacy-engines-mixed.html

  * igt@gem_eio@unwedge-stress:
    - shard-tglb:         [PASS][3] -> [TIMEOUT][4] ([i915#2369] / [i915#3063] / [i915#3648])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-tglb8/igt@gem_eio@unwedge-stress.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-tglb2/igt@gem_eio@unwedge-stress.html
    - shard-snb:          NOTRUN -> [FAIL][5] ([i915#3354])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-snb6/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_capture@pi@vecs0:
    - shard-skl:          [PASS][6] -> [INCOMPLETE][7] ([i915#198] / [i915#2624])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl10/igt@gem_exec_capture@pi@vecs0.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-skl3/igt@gem_exec_capture@pi@vecs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-kbl:          NOTRUN -> [FAIL][8] ([i915#2842])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-kbl2/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][9] ([i915#2842])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-iclb4/igt@gem_exec_fair@basic-none@vcs1.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         NOTRUN -> [FAIL][10] ([i915#2842])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-iclb:         [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-iclb8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-iclb1/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_params@no-vebox:
    - shard-iclb:         NOTRUN -> [SKIP][13] ([fdo#109283])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-iclb4/igt@gem_exec_params@no-vebox.html

  * igt@gem_mmap_gtt@cpuset-big-copy:
    - shard-iclb:         [PASS][14] -> [FAIL][15] ([i915#2428])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-iclb7/igt@gem_mmap_gtt@cpuset-big-copy.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-iclb8/igt@gem_mmap_gtt@cpuset-big-copy.html

  * igt@gem_userptr_blits@input-checking:
    - shard-snb:          NOTRUN -> [DMESG-WARN][16] ([i915#3002])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-snb6/igt@gem_userptr_blits@input-checking.html

  * igt@gen3_render_tiledx_blits:
    - shard-tglb:         NOTRUN -> [SKIP][17] ([fdo#109289])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-tglb3/igt@gen3_render_tiledx_blits.html

  * igt@gen9_exec_parse@bb-start-param:
    - shard-tglb:         NOTRUN -> [SKIP][18] ([i915#2856])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-tglb3/igt@gen9_exec_parse@bb-start-param.html

  * igt@i915_pm_dc@dc5-dpms:
    - shard-skl:          NOTRUN -> [FAIL][19] ([i915#545])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-skl5/igt@i915_pm_dc@dc5-dpms.html

  * igt@kms_atomic_transition@plane-all-modeset-transition:
    - shard-iclb:         NOTRUN -> [SKIP][20] ([i915#1769])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-iclb4/igt@kms_atomic_transition@plane-all-modeset-transition.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-0:
    - shard-glk:          [PASS][21] -> [DMESG-WARN][22] ([i915#118] / [i915#95])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-glk6/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-glk4/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-apl:          NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#3777])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-apl8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
    - shard-skl:          NOTRUN -> [SKIP][24] ([fdo#109271]) +73 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-skl5/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][25] ([i915#3689])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-tglb3/igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@vga-hpd-without-ddc:
    - shard-snb:          NOTRUN -> [SKIP][26] ([fdo#109271] / [fdo#111827]) +12 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-snb6/igt@kms_chamelium@vga-hpd-without-ddc.html

  * igt@kms_color@pipe-b-ctm-0-5:
    - shard-skl:          [PASS][27] -> [DMESG-WARN][28] ([i915#1982])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl10/igt@kms_color@pipe-b-ctm-0-5.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-skl3/igt@kms_color@pipe-b-ctm-0-5.html

  * igt@kms_color_chamelium@pipe-b-degamma:
    - shard-kbl:          NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-kbl1/igt@kms_color_chamelium@pipe-b-degamma.html

  * igt@kms_color_chamelium@pipe-b-gamma:
    - shard-iclb:         NOTRUN -> [SKIP][30] ([fdo#109284] / [fdo#111827]) +2 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-iclb4/igt@kms_color_chamelium@pipe-b-gamma.html

  * igt@kms_color_chamelium@pipe-c-ctm-negative:
    - shard-skl:          NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +5 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-skl2/igt@kms_color_chamelium@pipe-c-ctm-negative.html

  * igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes:
    - shard-apl:          NOTRUN -> [SKIP][32] ([fdo#109271] / [fdo#111827]) +12 similar issues
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-apl1/igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-iclb:         NOTRUN -> [SKIP][33] ([i915#3116])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-iclb4/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@legacy:
    - shard-kbl:          NOTRUN -> [TIMEOUT][34] ([i915#1319])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-kbl1/igt@kms_content_protection@legacy.html
    - shard-apl:          NOTRUN -> [TIMEOUT][35] ([i915#1319])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-apl1/igt@kms_content_protection@legacy.html

  * igt@kms_cursor_crc@pipe-a-cursor-max-size-onscreen:
    - shard-kbl:          NOTRUN -> [SKIP][36] ([fdo#109271]) +42 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-max-size-onscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-256x85-random:
    - shard-apl:          NOTRUN -> [FAIL][37] ([i915#3444])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-apl8/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html

  * igt@kms_cursor_crc@pipe-c-cursor-256x256-offscreen:
    - shard-tglb:         [PASS][38] -> [DMESG-WARN][39] ([i915#2868])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-tglb5/igt@kms_cursor_crc@pipe-c-cursor-256x256-offscreen.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-tglb5/igt@kms_cursor_crc@pipe-c-cursor-256x256-offscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-32x10-rapid-movement:
    - shard-tglb:         NOTRUN -> [SKIP][40] ([i915#3359])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-tglb3/igt@kms_cursor_crc@pipe-c-cursor-32x10-rapid-movement.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [PASS][41] -> [DMESG-WARN][42] ([i915#180]) +1 similar issue
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          [PASS][43] -> [FAIL][44] ([i915#2346] / [i915#533])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@pipe-d-torture-move:
    - shard-iclb:         NOTRUN -> [SKIP][45] ([fdo#109278]) +6 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-iclb4/igt@kms_cursor_legacy@pipe-d-torture-move.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
    - shard-snb:          [PASS][46] -> [SKIP][47] ([fdo#109271]) +4 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-snb2/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-snb2/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][48] ([i915#180]) +2 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-kbl6/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * igt@kms_frontbuffer_tracking@fbc-2p-rte:
    - shard-tglb:         NOTRUN -> [SKIP][49] ([fdo#111825]) +6 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-2p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt:
    - shard-snb:          NOTRUN -> [SKIP][50] ([fdo#109271]) +175 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-snb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt:
    - shard-iclb:         NOTRUN -> [SKIP][51] ([fdo#109280]) +3 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-iclb4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          NOTRUN -> [FAIL][52] ([fdo#108145] / [i915#265])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
    - shard-apl:          NOTRUN -> [FAIL][53] ([fdo#108145] / [i915#265])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][54] ([i915#265])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][55] -> [FAIL][56] ([fdo#108145] / [i915#265]) +1 similar issue
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_plane_lowres@pipe-c-tiling-yf:
    - shard-tglb:         NOTRUN -> [SKIP][57] ([fdo#112054])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-tglb3/igt@kms_plane_lowres@pipe-c-tiling-yf.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
    - shard-apl:          NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#658]) +3 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-apl1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         NOTRUN -> [SKIP][59] ([fdo#109642] / [fdo#111068] / [i915#658])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-iclb4/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-tglb:         NOTRUN -> [FAIL][60] ([i915#132] / [i915#3467])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-tglb3/igt@kms_psr@psr2_cursor_plane_move.html

  * igt@kms_psr@psr2_primary_mmap_gtt:
    - shard-iclb:         [PASS][61] -> [SKIP][62] ([fdo#109441]) +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-iclb6/igt@kms_psr@psr2_primary_mmap_gtt.html

  * igt@kms_writeback@writeback-check-output:
    - shard-apl:          NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#2437])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-apl1/igt@kms_writeback@writeback-check-output.html

  * igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame:
    - shard-apl:          NOTRUN -> [SKIP][64] ([fdo#109271]) +164 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-apl1/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html

  * igt@perf@polling-parameterized:
    - shard-skl:          [PASS][65] -> [FAIL][66] ([i915#1542])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl1/igt@perf@polling-parameterized.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-skl10/igt@perf@polling-parameterized.html

  * igt@sysfs_clients@fair-1:
    - shard-apl:          NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#2994]) +2 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-apl8/igt@sysfs_clients@fair-1.html

  * igt@sysfs_clients@fair-3:
    - shard-skl:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2994])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-skl5/igt@sysfs_clients@fair-3.html

  * igt@sysfs_heartbeat_interval@precise@vecs0:
    - shard-iclb:         [PASS][69] -> [FAIL][70] ([i915#1755])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-iclb8/igt@sysfs_heartbeat_interval@precise@vecs0.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-iclb1/igt@sysfs_heartbeat_interval@precise@vecs0.html

  
#### Possible fixes ####

  * igt@feature_discovery@psr2:
    - {shard-rkl}:        [SKIP][71] ([i915#658]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-5/igt@feature_discovery@psr2.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-rkl-6/igt@feature_discovery@psr2.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
    - shard-glk:          [FAIL][73] ([i915#2842]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-glk9/igt@gem_exec_fair@basic-none-vip@rcs0.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-glk5/igt@gem_exec_fair@basic-none-vip@rcs0.html

  * igt@gem_exec_reloc@basic-scanout@vecs0:
    - {shard-rkl}:        [SKIP][75] ([i915#3639]) -> [PASS][76] +3 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-2/igt@gem_exec_reloc@basic-scanout@vecs0.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-rkl-6/igt@gem_exec_reloc@basic-scanout@vecs0.html

  * igt@gem_exec_whisper@basic-queues-all:
    - shard-glk:          [DMESG-WARN][77] ([i915#118] / [i915#95]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-glk8/igt@gem_exec_whisper@basic-queues-all.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-glk9/igt@gem_exec_whisper@basic-queues-all.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [SKIP][79] ([i915#2190]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-tglb6/igt@gem_huc_copy@huc-copy.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-tglb3/igt@gem_huc_copy@huc-copy.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-skl:          [INCOMPLETE][81] ([i915#198]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl2/igt@gem_workarounds@suspend-resume-context.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-skl5/igt@gem_workarounds@suspend-resume-context.html

  * igt@i915_pm_backlight@fade_with_suspend:
    - shard-skl:          [INCOMPLETE][83] ([i915#146] / [i915#198]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl1/igt@i915_pm_backlight@fade_with_suspend.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-skl2/igt@i915_pm_backlight@fade_with_suspend.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [FAIL][85] ([i915#454]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-iclb5/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rpm@gem-execbuf-stress:
    - {shard-rkl}:        [SKIP][87] ([i915#3844] / [i915#579]) -> [PASS][88] +3 similar issues
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-6/igt@i915_pm_rpm@gem-execbuf-stress.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-rkl-1/igt@i915_pm_rpm@gem-execbuf-stress.html

  * igt@kms_atomic@test-only:
    - {shard-rkl}:        [SKIP][89] ([i915#1845]) -> [PASS][90] +13 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-2/igt@kms_atomic@test-only.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-rkl-6/igt@kms_atomic@test-only.html

  * igt@kms_big_fb@linear-64bpp-rotate-180:
    - {shard-rkl}:        [SKIP][91] ([i915#3638]) -> [PASS][92] +1 similar issue
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-5/igt@kms_big_fb@linear-64bpp-rotate-180.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-rkl-6/igt@kms_big_fb@linear-64bpp-rotate-180.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - {shard-rkl}:        [SKIP][93] ([i915#3721]) -> [PASS][94] +2 similar issues
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-iclb:         [DMESG-WARN][95] ([i915#3621]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-iclb1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-iclb4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
    - {shard-rkl}:        [FAIL][97] ([i915#3678]) -> [PASS][98] +6 similar issues
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-5/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-rkl-6/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_color@pipe-c-degamma:
    - {shard-rkl}:        [SKIP][99] ([i915#1149] / [i915#1849]) -> [PASS][100] +3 similar issues
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-5/igt@kms_color@pipe-c-degamma.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-rkl-6/igt@kms_color@pipe-c-degamma.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen:
    - {shard-rkl}:        [SKIP][101] ([fdo#112022]) -> [PASS][102] +11 similar issues
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-2/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic:
    - {shard-rkl}:        [SKIP][103] ([fdo#111825]) -> [PASS][104] +6 similar issues
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-2/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-rkl-6/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html

  * igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled:
    - {shard-rkl}:        [SKIP][105] ([fdo#111314]) -> [PASS][106] +3 similar issues
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][107] ([i915#79]) -> [PASS][108]
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1:
    - shard-glk:          [FAIL][109] ([i915#2122]) -> [PASS][110]
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-apl:          [DMESG-WARN][111] ([i915#180]) -> [PASS][112] +1 similar issue
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt:
    - shard-snb:          [SKIP][113] ([fdo#109271]) -> [PASS][114]
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-snb6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-snb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite:
    - shard-glk:          [FAIL][115] ([i915#2546]) -> [PASS][116]
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-glk5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-glk3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render:
    - shard-tglb:         [INCOMPLETE][117] -> [PASS][118]
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-skl:          [FAIL][119] ([i915#1188]) -> [PASS][120]
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-skl3/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
    - {shard-rkl}:        [SKIP][121] ([i915#1849]) -> [PASS][122] +37 similar issues
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-5/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-rkl-6/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
    - shard-kbl:          [DMESG-WARN][123] ([i915#180]) -> [PASS][124] +4 similar issues
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [FAIL][125] ([fdo#108145] / [i915#265]) -> [PASS][126]
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
    - {shard-rkl}:        [SKIP][127] ([i915#1849] / [i915#3558]) -> [PASS][128] +1 similar issue
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-5/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-rkl-6/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html

  * igt@kms_psr@sprite_plane_onoff:
    - {shard-rkl}:        [SKIP][129] ([i915#1072]) -> [PASS][130] +3 similar issues
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-5/igt@kms_psr@sprite_plane_onoff.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-rkl-6/igt@kms_psr@sprite_plane_onoff.html

  * igt@perf@polling-small-buf:
    - shard-skl:          [FAIL][131] ([i915#1722]) -> [PASS][132]
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl6/igt@perf@polling-small-buf.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-skl10/igt@perf@polling-small-buf.html

  * igt@perf_pmu@rc6-runtime-pm-long:
    - {shard-rkl}:        [SKIP][133] ([i915#293]) -> [PASS][134]
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-6/igt@perf_pmu@rc6-runtime-pm-long.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-rkl-5/igt@perf_pmu@rc6-runtime-pm-long.html

  * igt@sysfs_heartbeat_interval@precise@vecs0:
    - shard-skl:          [FAIL][135] ([i915#1755]) -> [PASS][136]
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl9/igt@sysfs_heartbeat_interval@precise@vecs0.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-skl6/igt@sysfs_heartbeat_interval@precise@vecs0.html

  * igt@sysfs_timeslice_duration@timeout@rcs0:
    - {shard-rkl}:        [FAIL][137] ([i915#3259]) -> [PASS][138] +3 similar issues
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-2/igt@sysfs_timeslice_duration@timeout@rcs0.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-rkl-1/igt@sysfs_timeslice_duration@timeout@rcs0.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-iclb:         [SKIP][139] ([i915#588]) -> [SKIP][140] ([i915#658])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-iclb6/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-skl:          [FAIL][141] ([i915#3743]) -> [FAIL][142] ([i915#3722])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-skl8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-3:
    - shard-iclb:         [SKIP][143] ([i915#2920]) -> [SKIP][144] ([i915#658]) +1 similar issue
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/shard-iclb6/igt@kms_psr2_sf@plane-

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/index.html

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^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [Intel-gfx] [PATCH v2 3/6] drm/i915: Make shadow tables range-based
  2021-07-29 21:59       ` Matt Roper
@ 2021-08-10 22:02         ` Yokoyama, Caz
  0 siblings, 0 replies; 22+ messages in thread
From: Yokoyama, Caz @ 2021-08-10 22:02 UTC (permalink / raw)
  To: Roper, Matthew D; +Cc: intel-gfx

Reviewed-by: Caz Yokoyama <caz.yokoyama@intel.com>
-caz

On Thu, 2021-07-29 at 14:59 -0700, Matt Roper wrote:
> On Thu, Jul 29, 2021 at 02:55:17PM -0700, Yokoyama, Caz wrote:
> > On Thu, 2021-07-29 at 08:21 -0700, Matt Roper wrote:
> > > Rather than defining our shadow tables as a list of individual
> > > registers, provide them as a list of register ranges; we'll have
> > > some
> > > ranges of multiple registers being added soon (and we already
> > > have a
> > > couple adjacent registers that we can squash into a single range
> > > now).
> > > 
> > > This change also defines the table with hex literal values rather
> > > than
> > > symbolic register names; since that's how the tables are defined
> > > in
> > > the
> > > bspec, this change will make it easier to review the tables
> > > overall.
> > > 
> > > v2:
> > >  - Force signed comparison on range overlap sanity check
> > > 
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/gt/intel_workarounds.c   |  13 +-
> > >  drivers/gpu/drm/i915/intel_uncore.c           | 160 +++++++++---
> > > ----
> > > --
> > >  drivers/gpu/drm/i915/intel_uncore.h           |   6 +
> > >  drivers/gpu/drm/i915/selftests/intel_uncore.c |  32 ++--
> > >  4 files changed, 108 insertions(+), 103 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > index 9173df59821a..7558414bafb2 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > @@ -1963,12 +1963,7 @@ void intel_engine_apply_workarounds(struct
> > > intel_engine_cs *engine)
> > >       wa_list_apply(engine->gt, &engine->wa_list);
> > >  }
> > > 
> > > -struct mcr_range {
> > > -     u32 start;
> > > -     u32 end;
> > > -};
> > > -
> > > -static const struct mcr_range mcr_ranges_gen8[] = {
> > > +static const struct i915_range mcr_ranges_gen8[] = {
> > >       { .start = 0x5500, .end = 0x55ff },
> > >       { .start = 0x7000, .end = 0x7fff },
> > >       { .start = 0x9400, .end = 0x97ff },
> > > @@ -1977,7 +1972,7 @@ static const struct mcr_range
> > > mcr_ranges_gen8[]
> > > = {
> > >       {},
> > >  };
> > > 
> > > -static const struct mcr_range mcr_ranges_gen12[] = {
> > > +static const struct i915_range mcr_ranges_gen12[] = {
> > >       { .start =  0x8150, .end =  0x815f },
> > >       { .start =  0x9520, .end =  0x955f },
> > >       { .start =  0xb100, .end =  0xb3ff },
> > > @@ -1986,7 +1981,7 @@ static const struct mcr_range
> > > mcr_ranges_gen12[] = {
> > >       {},
> > >  };
> > > 
> > > -static const struct mcr_range mcr_ranges_xehp[] = {
> > > +static const struct i915_range mcr_ranges_xehp[] = {
> > >       { .start =  0x4000, .end =  0x4aff },
> > >       { .start =  0x5200, .end =  0x52ff },
> > >       { .start =  0x5400, .end =  0x7fff },
> > > @@ -2004,7 +1999,7 @@ static const struct mcr_range
> > > mcr_ranges_xehp[]
> > > = {
> > > 
> > >  static bool mcr_range(struct drm_i915_private *i915, u32 offset)
> > >  {
> > > -     const struct mcr_range *mcr_ranges;
> > > +     const struct i915_range *mcr_ranges;
> > >       int i;
> > > 
> > >       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> > > b/drivers/gpu/drm/i915/intel_uncore.c
> > > index ea910f7ee635..2cfbc16f7dee 100644
> > > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > > @@ -946,101 +946,95 @@ static const struct intel_forcewake_range
> > > __vlv_fw_ranges[] = {
> > >       find_fw_domain(uncore, offset)
> > > 
> > >  /* *Must* be sorted by offset! See intel_shadow_table_check().
> > > */
> > > -static const i915_reg_t gen8_shadowed_regs[] = {
> > > -     RING_TAIL(RENDER_RING_BASE),    /* 0x2000 (base) */
> > > -     GEN6_RPNSWREQ,                  /* 0xA008 *
> > > -     GEN6_RC_VIDEO_FREQ,             /* 0xA00C */
> > > -     RING_TAIL(GEN6_BSD_RING_BASE),  /* 0x12000 (base) */
> > > -     RING_TAIL(VEBOX_RING_BASE),     /* 0x1a000 (base) */
> > > -     RING_TAIL(BLT_RING_BASE),       /* 0x22000 (base) */
> > > +static const struct i915_range gen8_shadowed_regs[] = {
> > > +     { .start =  0x2030, .end =  0x2030 },
> > > +     { .start =  0xA008, .end =  0xA00C },
> > > +     { .start = 0x12030, .end = 0x12030 },
> > > +     { .start = 0x1a030, .end = 0x1a030 },
> > > +     { .start = 0x22030, .end = 0x22030 },
> > You are replacing macro defined values by literal values. These
> > macro
> > defined values are no longer used in this patch, but used in other
> > places such as intel_rps.c:gen6_rps_set(). What plan do you have
> > about
> > the same address is defined in 2 ways, i.e. macro and literal
> > value?
> 
> These are ranges of registers offsets (similar to what we already do
> elsewhere in the driver for multicast ranges, forcewake ranges,
> etc.),
> whereas individual registers used throughout the driver are still
> defined in i915_reg.h.  Some of these wind up being single-register
> ranges, but that's fine/expected, and some of those single-register
> ranges also get extended to cover a larger range by later patches in
> this series.
> 
> 
> Matt
> 
> > -caz
> > 
> > >       /* TODO: Other registers are not yet used */
> > >  };
> > > 
> > > -static const i915_reg_t gen11_shadowed_regs[] = {
> > > -     RING_TAIL(RENDER_RING_BASE),                    /* 0x2000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(RENDER_RING_BASE),        /* 0x2550
> > > */
> > > -     GEN6_RPNSWREQ,                                  /* 0xA008
> > > */
> > > -     GEN6_RC_VIDEO_FREQ,                             /* 0xA00C
> > > */
> > > -     RING_TAIL(BLT_RING_BASE),                       /* 0x22000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(BLT_RING_BASE),           /* 0x22550
> > > */
> > > -     RING_TAIL(GEN11_BSD_RING_BASE),                 /* 0x1C0000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE),     /* 0x1C0550
> > > */
> > > -     RING_TAIL(GEN11_BSD2_RING_BASE),                /* 0x1C4000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE),    /* 0x1C4550
> > > */
> > > -     RING_TAIL(GEN11_VEBOX_RING_BASE),               /* 0x1C8000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE),   /* 0x1C8550
> > > */
> > > -     RING_TAIL(GEN11_BSD3_RING_BASE),                /* 0x1D0000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE),    /* 0x1D0550
> > > */
> > > -     RING_TAIL(GEN11_BSD4_RING_BASE),                /* 0x1D4000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE),    /* 0x1D4550
> > > */
> > > -     RING_TAIL(GEN11_VEBOX2_RING_BASE),              /* 0x1D8000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE),  /* 0x1D8550
> > > */
> > > +static const struct i915_range gen11_shadowed_regs[] = {
> > > +     { .start =   0x2030, .end =   0x2030 },
> > > +     { .start =   0x2550, .end =   0x2550 },
> > > +     { .start =   0xA008, .end =   0xA00C },
> > > +     { .start =  0x22030, .end =  0x22030 },
> > > +     { .start =  0x22550, .end =  0x22550 },
> > > +     { .start = 0x1C0030, .end = 0x1C0030 },
> > > +     { .start = 0x1C0550, .end = 0x1C0550 },
> > > +     { .start = 0x1C4030, .end = 0x1C4030 },
> > > +     { .start = 0x1C4550, .end = 0x1C4550 },
> > > +     { .start = 0x1C8030, .end = 0x1C8030 },
> > > +     { .start = 0x1C8550, .end = 0x1C8550 },
> > > +     { .start = 0x1D0030, .end = 0x1D0030 },
> > > +     { .start = 0x1D0550, .end = 0x1D0550 },
> > > +     { .start = 0x1D4030, .end = 0x1D4030 },
> > > +     { .start = 0x1D4550, .end = 0x1D4550 },
> > > +     { .start = 0x1D8030, .end = 0x1D8030 },
> > > +     { .start = 0x1D8550, .end = 0x1D8550 },
> > >       /* TODO: Other registers are not yet used */
> > >  };
> > > 
> > > -static const i915_reg_t gen12_shadowed_regs[] = {
> > > -     RING_TAIL(RENDER_RING_BASE),                    /* 0x2000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(RENDER_RING_BASE),        /* 0x2550
> > > */
> > > -     GEN6_RPNSWREQ,                                  /* 0xA008
> > > */
> > > -     GEN6_RC_VIDEO_FREQ,                             /* 0xA00C
> > > */
> > > -     RING_TAIL(BLT_RING_BASE),                       /* 0x22000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(BLT_RING_BASE),           /* 0x22550
> > > */
> > > -     RING_TAIL(GEN11_BSD_RING_BASE),                 /* 0x1C0000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE),     /* 0x1C0550
> > > */
> > > -     RING_TAIL(GEN11_BSD2_RING_BASE),                /* 0x1C4000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE),    /* 0x1C4550
> > > */
> > > -     RING_TAIL(GEN11_VEBOX_RING_BASE),               /* 0x1C8000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE),   /* 0x1C8550
> > > */
> > > -     RING_TAIL(GEN11_BSD3_RING_BASE),                /* 0x1D0000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE),    /* 0x1D0550
> > > */
> > > -     RING_TAIL(GEN11_BSD4_RING_BASE),                /* 0x1D4000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE),    /* 0x1D4550
> > > */
> > > -     RING_TAIL(GEN11_VEBOX2_RING_BASE),              /* 0x1D8000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE),  /* 0x1D8550
> > > */
> > > +static const struct i915_range gen12_shadowed_regs[] = {
> > > +     { .start =   0x2030, .end =   0x2030 },
> > > +     { .start =   0x2550, .end =   0x2550 },
> > > +     { .start =   0xA008, .end =   0xA00C },
> > > +     { .start =  0x22030, .end =  0x22030 },
> > > +     { .start =  0x22550, .end =  0x22550 },
> > > +     { .start = 0x1C0030, .end = 0x1C0030 },
> > > +     { .start = 0x1C0550, .end = 0x1C0550 },
> > > +     { .start = 0x1C4030, .end = 0x1C4030 },
> > > +     { .start = 0x1C4550, .end = 0x1C4550 },
> > > +     { .start = 0x1C8030, .end = 0x1C8030 },
> > > +     { .start = 0x1C8550, .end = 0x1C8550 },
> > > +     { .start = 0x1D0030, .end = 0x1D0030 },
> > > +     { .start = 0x1D0550, .end = 0x1D0550 },
> > > +     { .start = 0x1D4030, .end = 0x1D4030 },
> > > +     { .start = 0x1D4550, .end = 0x1D4550 },
> > > +     { .start = 0x1D8030, .end = 0x1D8030 },
> > > +     { .start = 0x1D8550, .end = 0x1D8550 },
> > >       /* TODO: Other registers are not yet used */
> > >  };
> > > 
> > > -static const i915_reg_t xehp_shadowed_regs[] = {
> > > -     RING_TAIL(RENDER_RING_BASE),                    /* 0x2000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(RENDER_RING_BASE),        /* 0x2550
> > > */
> > > -     GEN6_RPNSWREQ,                                  /* 0xA008
> > > */
> > > -     GEN6_RC_VIDEO_FREQ,                             /* 0xA00C
> > > */
> > > -     RING_TAIL(BLT_RING_BASE),                       /* 0x22000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(BLT_RING_BASE),           /* 0x22550
> > > */
> > > -     RING_TAIL(GEN11_BSD_RING_BASE),                 /* 0x1C0000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE),     /* 0x1C0550
> > > */
> > > -     RING_TAIL(GEN11_BSD2_RING_BASE),                /* 0x1C4000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE),    /* 0x1C4550
> > > */
> > > -     RING_TAIL(GEN11_VEBOX_RING_BASE),               /* 0x1C8000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE),   /* 0x1C8550
> > > */
> > > -     RING_TAIL(GEN11_BSD3_RING_BASE),                /* 0x1D0000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE),    /* 0x1D0550
> > > */
> > > -     RING_TAIL(GEN11_BSD4_RING_BASE),                /* 0x1D4000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE),    /* 0x1D4550
> > > */
> > > -     RING_TAIL(GEN11_VEBOX2_RING_BASE),              /* 0x1D8000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE),  /* 0x1D8550
> > > */
> > > -     RING_TAIL(XEHP_BSD5_RING_BASE),                 /* 0x1E0000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(XEHP_BSD5_RING_BASE),     /* 0x1E0550
> > > */
> > > -     RING_TAIL(XEHP_BSD6_RING_BASE),                 /* 0x1E4000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(XEHP_BSD6_RING_BASE),     /* 0x1E4550
> > > */
> > > -     RING_TAIL(XEHP_VEBOX3_RING_BASE),               /* 0x1E8000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(XEHP_VEBOX3_RING_BASE),   /* 0x1E8550
> > > */
> > > -     RING_TAIL(XEHP_BSD7_RING_BASE),                 /* 0x1F0000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(XEHP_BSD7_RING_BASE),     /* 0x1F0550
> > > */
> > > -     RING_TAIL(XEHP_BSD8_RING_BASE),                 /* 0x1F4000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(XEHP_BSD8_RING_BASE),     /* 0x1F4550
> > > */
> > > -     RING_TAIL(XEHP_VEBOX4_RING_BASE),               /* 0x1F8000
> > > (base) */
> > > -     RING_EXECLIST_CONTROL(XEHP_VEBOX4_RING_BASE),   /* 0x1F8550
> > > */
> > > +static const struct i915_range xehp_shadowed_regs[] = {
> > > +     { .start =   0x2000, .end =   0x2030 },
> > > +     { .start =   0x2550, .end =   0x2550 },
> > > +     { .start =   0xA008, .end =   0xA00C },
> > > +     { .start =  0x22030, .end =  0x22030 },
> > > +     { .start =  0x22550, .end =  0x22550 },
> > > +     { .start = 0x1C0030, .end = 0x1C0030 },
> > > +     { .start = 0x1C0550, .end = 0x1C0550 },
> > > +     { .start = 0x1C4030, .end = 0x1C4030 },
> > > +     { .start = 0x1C4550, .end = 0x1C4550 },
> > > +     { .start = 0x1C8030, .end = 0x1C8030 },
> > > +     { .start = 0x1C8550, .end = 0x1C8550 },
> > > +     { .start = 0x1D0030, .end = 0x1D0030 },
> > > +     { .start = 0x1D0550, .end = 0x1D0550 },
> > > +     { .start = 0x1D4030, .end = 0x1D4030 },
> > > +     { .start = 0x1D4550, .end = 0x1D4550 },
> > > +     { .start = 0x1D8030, .end = 0x1D8030 },
> > > +     { .start = 0x1D8550, .end = 0x1D8550 },
> > > +     { .start = 0x1E0030, .end = 0x1E0030 },
> > > +     { .start = 0x1E0550, .end = 0x1E0550 },
> > > +     { .start = 0x1E4030, .end = 0x1E4030 },
> > > +     { .start = 0x1E4550, .end = 0x1E4550 },
> > > +     { .start = 0x1E8030, .end = 0x1E8030 },
> > > +     { .start = 0x1E8550, .end = 0x1E8550 },
> > > +     { .start = 0x1F0030, .end = 0x1F0030 },
> > > +     { .start = 0x1F0550, .end = 0x1F0550 },
> > > +     { .start = 0x1F4030, .end = 0x1F4030 },
> > > +     { .start = 0x1F4550, .end = 0x1F4550 },
> > > +     { .start = 0x1F8030, .end = 0x1F8030 },
> > > +     { .start = 0x1F8550, .end = 0x1F8550 },
> > >       /* TODO: Other registers are not yet used */
> > >  };
> > > 
> > > -static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
> > > +static int mmio_range_cmp(u32 key, const struct i915_range
> > > *range)
> > >  {
> > > -     u32 offset = i915_mmio_reg_offset(*reg);
> > > -
> > > -     if (key < offset)
> > > +     if (key < range->start)
> > >               return -1;
> > > -     else if (key > offset)
> > > +     else if (key > range->end)
> > >               return 1;
> > >       else
> > >               return 0;
> > > @@ -1049,9 +1043,9 @@ static int mmio_reg_cmp(u32 key, const
> > > i915_reg_t *reg)
> > >  #define __is_X_shadowed(x) \
> > >  static bool is_##x##_shadowed(u32 offset) \
> > >  { \
> > > -     const i915_reg_t *regs = x##_shadowed_regs; \
> > > +     const struct i915_range *regs = x##_shadowed_regs; \
> > >       return BSEARCH(offset, regs, ARRAY_SIZE(x##_shadowed_regs),
> > > \
> > > -                    mmio_reg_cmp); \
> > > +                    mmio_range_cmp); \
> > >  }
> > > 
> > >  __is_X_shadowed(gen8)
> > > diff --git a/drivers/gpu/drm/i915/intel_uncore.h
> > > b/drivers/gpu/drm/i915/intel_uncore.h
> > > index 3c0b0a8b5250..531665b08039 100644
> > > --- a/drivers/gpu/drm/i915/intel_uncore.h
> > > +++ b/drivers/gpu/drm/i915/intel_uncore.h
> > > @@ -119,6 +119,12 @@ struct intel_forcewake_range {
> > >       enum forcewake_domains domains;
> > >  };
> > > 
> > > +/* Other register ranges (e.g., shadow tables, MCR tables, etc.)
> > > */
> > > +struct i915_range {
> > > +     u32 start;
> > > +     u32 end;
> > > +};
> > > +
> > >  struct intel_uncore {
> > >       void __iomem *regs;
> > > 
> > > diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> > > b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> > > index 720b60853f8b..d6a9c11afa23 100644
> > > --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> > > +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> > > @@ -62,30 +62,40 @@ static int intel_fw_table_check(const struct
> > > intel_forcewake_range *ranges,
> > >  static int intel_shadow_table_check(void)
> > >  {
> > >       struct {
> > > -             const i915_reg_t *regs;
> > > +             const struct i915_range *regs;
> > >               unsigned int size;
> > > -     } reg_lists[] = {
> > > +     } range_lists[] = {
> > >               { gen8_shadowed_regs,
> > > ARRAY_SIZE(gen8_shadowed_regs) },
> > >               { gen11_shadowed_regs,
> > > ARRAY_SIZE(gen11_shadowed_regs)
> > > },
> > >               { gen12_shadowed_regs,
> > > ARRAY_SIZE(gen12_shadowed_regs)
> > > },
> > >               { xehp_shadowed_regs,
> > > ARRAY_SIZE(xehp_shadowed_regs) },
> > >       };
> > > -     const i915_reg_t *reg;
> > > +     const struct i915_range *range;
> > >       unsigned int i, j;
> > >       s32 prev;
> > > 
> > > -     for (j = 0; j < ARRAY_SIZE(reg_lists); ++j) {
> > > -             reg = reg_lists[j].regs;
> > > -             for (i = 0, prev = -1; i < reg_lists[j].size; i++,
> > > reg++) {
> > > -                     u32 offset = i915_mmio_reg_offset(*reg);
> > > +     for (j = 0; j < ARRAY_SIZE(range_lists); ++j) {
> > > +             range = range_lists[j].regs;
> > > +             for (i = 0, prev = -1; i < range_lists[j].size;
> > > i++,
> > > range++) {
> > > +                     if (range->end < range->start) {
> > > +                             pr_err("%s: range[%d]:(%06x-%06x)
> > > has
> > > end before start\n",
> > > +                                    __func__, i, range->start,
> > > range->end);
> > > +                             return -EINVAL;
> > > +                     }
> > > +
> > > +                     if (prev >= (s32)range->start) {
> > > +                             pr_err("%s: range[%d]:(%06x-%06x)
> > > is
> > > before end of previous (%06x)\n",
> > > +                                    __func__, i, range->start,
> > > range->end, prev);
> > > +                             return -EINVAL;
> > > +                     }
> > > 
> > > -                     if (prev >= (s32)offset) {
> > > -                             pr_err("%s: entry[%d]:(%x) is
> > > before
> > > previous (%x)\n",
> > > -                                    __func__, i, offset, prev);
> > > +                     if (range->start % 4) {
> > > +                             pr_err("%s: range[%d]:(%06x-%06x)
> > > has
> > > non-dword-aligned start\n",
> > > +                                    __func__, i, range->start,
> > > range->end);
> > >                               return -EINVAL;
> > >                       }
> > > 
> > > -                     prev = offset;
> > > +                     prev = range->end;
> > >               }
> > >       }
> > > 

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [Intel-gfx] [PATCH 4/6] drm/i915/gen11: Update shadowed register table
  2021-07-29  5:41 ` [Intel-gfx] [PATCH 4/6] drm/i915/gen11: Update shadowed register table Matt Roper
@ 2021-08-10 22:03   ` Yokoyama, Caz
  0 siblings, 0 replies; 22+ messages in thread
From: Yokoyama, Caz @ 2021-08-10 22:03 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx

Reviewed-by: Caz Yokoyama <caz.yokoyama@intel.com>
-caz

On Wed, 2021-07-28 at 22:41 -0700, Matt Roper wrote:
> The bspec lists many shadowed registers (i.e., registers for which we
> don't need to grab forcewake when writing) that we weren't tracking
> in
> the driver.  Although we may not actually use all of these registers
> right now, it's best to just match the bspec list exactly.
> 
> Note that the bspec also lists registers that are shadowed for
> various
> HW-internal accesses; we can ignore those and just list the ones that
> are shadowed for accesses from the IA/CPU.
> 
> Bspec: 18333
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 22 ++++++++++++++--------
>  1 file changed, 14 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 2cfbc16f7dee..31e0456dce5a 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -960,20 +960,26 @@ static const struct i915_range
> gen11_shadowed_regs[] = {
>  	{ .start =   0x2550, .end =   0x2550 },
>  	{ .start =   0xA008, .end =   0xA00C },
>  	{ .start =  0x22030, .end =  0x22030 },
> -	{ .start =  0x22550, .end =  0x22550 },
> +	{ .start =  0x22230, .end =  0x22230 },
> +	{ .start =  0x22510, .end =  0x22550 },
>  	{ .start = 0x1C0030, .end = 0x1C0030 },
> -	{ .start = 0x1C0550, .end = 0x1C0550 },
> +	{ .start = 0x1C0230, .end = 0x1C0230 },
> +	{ .start = 0x1C0510, .end = 0x1C0550 },
>  	{ .start = 0x1C4030, .end = 0x1C4030 },
> -	{ .start = 0x1C4550, .end = 0x1C4550 },
> +	{ .start = 0x1C4230, .end = 0x1C4230 },
> +	{ .start = 0x1C4510, .end = 0x1C4550 },
>  	{ .start = 0x1C8030, .end = 0x1C8030 },
> -	{ .start = 0x1C8550, .end = 0x1C8550 },
> +	{ .start = 0x1C8230, .end = 0x1C8230 },
> +	{ .start = 0x1C8510, .end = 0x1C8550 },
>  	{ .start = 0x1D0030, .end = 0x1D0030 },
> -	{ .start = 0x1D0550, .end = 0x1D0550 },
> +	{ .start = 0x1D0230, .end = 0x1D0230 },
> +	{ .start = 0x1D0510, .end = 0x1D0550 },
>  	{ .start = 0x1D4030, .end = 0x1D4030 },
> -	{ .start = 0x1D4550, .end = 0x1D4550 },
> +	{ .start = 0x1D4230, .end = 0x1D4230 },
> +	{ .start = 0x1D4510, .end = 0x1D4550 },
>  	{ .start = 0x1D8030, .end = 0x1D8030 },
> -	{ .start = 0x1D8550, .end = 0x1D8550 },
> -	/* TODO: Other registers are not yet used */
> +	{ .start = 0x1D8230, .end = 0x1D8230 },
> +	{ .start = 0x1D8510, .end = 0x1D8550 },
>  };
>  
>  static const struct i915_range gen12_shadowed_regs[] = {

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [Intel-gfx] [PATCH 5/6] drm/i915/gen12: Update shadowed register table
  2021-07-29  5:41 ` [Intel-gfx] [PATCH 5/6] drm/i915/gen12: " Matt Roper
@ 2021-08-10 22:04   ` Yokoyama, Caz
  0 siblings, 0 replies; 22+ messages in thread
From: Yokoyama, Caz @ 2021-08-10 22:04 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx

Reviewed-by: Caz Yokoyama <caz.yokoyama@intel.com>
-caz

On Wed, 2021-07-28 at 22:41 -0700, Matt Roper wrote:
> The bspec lists many shadowed registers (i.e., registers for which we
> don't need to grab forcewake when writing) that we weren't tracking
> in
> the driver.  Although we may not actually use all of these registers
> right now, it's best to just match the bspec list exactly.
> 
> Note that the bspec also lists registers that are shadowed for
> various
> HW-internal accesses; we can ignore those and just list the ones that
> are shadowed for accesses from the IA/CPU.
> 
> Bspec: 52077
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 23 ++++++++++++++---------
>  1 file changed, 14 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 31e0456dce5a..42acf106a6df 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -984,23 +984,28 @@ static const struct i915_range
> gen11_shadowed_regs[] = {
>  
>  static const struct i915_range gen12_shadowed_regs[] = {
>  	{ .start =   0x2030, .end =   0x2030 },
> -	{ .start =   0x2550, .end =   0x2550 },
> +	{ .start =   0x2510, .end =   0x2550 },
>  	{ .start =   0xA008, .end =   0xA00C },
> +	{ .start =   0xA188, .end =   0xA188 },
> +	{ .start =   0xA278, .end =   0xA278 },
> +	{ .start =   0xA540, .end =   0xA56C },
> +	{ .start =   0xC4C8, .end =   0xC4C8 },
> +	{ .start =   0xC4D4, .end =   0xC4D4 },
> +	{ .start =   0xC600, .end =   0xC600 },
>  	{ .start =  0x22030, .end =  0x22030 },
> -	{ .start =  0x22550, .end =  0x22550 },
> +	{ .start =  0x22510, .end =  0x22550 },
>  	{ .start = 0x1C0030, .end = 0x1C0030 },
> -	{ .start = 0x1C0550, .end = 0x1C0550 },
> +	{ .start = 0x1C0510, .end = 0x1C0550 },
>  	{ .start = 0x1C4030, .end = 0x1C4030 },
> -	{ .start = 0x1C4550, .end = 0x1C4550 },
> +	{ .start = 0x1C4510, .end = 0x1C4550 },
>  	{ .start = 0x1C8030, .end = 0x1C8030 },
> -	{ .start = 0x1C8550, .end = 0x1C8550 },
> +	{ .start = 0x1C8510, .end = 0x1C8550 },
>  	{ .start = 0x1D0030, .end = 0x1D0030 },
> -	{ .start = 0x1D0550, .end = 0x1D0550 },
> +	{ .start = 0x1D0510, .end = 0x1D0550 },
>  	{ .start = 0x1D4030, .end = 0x1D4030 },
> -	{ .start = 0x1D4550, .end = 0x1D4550 },
> +	{ .start = 0x1D4510, .end = 0x1D4550 },
>  	{ .start = 0x1D8030, .end = 0x1D8030 },
> -	{ .start = 0x1D8550, .end = 0x1D8550 },
> -	/* TODO: Other registers are not yet used */
> +	{ .start = 0x1D8510, .end = 0x1D8550 },
>  };
>  
>  static const struct i915_range xehp_shadowed_regs[] = {

^ permalink raw reply	[flat|nested] 22+ messages in thread

end of thread, other threads:[~2021-08-10 22:04 UTC | newest]

Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-29  5:41 [Intel-gfx] [PATCH 0/6] Forcewake and shadowed register updates Matt Roper
2021-07-29  5:41 ` [Intel-gfx] [PATCH 1/6] drm/i915: correct name of GT forcewake domain in error messages Matt Roper
2021-07-29 14:13   ` Yokoyama, Caz
2021-07-29  5:41 ` [Intel-gfx] [PATCH 2/6] drm/i915: Re-use gen11 forcewake read functions on gen12 Matt Roper
2021-07-29 21:02   ` Yokoyama, Caz
2021-07-29  5:41 ` [Intel-gfx] [PATCH 3/6] drm/i915: Make shadow tables range-based Matt Roper
2021-07-29 15:21   ` [Intel-gfx] [PATCH v2 " Matt Roper
2021-07-29 21:55     ` Yokoyama, Caz
2021-07-29 21:59       ` Matt Roper
2021-08-10 22:02         ` Yokoyama, Caz
2021-07-29  5:41 ` [Intel-gfx] [PATCH 4/6] drm/i915/gen11: Update shadowed register table Matt Roper
2021-08-10 22:03   ` Yokoyama, Caz
2021-07-29  5:41 ` [Intel-gfx] [PATCH 5/6] drm/i915/gen12: " Matt Roper
2021-08-10 22:04   ` Yokoyama, Caz
2021-07-29  5:41 ` [Intel-gfx] [PATCH 6/6] drm/i915/xehp: Xe_HP shadowed registers are a strict superset of gen12 Matt Roper
2021-07-29 23:36   ` Yokoyama, Caz
2021-07-29  6:09 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Forcewake and shadowed register updates Patchwork
2021-07-29  6:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-29 13:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-07-29 20:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Forcewake and shadowed register updates (rev2) Patchwork
2021-07-29 20:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-30  8:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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