* [Intel-gfx] [RFC v3 0/2] lpsp with hdmi/dp outputs
@ 2021-06-01 10:02 Anshuman Gupta
2021-06-01 10:02 ` [Intel-gfx] [RFC v3 1/2] drm/i915/dg1: Adjust the AUDIO power domain Anshuman Gupta
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Anshuman Gupta @ 2021-06-01 10:02 UTC (permalink / raw)
To: intel-gfx
v2 link: https://patchwork.freedesktop.org/series/77866/
Anshuman Gupta (2):
drm/i915/dg1: Adjust the AUDIO power domain
drm/i915/display: Use AUDIO_VERBS for crtc power domain mask
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
.../drm/i915/display/intel_display_power.c | 382 +++++++++++++++++-
.../drm/i915/display/intel_display_power.h | 1 +
4 files changed, 384 insertions(+), 3 deletions(-)
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] [RFC v3 1/2] drm/i915/dg1: Adjust the AUDIO power domain
2021-06-01 10:02 [Intel-gfx] [RFC v3 0/2] lpsp with hdmi/dp outputs Anshuman Gupta
@ 2021-06-01 10:02 ` Anshuman Gupta
2021-06-07 15:21 ` Kai Vehmanen
2021-06-28 17:42 ` Imre Deak
2021-06-01 10:02 ` [Intel-gfx] [RFC v3 2/2] drm/i915/display: Use AUDIO_VERBS for crtc power domain mask Anshuman Gupta
` (3 subsequent siblings)
4 siblings, 2 replies; 9+ messages in thread
From: Anshuman Gupta @ 2021-06-01 10:02 UTC (permalink / raw)
To: intel-gfx
DG1 and XE_PLD platforms has Audio MMIO/VERBS lies in PG0 power
well. Adjusting the power domain accordingly to
POWER_DOMAIN_AUDIO_VERBS for audio detection and POWER_DOMAIN_AUDIO
for audio playback.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_power.c | 382 +++++++++++++++++-
.../drm/i915/display/intel_display_power.h | 1 +
2 files changed, 382 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 2f7d1664c473..da5894138e8b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -106,6 +106,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "PORT_OTHER";
case POWER_DOMAIN_VGA:
return "VGA";
+ case POWER_DOMAIN_AUDIO_VERBS:
+ return "AUDIO_VERBS";
case POWER_DOMAIN_AUDIO:
return "AUDIO";
case POWER_DOMAIN_AUX_A:
@@ -2499,6 +2501,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
BIT_ULL(POWER_DOMAIN_AUDIO) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
@@ -2549,6 +2552,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
BIT_ULL(POWER_DOMAIN_AUDIO) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
@@ -2582,6 +2586,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
BIT_ULL(POWER_DOMAIN_AUDIO) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -2598,6 +2603,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
BIT_ULL(POWER_DOMAIN_AUDIO) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -2616,6 +2622,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
BIT_ULL(POWER_DOMAIN_AUDIO) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -2651,6 +2658,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
BIT_ULL(POWER_DOMAIN_AUDIO) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -2684,6 +2692,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
BIT_ULL(POWER_DOMAIN_AUDIO) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -2739,6 +2748,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_AUX_D) | \
BIT_ULL(POWER_DOMAIN_AUX_F) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
BIT_ULL(POWER_DOMAIN_AUDIO) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -2821,6 +2831,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
BIT_ULL(POWER_DOMAIN_AUDIO) | \
BIT_ULL(POWER_DOMAIN_INIT))
/*
@@ -2913,6 +2924,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
BIT_ULL(POWER_DOMAIN_AUDIO) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -2983,6 +2995,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
RKL_PW_4_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
BIT_ULL(POWER_DOMAIN_AUDIO) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
@@ -3020,6 +3033,42 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
+/*
+ * DG1 Audio MMIO/VERBS lies in PG0 power well.
+ */
+
+#define DG1_PW_2_POWER_DOMAINS ( \
+ DG1_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_PW_3_POWER_DOMAINS ( \
+ TGL_PW_4_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC5) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC6) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
/*
* XE_LPD Power Domains
*
@@ -4497,6 +4546,335 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
};
+static const struct i915_power_well_desc dg1_power_wells[] = {
+ {
+ .name = "always-on",
+ .always_on = true,
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ },
+ {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .always_on = true,
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "DC off",
+ .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ },
+ {
+ .name = "power well 2",
+ .domains = DG1_PW_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "power well 3",
+ .domains = DG1_PW_3_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = ICL_DISP_PW_3,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "DDI A IO",
+ .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+ }
+ },
+ {
+ .name = "DDI B IO",
+ .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+ }
+ },
+ {
+ .name = "DDI C IO",
+ .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
+ }
+ },
+ {
+ .name = "DDI IO TC1",
+ .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
+ },
+ },
+ {
+ .name = "DDI IO TC2",
+ .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
+ },
+ },
+ {
+ .name = "DDI IO TC3",
+ .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
+ },
+ },
+ {
+ .name = "DDI IO TC4",
+ .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
+ },
+ },
+ {
+ .name = "DDI IO TC5",
+ .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
+ },
+ },
+ {
+ .name = "DDI IO TC6",
+ .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
+ },
+ },
+ {
+ .name = "AUX A",
+ .domains = TGL_AUX_A_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+ },
+ },
+ {
+ .name = "AUX B",
+ .domains = TGL_AUX_B_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+ },
+ },
+ {
+ .name = "AUX C",
+ .domains = TGL_AUX_C_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
+ },
+ },
+ {
+ .name = "AUX USBC1",
+ .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+ .hsw.is_tc_tbt = false,
+ },
+ },
+ {
+ .name = "AUX USBC2",
+ .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
+ .hsw.is_tc_tbt = false,
+ },
+ },
+ {
+ .name = "AUX USBC3",
+ .domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
+ .hsw.is_tc_tbt = false,
+ },
+ },
+ {
+ .name = "AUX USBC4",
+ .domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
+ .hsw.is_tc_tbt = false,
+ },
+ },
+ {
+ .name = "AUX USBC5",
+ .domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
+ .hsw.is_tc_tbt = false,
+ },
+ },
+ {
+ .name = "AUX USBC6",
+ .domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
+ .hsw.is_tc_tbt = false,
+ },
+ },
+ {
+ .name = "AUX TBT1",
+ .domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
+ .hsw.is_tc_tbt = true,
+ },
+ },
+ {
+ .name = "AUX TBT2",
+ .domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
+ .hsw.is_tc_tbt = true,
+ },
+ },
+ {
+ .name = "AUX TBT3",
+ .domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
+ .hsw.is_tc_tbt = true,
+ },
+ },
+ {
+ .name = "AUX TBT4",
+ .domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
+ .hsw.is_tc_tbt = true,
+ },
+ },
+ {
+ .name = "AUX TBT5",
+ .domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
+ .hsw.is_tc_tbt = true,
+ },
+ },
+ {
+ .name = "AUX TBT6",
+ .domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
+ .hsw.is_tc_tbt = true,
+ },
+ },
+ {
+ .name = "power well 4",
+ .domains = TGL_PW_4_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_C),
+ }
+ },
+ {
+ .name = "power well 5",
+ .domains = TGL_PW_5_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_D),
+ },
+ },
+};
+
static const struct i915_power_well_desc rkl_power_wells[] = {
{
.name = "always-on",
@@ -5110,9 +5488,11 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
err = 0;
} else if (DISPLAY_VER(dev_priv) >= 13) {
err = set_power_wells(power_domains, xelpd_power_wells);
- } else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
+ } else if (IS_ALDERLAKE_S(dev_priv)) {
err = set_power_wells_mask(power_domains, tgl_power_wells,
BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
+ } else if (IS_DG1(dev_priv)) {
+ err = set_power_wells(power_domains, dg1_power_wells);
} else if (IS_ROCKETLAKE(dev_priv)) {
err = set_power_wells(power_domains, rkl_power_wells);
} else if (DISPLAY_VER(dev_priv) == 12) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 4f0917df4375..d9c824264ac9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -76,6 +76,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_CRT,
POWER_DOMAIN_PORT_OTHER,
POWER_DOMAIN_VGA,
+ POWER_DOMAIN_AUDIO_VERBS,
POWER_DOMAIN_AUDIO,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_AUX_B,
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] [RFC v3 2/2] drm/i915/display: Use AUDIO_VERBS for crtc power domain mask
2021-06-01 10:02 [Intel-gfx] [RFC v3 0/2] lpsp with hdmi/dp outputs Anshuman Gupta
2021-06-01 10:02 ` [Intel-gfx] [RFC v3 1/2] drm/i915/dg1: Adjust the AUDIO power domain Anshuman Gupta
@ 2021-06-01 10:02 ` Anshuman Gupta
2021-06-01 13:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for lpsp with hdmi/dp outputs Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Anshuman Gupta @ 2021-06-01 10:02 UTC (permalink / raw)
To: intel-gfx
Use POWER_DOMAIN_AUDIO_VERBS power domain instead of
POWER_DOMAIN_AUDIO in crtc power domain mask.
It will save the power in use cases when DP/HDMI connectors
configured with PIPE_A without any audio playback.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3d8918674153..55c392114272 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3494,7 +3494,7 @@ static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
if (cpu_transcoder == TRANSCODER_EDP)
return false;
- if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
+ if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_VERBS))
return false;
return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0bb2e582c87f..c24465739af5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3829,7 +3829,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
}
if (HAS_DDI(dev_priv) && crtc_state->has_audio)
- mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
+ mask |= BIT_ULL(POWER_DOMAIN_AUDIO_VERBS);
if (crtc_state->shared_dpll)
mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for lpsp with hdmi/dp outputs
2021-06-01 10:02 [Intel-gfx] [RFC v3 0/2] lpsp with hdmi/dp outputs Anshuman Gupta
2021-06-01 10:02 ` [Intel-gfx] [RFC v3 1/2] drm/i915/dg1: Adjust the AUDIO power domain Anshuman Gupta
2021-06-01 10:02 ` [Intel-gfx] [RFC v3 2/2] drm/i915/display: Use AUDIO_VERBS for crtc power domain mask Anshuman Gupta
@ 2021-06-01 13:54 ` Patchwork
2021-06-01 14:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-06-01 18:14 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2021-06-01 13:54 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: lpsp with hdmi/dp outputs
URL : https://patchwork.freedesktop.org/series/90827/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1207:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for lpsp with hdmi/dp outputs
2021-06-01 10:02 [Intel-gfx] [RFC v3 0/2] lpsp with hdmi/dp outputs Anshuman Gupta
` (2 preceding siblings ...)
2021-06-01 13:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for lpsp with hdmi/dp outputs Patchwork
@ 2021-06-01 14:23 ` Patchwork
2021-06-01 18:14 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2021-06-01 14:23 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 6660 bytes --]
== Series Details ==
Series: lpsp with hdmi/dp outputs
URL : https://patchwork.freedesktop.org/series/90827/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10154 -> Patchwork_20250
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/index.html
Known issues
------------
Here are the changes found in Patchwork_20250 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][3] -> [FAIL][4] ([i915#49])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][5] ([i915#3303]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][7] ([i915#1372]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
#### Warnings ####
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [INCOMPLETE][9] ([i915#2782] / [i915#2940] / [i915#3462]) -> [DMESG-FAIL][10] ([i915#3462])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-bsw-nick/igt@i915_selftest@live@execlists.html
- fi-icl-u2: [INCOMPLETE][11] ([i915#2782] / [i915#3462]) -> [DMESG-FAIL][12] ([i915#3462])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-icl-u2/igt@i915_selftest@live@execlists.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-icl-u2/igt@i915_selftest@live@execlists.html
- fi-tgl-u2: [INCOMPLETE][13] ([i915#3462]) -> [DMESG-FAIL][14] ([i915#3462])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-tgl-u2/igt@i915_selftest@live@execlists.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-tgl-u2/igt@i915_selftest@live@execlists.html
* igt@runner@aborted:
- fi-icl-u2: [FAIL][15] ([i915#2782] / [i915#3363]) -> [FAIL][16] ([i915#2426] / [i915#2782] / [i915#3363])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-icl-u2/igt@runner@aborted.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-icl-u2/igt@runner@aborted.html
- fi-glk-dsi: [FAIL][17] ([i915#2426] / [i915#3363] / [k.org#202321]) -> [FAIL][18] ([i915#3363] / [k.org#202321])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-glk-dsi/igt@runner@aborted.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-glk-dsi/igt@runner@aborted.html
- fi-kbl-soraka: [FAIL][19] ([i915#1436] / [i915#3363]) -> [FAIL][20] ([i915#1436] / [i915#2426] / [i915#3363])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-soraka/igt@runner@aborted.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-kbl-soraka/igt@runner@aborted.html
- fi-cml-u2: [FAIL][21] ([i915#3363] / [i915#3462]) -> [FAIL][22] ([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-cml-u2/igt@runner@aborted.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-cml-u2/igt@runner@aborted.html
- fi-cfl-guc: [FAIL][23] ([i915#2426] / [i915#3363]) -> [FAIL][24] ([i915#3363])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-cfl-guc/igt@runner@aborted.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-cfl-guc/igt@runner@aborted.html
- fi-skl-6700k2: [FAIL][25] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][26] ([i915#1436] / [i915#3363])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-skl-6700k2/igt@runner@aborted.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-skl-6700k2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (47 -> 42)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10154 -> Patchwork_20250
CI-20190529: 20190529
CI_DRM_10154: 810010ed3d29e0500d452a90010a88a0879f2b45 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6097: f823d8ec14b34a6dd2c0804c684b07b0a50f7bb7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20250: cad36fa4bba83434c2fce1a3ec06f89fbdefe50a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cad36fa4bba8 drm/i915/display: Use AUDIO_VERBS for crtc power domain mask
831b018f0b6a drm/i915/dg1: Adjust the AUDIO power domain
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/index.html
[-- Attachment #1.2: Type: text/html, Size: 9466 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for lpsp with hdmi/dp outputs
2021-06-01 10:02 [Intel-gfx] [RFC v3 0/2] lpsp with hdmi/dp outputs Anshuman Gupta
` (3 preceding siblings ...)
2021-06-01 14:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-06-01 18:14 ` Patchwork
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2021-06-01 18:14 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30248 bytes --]
== Series Details ==
Series: lpsp with hdmi/dp outputs
URL : https://patchwork.freedesktop.org/series/90827/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10154_full -> Patchwork_20250_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_20250_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-clear:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#1888] / [i915#3160])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk9/igt@gem_create@create-clear.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-glk8/igt@gem_create@create-clear.html
* igt@gem_ctx_persistence@idempotent:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +4 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-snb7/igt@gem_ctx_persistence@idempotent.html
* igt@gem_ctx_ringsize@active@bcs0:
- shard-skl: [PASS][4] -> [INCOMPLETE][5] ([i915#3316])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl8/igt@gem_ctx_ringsize@active@bcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl8/igt@gem_ctx_ringsize@active@bcs0.html
* igt@gem_eio@unwedge-stress:
- shard-snb: NOTRUN -> [FAIL][6] ([i915#3354])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-snb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][9] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) +2 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-glk5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
- shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-tglb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-tglb6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2849])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_reloc@basic-wide-active@rcs0:
- shard-snb: NOTRUN -> [FAIL][16] ([i915#2389]) +2 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-snb5/igt@gem_exec_reloc@basic-wide-active@rcs0.html
* igt@gem_exec_whisper@basic-fds-forked:
- shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#118] / [i915#95])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk9/igt@gem_exec_whisper@basic-fds-forked.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-glk6/igt@gem_exec_whisper@basic-fds-forked.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2190])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-apl2/igt@gem_huc_copy@huc-copy.html
* igt@gem_mmap_gtt@big-copy:
- shard-skl: [PASS][20] -> [FAIL][21] ([i915#307])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl6/igt@gem_mmap_gtt@big-copy.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl6/igt@gem_mmap_gtt@big-copy.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy:
- shard-glk: [PASS][22] -> [INCOMPLETE][23] ([i915#2055] / [i915#3468])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk5/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-glk2/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-odd:
- shard-iclb: NOTRUN -> [INCOMPLETE][24] ([i915#2910] / [i915#3468])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb8/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
- shard-kbl: [PASS][25] -> [INCOMPLETE][26] ([i915#3468]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl4/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl4/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
* igt@gem_mmap_gtt@fault-concurrent:
- shard-skl: NOTRUN -> [INCOMPLETE][27] ([i915#3468])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl7/igt@gem_mmap_gtt@fault-concurrent.html
* igt@gem_mmap_gtt@fault-concurrent-y:
- shard-snb: NOTRUN -> [INCOMPLETE][28] ([i915#3468]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-snb6/igt@gem_mmap_gtt@fault-concurrent-y.html
- shard-apl: NOTRUN -> [INCOMPLETE][29] ([i915#3468])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-apl1/igt@gem_mmap_gtt@fault-concurrent-y.html
* igt@gem_pread@exhaustion:
- shard-snb: NOTRUN -> [WARN][30] ([i915#2658])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-snb7/igt@gem_pread@exhaustion.html
- shard-kbl: NOTRUN -> [WARN][31] ([i915#2658])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl1/igt@gem_pread@exhaustion.html
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][32] ([i915#3318])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-apl1/igt@gem_userptr_blits@vma-merge.html
- shard-skl: NOTRUN -> [FAIL][33] ([i915#3318])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl8/igt@gem_userptr_blits@vma-merge.html
* igt@i915_hangman@engine-error@vecs0:
- shard-kbl: NOTRUN -> [SKIP][34] ([fdo#109271]) +110 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl7/igt@i915_hangman@engine-error@vecs0.html
* igt@i915_selftest@live@execlists:
- shard-apl: NOTRUN -> [DMESG-FAIL][35] ([i915#3462])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-apl1/igt@i915_selftest@live@execlists.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-kbl: NOTRUN -> [DMESG-WARN][36] ([i915#180])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl7/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_ccs@pipe-d-bad-pixel-format:
- shard-iclb: NOTRUN -> [SKIP][37] ([fdo#109278])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb8/igt@kms_ccs@pipe-d-bad-pixel-format.html
* igt@kms_chamelium@hdmi-edid-change-during-suspend:
- shard-iclb: NOTRUN -> [SKIP][38] ([fdo#109284] / [fdo#111827])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb8/igt@kms_chamelium@hdmi-edid-change-during-suspend.html
* igt@kms_chamelium@hdmi-hpd:
- shard-skl: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +5 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl8/igt@kms_chamelium@hdmi-hpd.html
* igt@kms_chamelium@vga-hpd:
- shard-apl: NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +23 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-apl7/igt@kms_chamelium@vga-hpd.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-snb: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +17 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-snb6/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
- shard-kbl: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +9 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl7/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_content_protection@legacy:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109300] / [fdo#111066])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb8/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@srm:
- shard-kbl: NOTRUN -> [TIMEOUT][44] ([i915#1319])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl1/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl: [PASS][45] -> [FAIL][46] ([i915#3444])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-512x512-sliding:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109278] / [fdo#109279])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb8/igt@kms_cursor_crc@pipe-c-cursor-512x512-sliding.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [PASS][48] -> [FAIL][49] ([i915#72])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [PASS][50] -> [INCOMPLETE][51] ([i915#155] / [i915#180] / [i915#636])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-panning-vs-hang:
- shard-iclb: NOTRUN -> [SKIP][52] ([fdo#109274]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb8/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2:
- shard-glk: [PASS][53] -> [FAIL][54] ([i915#79])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
- shard-snb: NOTRUN -> [SKIP][55] ([fdo#109271]) +348 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-snb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
- shard-iclb: NOTRUN -> [SKIP][56] ([fdo#109280]) +3 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][57] -> [FAIL][58] ([i915#1188])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
- shard-iclb: NOTRUN -> [SKIP][59] ([fdo#109289])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb8/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#533]) +2 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-apl1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#533]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl7/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][62] ([fdo#108145] / [i915#265]) +2 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][63] ([fdo#108145] / [i915#265]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl1/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][64] ([i915#265])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl7/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#658]) +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
- shard-skl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#658])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
* igt@kms_psr2_su@page_flip:
- shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#658]) +3 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-apl2/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][68] -> [SKIP][69] ([fdo#109441]) +2 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb1/igt@kms_psr@psr2_no_drrs.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-skl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#533]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl8/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-fb-id:
- shard-kbl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#2437])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl7/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#2437])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-apl7/igt@kms_writeback@writeback-invalid-parameters.html
* igt@nouveau_crc@ctx-flip-threshold-reset-after-capture:
- shard-iclb: NOTRUN -> [SKIP][73] ([i915#2530])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb8/igt@nouveau_crc@ctx-flip-threshold-reset-after-capture.html
* igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame:
- shard-apl: NOTRUN -> [SKIP][74] ([fdo#109271]) +254 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-apl1/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html
* igt@perf_pmu@rc6-suspend:
- shard-kbl: [PASS][75] -> [DMESG-WARN][76] ([i915#180])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl2/igt@perf_pmu@rc6-suspend.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl1/igt@perf_pmu@rc6-suspend.html
* igt@prime_nv_api@i915_self_import:
- shard-skl: NOTRUN -> [SKIP][77] ([fdo#109271]) +45 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl8/igt@prime_nv_api@i915_self_import.html
* igt@sysfs_clients@fair-7:
- shard-kbl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2994])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl1/igt@sysfs_clients@fair-7.html
* igt@sysfs_clients@recycle-many:
- shard-apl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2994]) +4 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-apl1/igt@sysfs_clients@recycle-many.html
- shard-skl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2994]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl8/igt@sysfs_clients@recycle-many.html
#### Possible fixes ####
* igt@gem_ctx_persistence@many-contexts:
- shard-iclb: [INCOMPLETE][81] ([i915#3057]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb3/igt@gem_ctx_persistence@many-contexts.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb8/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_eio@unwedge-stress:
- shard-skl: [TIMEOUT][83] ([i915#2369] / [i915#3063]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl7/igt@gem_eio@unwedge-stress.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl8/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][85] ([i915#2842]) -> [PASS][86] +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-glk: [FAIL][87] ([i915#2842]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk8/igt@gem_exec_fair@basic-none-solo@rcs0.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-glk5/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [FAIL][89] ([i915#2842]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-apl6/igt@gem_exec_fair@basic-none@vcs0.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-apl6/igt@gem_exec_fair@basic-none@vcs0.html
* igt@kms_color@pipe-b-ctm-red-to-blue:
- shard-skl: [DMESG-WARN][91] ([i915#1982]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl5/igt@kms_color@pipe-b-ctm-red-to-blue.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl1/igt@kms_color@pipe-b-ctm-red-to-blue.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][93] ([i915#180]) -> [PASS][94] +4 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [FAIL][95] ([i915#72]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-iclb: [FAIL][97] ([i915#2346]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb2/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [FAIL][99] ([i915#79]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [DMESG-WARN][101] ([i915#180]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-apl3/igt@kms_flip@flip-vs-suspend@a-dp1.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-apl3/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
- shard-skl: [FAIL][103] ([i915#2122]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl4/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][105] ([i915#1188]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][107] ([fdo#109441]) -> [PASS][108] +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb6/igt@kms_psr@psr2_primary_mmap_cpu.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
#### Warnings ####
* igt@gem_mmap_gtt@cpuset-basic-small-copy-xy:
- shard-skl: [INCOMPLETE][109] ([i915#198]) -> [INCOMPLETE][110] ([i915#198] / [i915#3468])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl7/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl5/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-skl: [SKIP][111] ([fdo#109271] / [i915#658]) -> [INCOMPLETE][112] ([i915#198])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl1/igt@i915_pm_dc@dc3co-vpb-simulation.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl7/igt@i915_pm_dc@dc3co-vpb-simulation.html
- shard-iclb: [SKIP][113] ([i915#658]) -> [SKIP][114] ([i915#588])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb6/igt@i915_pm_dc@dc3co-vpb-simulation.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][115] ([i915#2684]) -> [WARN][116] ([i915#1804] / [i915#2684])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb6/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_selftest@live@execlists:
- shard-iclb: [INCOMPLETE][117] ([i915#2782] / [i915#3462]) -> [DMESG-FAIL][118] ([i915#3462])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb2/igt@i915_selftest@live@execlists.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb7/igt@i915_selftest@live@execlists.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3:
- shard-iclb: [SKIP][119] ([i915#2920]) -> [SKIP][120] ([i915#658]) +1 similar issue
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
- shard-iclb: [SKIP][121] ([i915#658]) -> [SKIP][122] ([i915#2920]) +2 similar issues
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2722] / [i915#3002] / [i915#3363] / [i915#602]) -> ([FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152], [FAIL][153], [FAIL][154], [FAIL][155], [FAIL][156]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2292] / [i915#2722] / [i915#3002] / [i915#3363] / [i915#602] / [i915#92])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl1/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl2/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl1/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl2/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl3/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl2/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl2/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl7/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl7/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl7/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl7/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl7/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl4/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl7/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl4/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl4/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl4/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl1/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl2/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl3/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl1/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl3/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl1/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl2/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl1/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl3/igt@runner@aborted.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl1/igt@runner@aborted.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl2/igt@runner@aborted.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl4/igt@runner@aborted.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl4/igt@runner@aborted.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl7/igt@runner@aborted.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl4/igt@runner@aborted.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl7/igt@runner@aborted.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl7/igt@runner@aborted.html
- shard-iclb: ([FAIL][157], [FAIL][158], [FAIL][159], [FAIL][160], [FAIL][161], [FAIL][162]) ([i915#2426] / [i915#2722] / [i915#2782] / [i915#3002]) -> ([FAIL][163], [FAIL][164], [FAIL][165], [FAIL][166], [FAIL][167], [FAIL][168], [FAIL][169], [FAIL][170]) ([i915#2722] / [i915#2782] / [i915#3002])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb1/igt@runner@aborted.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb6/igt@runner@aborted.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb3/igt@runner@aborted.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb6/igt@runner@aborted.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb5/igt@runner@aborted.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/sha
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [RFC v3 1/2] drm/i915/dg1: Adjust the AUDIO power domain
2021-06-01 10:02 ` [Intel-gfx] [RFC v3 1/2] drm/i915/dg1: Adjust the AUDIO power domain Anshuman Gupta
@ 2021-06-07 15:21 ` Kai Vehmanen
2021-06-28 17:42 ` Imre Deak
1 sibling, 0 replies; 9+ messages in thread
From: Kai Vehmanen @ 2021-06-07 15:21 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
Hi,
On Tue, 1 Jun 2021, Anshuman Gupta wrote:
> DG1 and XE_PLD platforms has Audio MMIO/VERBS lies in PG0 power
> well. Adjusting the power domain accordingly to
> POWER_DOMAIN_AUDIO_VERBS for audio detection and POWER_DOMAIN_AUDIO
> for audio playback.
thanks Anshuman! From audio perspective this looks good to go.
It would seem we don't need any additional code in display/intel_audio.c.
In theory, this leaves some corner cases, where we will take PD_AUDIO when
only PD_AUDIO_VERBS would suffice, but these mostly relate to initial
audio driver probe, so no need add separate logic for these.
Br, Kai
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [RFC v3 1/2] drm/i915/dg1: Adjust the AUDIO power domain
2021-06-01 10:02 ` [Intel-gfx] [RFC v3 1/2] drm/i915/dg1: Adjust the AUDIO power domain Anshuman Gupta
2021-06-07 15:21 ` Kai Vehmanen
@ 2021-06-28 17:42 ` Imre Deak
2021-06-30 11:44 ` Gupta, Anshuman
1 sibling, 1 reply; 9+ messages in thread
From: Imre Deak @ 2021-06-28 17:42 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
On Tue, Jun 01, 2021 at 03:32:27PM +0530, Anshuman Gupta wrote:
> DG1 and XE_PLD platforms has Audio MMIO/VERBS lies in PG0 power
> well. Adjusting the power domain accordingly to
> POWER_DOMAIN_AUDIO_VERBS for audio detection and POWER_DOMAIN_AUDIO
> for audio playback.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Kai Vehmanen <kai.vehmanen@linux.intel.com>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 382 +++++++++++++++++-
> .../drm/i915/display/intel_display_power.h | 1 +
> 2 files changed, 382 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 2f7d1664c473..da5894138e8b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -106,6 +106,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
> return "PORT_OTHER";
> case POWER_DOMAIN_VGA:
> return "VGA";
> + case POWER_DOMAIN_AUDIO_VERBS:
> + return "AUDIO_VERBS";
Maybe better named AUDIO_MMIO, as VERBS are a subset of that imo.
> case POWER_DOMAIN_AUDIO:
> return "AUDIO";
Let's also rename this to AUDIO_PLAYBACK for clarity.
> case POWER_DOMAIN_AUX_A:
> @@ -2499,6 +2501,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
> BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
> BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> BIT_ULL(POWER_DOMAIN_AUDIO) | \
> BIT_ULL(POWER_DOMAIN_AUX_B) | \
> BIT_ULL(POWER_DOMAIN_AUX_C) | \
> @@ -2549,6 +2552,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
> BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> BIT_ULL(POWER_DOMAIN_AUDIO) | \
> BIT_ULL(POWER_DOMAIN_AUX_B) | \
> BIT_ULL(POWER_DOMAIN_AUX_C) | \
> @@ -2582,6 +2586,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
> BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> BIT_ULL(POWER_DOMAIN_AUDIO) | \
> BIT_ULL(POWER_DOMAIN_INIT))
>
> @@ -2598,6 +2603,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
> BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> BIT_ULL(POWER_DOMAIN_AUDIO) | \
> BIT_ULL(POWER_DOMAIN_INIT))
>
> @@ -2616,6 +2622,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> BIT_ULL(POWER_DOMAIN_AUX_B) | \
> BIT_ULL(POWER_DOMAIN_AUX_C) | \
> BIT_ULL(POWER_DOMAIN_AUX_D) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> BIT_ULL(POWER_DOMAIN_AUDIO) | \
> BIT_ULL(POWER_DOMAIN_VGA) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> @@ -2651,6 +2658,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> BIT_ULL(POWER_DOMAIN_AUX_B) | \
> BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> BIT_ULL(POWER_DOMAIN_AUDIO) | \
> BIT_ULL(POWER_DOMAIN_VGA) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> @@ -2684,6 +2692,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> BIT_ULL(POWER_DOMAIN_AUX_B) | \
> BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> BIT_ULL(POWER_DOMAIN_AUDIO) | \
> BIT_ULL(POWER_DOMAIN_VGA) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> @@ -2739,6 +2748,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> BIT_ULL(POWER_DOMAIN_AUX_C) | \
> BIT_ULL(POWER_DOMAIN_AUX_D) | \
> BIT_ULL(POWER_DOMAIN_AUX_F) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> BIT_ULL(POWER_DOMAIN_AUDIO) | \
> BIT_ULL(POWER_DOMAIN_VGA) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> @@ -2821,6 +2831,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
> BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
> BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> BIT_ULL(POWER_DOMAIN_AUDIO) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> /*
> @@ -2913,6 +2924,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
> BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
> BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> BIT_ULL(POWER_DOMAIN_AUDIO) | \
> BIT_ULL(POWER_DOMAIN_INIT))
>
> @@ -2983,6 +2995,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> RKL_PW_4_POWER_DOMAINS | \
> BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> BIT_ULL(POWER_DOMAIN_AUDIO) | \
> BIT_ULL(POWER_DOMAIN_VGA) | \
> BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> @@ -3020,6 +3033,42 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> BIT_ULL(POWER_DOMAIN_AUX_B) | \
> BIT_ULL(POWER_DOMAIN_INIT))
>
> +/*
> + * DG1 Audio MMIO/VERBS lies in PG0 power well.
> + */
> +
> +#define DG1_PW_2_POWER_DOMAINS ( \
> + DG1_PW_3_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
Let's keep the order for other platforms and move DG1_PW_2 after
the DG1_PW_3 definition.
> +
> +#define DG1_PW_3_POWER_DOMAINS ( \
> + TGL_PW_4_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC5) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC6) | \
DG1 has only TC1/2 DDIs.
> + BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
Only AUX_USBC1/2.
> + BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
No TBT on DG1.
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
What about DC3co? I read about this change on HSD 1407435623:
"DC3 clock off mode is not possible with this mode since cdclk cannot be turned off."
Will DMC take care of this?
Could you please open a ticket to clarify the
"Audio codec idle and disabled."
DC3co requirement text wrt. this change on the BSpec/49196 page?
> /*
> * XE_LPD Power Domains
> *
What about the D13 platform? Looks like it has the same split between
the MMIO and playback audio functionality.
> @@ -4497,6 +4546,335 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> };
>
> +static const struct i915_power_well_desc dg1_power_wells[] = {
Let's follow the order of platform definitions and move this after the
rkl power well list.
> + {
> + .name = "always-on",
> + .always_on = true,
> + .domains = POWER_DOMAIN_MASK,
> + .ops = &i9xx_always_on_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + },
> + {
> + .name = "power well 1",
> + /* Handled by the DMC firmware */
> + .always_on = true,
> + .domains = 0,
> + .ops = &hsw_power_well_ops,
> + .id = SKL_DISP_PW_1,
> + {
> + .hsw.regs = &hsw_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_PW_1,
> + .hsw.has_fuses = true,
> + },
> + },
> + {
> + .name = "DC off",
> + .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .id = SKL_DISP_DC_OFF,
> + },
> + {
> + .name = "power well 2",
> + .domains = DG1_PW_2_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = SKL_DISP_PW_2,
> + {
> + .hsw.regs = &hsw_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> + .hsw.has_fuses = true,
> + },
> + },
> + {
> + .name = "power well 3",
> + .domains = DG1_PW_3_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = ICL_DISP_PW_3,
> + {
> + .hsw.regs = &hsw_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_PW_3,
> + .hsw.irq_pipe_mask = BIT(PIPE_B),
> + .hsw.has_vga = true,
> + .hsw.has_fuses = true,
> + },
> + },
> + {
> + .name = "DDI A IO",
> + .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> + }
> + },
> + {
> + .name = "DDI B IO",
> + .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> + }
> + },
> + {
> + .name = "DDI C IO",
> + .domains = ICL_DDI_IO_C_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
> + }
> + },
No DDI C on DG1.
> + {
> + .name = "DDI IO TC1",
> + .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
> + },
> + },
> + {
> + .name = "DDI IO TC2",
> + .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
> + },
> + },
> + {
> + .name = "DDI IO TC3",
> + .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
> + },
> + },
> + {
> + .name = "DDI IO TC4",
> + .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
> + },
> + },
> + {
> + .name = "DDI IO TC5",
> + .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
> + },
> + },
> + {
> + .name = "DDI IO TC6",
> + .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_ddi_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
> + },
> + },
Only DDI TC1/2 on DG1.
> + {
> + .name = "AUX A",
> + .domains = TGL_AUX_A_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> + },
> + },
> + {
> + .name = "AUX B",
> + .domains = TGL_AUX_B_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> + },
> + },
> + {
> + .name = "AUX C",
> + .domains = TGL_AUX_C_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
> + },
> + },
No AUX C on DG1.
> + {
> + .name = "AUX USBC1",
> + .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
> + .hsw.is_tc_tbt = false,
> + },
> + },
> + {
> + .name = "AUX USBC2",
> + .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
> + .hsw.is_tc_tbt = false,
> + },
> + },
> + {
> + .name = "AUX USBC3",
> + .domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
> + .hsw.is_tc_tbt = false,
> + },
> + },
> + {
> + .name = "AUX USBC4",
> + .domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
> + .hsw.is_tc_tbt = false,
> + },
> + },
> + {
> + .name = "AUX USBC5",
> + .domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
> + .hsw.is_tc_tbt = false,
> + },
> + },
> + {
> + .name = "AUX USBC6",
> + .domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
> + .hsw.is_tc_tbt = false,
> + },
> + },
Only AUX USBC1/2 on DG1.
> + {
> + .name = "AUX TBT1",
> + .domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
> + .hsw.is_tc_tbt = true,
> + },
> + },
> + {
> + .name = "AUX TBT2",
> + .domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
> + .hsw.is_tc_tbt = true,
> + },
> + },
> + {
> + .name = "AUX TBT3",
> + .domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
> + .hsw.is_tc_tbt = true,
> + },
> + },
> + {
> + .name = "AUX TBT4",
> + .domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
> + .hsw.is_tc_tbt = true,
> + },
> + },
> + {
> + .name = "AUX TBT5",
> + .domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
> + .hsw.is_tc_tbt = true,
> + },
> + },
> + {
> + .name = "AUX TBT6",
> + .domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &icl_aux_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
> + .hsw.is_tc_tbt = true,
> + },
> + },
No TBT on DG1.
> + {
> + .name = "power well 4",
> + .domains = TGL_PW_4_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &hsw_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_PW_4,
> + .hsw.has_fuses = true,
> + .hsw.irq_pipe_mask = BIT(PIPE_C),
> + }
> + },
> + {
> + .name = "power well 5",
> + .domains = TGL_PW_5_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.regs = &hsw_power_well_regs,
> + .hsw.idx = TGL_PW_CTL_IDX_PW_5,
> + .hsw.has_fuses = true,
> + .hsw.irq_pipe_mask = BIT(PIPE_D),
> + },
> + },
> +};
> +
> static const struct i915_power_well_desc rkl_power_wells[] = {
> {
> .name = "always-on",
> @@ -5110,9 +5488,11 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> err = 0;
> } else if (DISPLAY_VER(dev_priv) >= 13) {
> err = set_power_wells(power_domains, xelpd_power_wells);
> - } else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
> + } else if (IS_ALDERLAKE_S(dev_priv)) {
> err = set_power_wells_mask(power_domains, tgl_power_wells,
> BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
> + } else if (IS_DG1(dev_priv)) {
> + err = set_power_wells(power_domains, dg1_power_wells);
Let's move this after the D13 case.
> } else if (IS_ROCKETLAKE(dev_priv)) {
> err = set_power_wells(power_domains, rkl_power_wells);
> } else if (DISPLAY_VER(dev_priv) == 12) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 4f0917df4375..d9c824264ac9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -76,6 +76,7 @@ enum intel_display_power_domain {
> POWER_DOMAIN_PORT_CRT,
> POWER_DOMAIN_PORT_OTHER,
> POWER_DOMAIN_VGA,
> + POWER_DOMAIN_AUDIO_VERBS,
> POWER_DOMAIN_AUDIO,
> POWER_DOMAIN_AUX_A,
> POWER_DOMAIN_AUX_B,
> --
> 2.26.2
>
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [RFC v3 1/2] drm/i915/dg1: Adjust the AUDIO power domain
2021-06-28 17:42 ` Imre Deak
@ 2021-06-30 11:44 ` Gupta, Anshuman
0 siblings, 0 replies; 9+ messages in thread
From: Gupta, Anshuman @ 2021-06-30 11:44 UTC (permalink / raw)
To: Deak, Imre; +Cc: intel-gfx
> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Monday, June 28, 2021 11:12 PM
> To: Gupta, Anshuman <anshuman.gupta@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Ville Syrjälä <ville.syrjala@linux.intel.com>;
> Kai Vehmanen <kai.vehmanen@linux.intel.com>; Shankar, Uma
> <uma.shankar@intel.com>
> Subject: Re: [RFC v3 1/2] drm/i915/dg1: Adjust the AUDIO power domain
>
> On Tue, Jun 01, 2021 at 03:32:27PM +0530, Anshuman Gupta wrote:
> > DG1 and XE_PLD platforms has Audio MMIO/VERBS lies in PG0 power well.
> > Adjusting the power domain accordingly to POWER_DOMAIN_AUDIO_VERBS
> for
> > audio detection and POWER_DOMAIN_AUDIO for audio playback.
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Kai Vehmanen <kai.vehmanen@linux.intel.com>
> > Cc: Uma Shankar <uma.shankar@intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > .../drm/i915/display/intel_display_power.c | 382 +++++++++++++++++-
> > .../drm/i915/display/intel_display_power.h | 1 +
> > 2 files changed, 382 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 2f7d1664c473..da5894138e8b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -106,6 +106,8 @@ intel_display_power_domain_str(enum
> intel_display_power_domain domain)
> > return "PORT_OTHER";
> > case POWER_DOMAIN_VGA:
> > return "VGA";
> > + case POWER_DOMAIN_AUDIO_VERBS:
> > + return "AUDIO_VERBS";
>
> Maybe better named AUDIO_MMIO, as VERBS are a subset of that imo.
>
> > case POWER_DOMAIN_AUDIO:
> > return "AUDIO";
>
> Let's also rename this to AUDIO_PLAYBACK for clarity.
>
> > case POWER_DOMAIN_AUX_A:
> > @@ -2499,6 +2501,7 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> > BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
> > BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
> > BIT_ULL(POWER_DOMAIN_VGA) | \
> > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> > BIT_ULL(POWER_DOMAIN_AUDIO) | \
> > BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > @@ -2549,6 +2552,7 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> > BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> > BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
> > BIT_ULL(POWER_DOMAIN_VGA) | \
> > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> > BIT_ULL(POWER_DOMAIN_AUDIO) | \
> > BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > @@ -2582,6 +2586,7 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> > BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> > BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
> > BIT_ULL(POWER_DOMAIN_VGA) | \
> > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> > BIT_ULL(POWER_DOMAIN_AUDIO) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> >
> > @@ -2598,6 +2603,7 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> > BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> > BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
> > BIT_ULL(POWER_DOMAIN_VGA) | \
> > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> > BIT_ULL(POWER_DOMAIN_AUDIO) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> >
> > @@ -2616,6 +2622,7 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> > BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > BIT_ULL(POWER_DOMAIN_AUX_D) | \
> > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> > BIT_ULL(POWER_DOMAIN_AUDIO) | \
> > BIT_ULL(POWER_DOMAIN_VGA) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> > @@ -2651,6 +2658,7 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> > BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> > BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> > BIT_ULL(POWER_DOMAIN_AUDIO) | \
> > BIT_ULL(POWER_DOMAIN_VGA) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> > @@ -2684,6 +2692,7 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> > BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> > BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> > BIT_ULL(POWER_DOMAIN_AUDIO) | \
> > BIT_ULL(POWER_DOMAIN_VGA) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> > @@ -2739,6 +2748,7 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> > BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > BIT_ULL(POWER_DOMAIN_AUX_D) | \
> > BIT_ULL(POWER_DOMAIN_AUX_F) | \
> > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> > BIT_ULL(POWER_DOMAIN_AUDIO) | \
> > BIT_ULL(POWER_DOMAIN_VGA) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> > @@ -2821,6 +2831,7 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> > BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
> > BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
> > BIT_ULL(POWER_DOMAIN_VGA) | \
> > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> > BIT_ULL(POWER_DOMAIN_AUDIO) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> > /*
> > @@ -2913,6 +2924,7 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> > BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
> > BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
> > BIT_ULL(POWER_DOMAIN_VGA) | \
> > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> > BIT_ULL(POWER_DOMAIN_AUDIO) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> >
> > @@ -2983,6 +2995,7 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> > RKL_PW_4_POWER_DOMAINS | \
> > BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> > BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \
> > BIT_ULL(POWER_DOMAIN_AUDIO) | \
> > BIT_ULL(POWER_DOMAIN_VGA) | \
> > BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> > @@ -3020,6 +3033,42 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> > BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> >
> > +/*
> > + * DG1 Audio MMIO/VERBS lies in PG0 power well.
> > + */
> > +
> > +#define DG1_PW_2_POWER_DOMAINS ( \
> > + DG1_PW_3_POWER_DOMAINS | \
> > + BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
> > + BIT_ULL(POWER_DOMAIN_INIT))
>
> Let's keep the order for other platforms and move DG1_PW_2 after the
> DG1_PW_3 definition.
>
> > +
> > +#define DG1_PW_3_POWER_DOMAINS ( \
> > + TGL_PW_4_POWER_DOMAINS | \
> > + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> > + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> > + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC5) | \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC6) | \
>
> DG1 has only TC1/2 DDIs.
>
> > + BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
>
> Only AUX_USBC1/2.
>
> > + BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
>
> No TBT on DG1.
>
> > + BIT_ULL(POWER_DOMAIN_VGA) | \
> > + BIT_ULL(POWER_DOMAIN_AUDIO) | \
> > + BIT_ULL(POWER_DOMAIN_INIT))
> > +
>
>
> What about DC3co? I read about this change on HSD 1407435623:
> "DC3 clock off mode is not possible with this mode since cdclk cannot be turned
> off."
>
> Will DMC take care of this?
>
> Could you please open a ticket to clarify the "Audio codec idle and disabled."
> DC3co requirement text wrt. this change on the BSpec/49196 page?
Thanks Imre for Review, have raised a ticket for above issue
https://gfxspecs.intel.com/Predator/Issue/27828
I will fix all the review comments in next revision.
Br,
Anshuman Gupta.
>
> > /*
> > * XE_LPD Power Domains
> > *
>
> What about the D13 platform? Looks like it has the same split between the
> MMIO and playback audio functionality.
>
>
> > @@ -4497,6 +4546,335 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> > },
> > };
> >
> > +static const struct i915_power_well_desc dg1_power_wells[] = {
>
> Let's follow the order of platform definitions and move this after the rkl power
> well list.
>
> > + {
> > + .name = "always-on",
> > + .always_on = true,
> > + .domains = POWER_DOMAIN_MASK,
> > + .ops = &i9xx_always_on_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + },
> > + {
> > + .name = "power well 1",
> > + /* Handled by the DMC firmware */
> > + .always_on = true,
> > + .domains = 0,
> > + .ops = &hsw_power_well_ops,
> > + .id = SKL_DISP_PW_1,
> > + {
> > + .hsw.regs = &hsw_power_well_regs,
> > + .hsw.idx = ICL_PW_CTL_IDX_PW_1,
> > + .hsw.has_fuses = true,
> > + },
> > + },
> > + {
> > + .name = "DC off",
> > + .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
> > + .ops = &gen9_dc_off_power_well_ops,
> > + .id = SKL_DISP_DC_OFF,
> > + },
> > + {
> > + .name = "power well 2",
> > + .domains = DG1_PW_2_POWER_DOMAINS,
> > + .ops = &hsw_power_well_ops,
> > + .id = SKL_DISP_PW_2,
> > + {
> > + .hsw.regs = &hsw_power_well_regs,
> > + .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> > + .hsw.has_fuses = true,
> > + },
> > + },
> > + {
> > + .name = "power well 3",
> > + .domains = DG1_PW_3_POWER_DOMAINS,
> > + .ops = &hsw_power_well_ops,
> > + .id = ICL_DISP_PW_3,
> > + {
> > + .hsw.regs = &hsw_power_well_regs,
> > + .hsw.idx = ICL_PW_CTL_IDX_PW_3,
> > + .hsw.irq_pipe_mask = BIT(PIPE_B),
> > + .hsw.has_vga = true,
> > + .hsw.has_fuses = true,
> > + },
> > + },
> > + {
> > + .name = "DDI A IO",
> > + .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> > + .ops = &hsw_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_ddi_power_well_regs,
> > + .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> > + }
> > + },
> > + {
> > + .name = "DDI B IO",
> > + .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> > + .ops = &hsw_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_ddi_power_well_regs,
> > + .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> > + }
> > + },
> > + {
> > + .name = "DDI C IO",
> > + .domains = ICL_DDI_IO_C_POWER_DOMAINS,
> > + .ops = &hsw_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_ddi_power_well_regs,
> > + .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
> > + }
> > + },
>
> No DDI C on DG1.
>
> > + {
> > + .name = "DDI IO TC1",
> > + .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> > + .ops = &hsw_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_ddi_power_well_regs,
> > + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
> > + },
> > + },
> > + {
> > + .name = "DDI IO TC2",
> > + .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> > + .ops = &hsw_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_ddi_power_well_regs,
> > + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
> > + },
> > + },
> > + {
> > + .name = "DDI IO TC3",
> > + .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
> > + .ops = &hsw_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_ddi_power_well_regs,
> > + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
> > + },
> > + },
> > + {
> > + .name = "DDI IO TC4",
> > + .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
> > + .ops = &hsw_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_ddi_power_well_regs,
> > + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
> > + },
> > + },
> > + {
> > + .name = "DDI IO TC5",
> > + .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
> > + .ops = &hsw_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_ddi_power_well_regs,
> > + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
> > + },
> > + },
> > + {
> > + .name = "DDI IO TC6",
> > + .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
> > + .ops = &hsw_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_ddi_power_well_regs,
> > + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
> > + },
> > + },
>
> Only DDI TC1/2 on DG1.
>
> > + {
> > + .name = "AUX A",
> > + .domains = TGL_AUX_A_IO_POWER_DOMAINS,
> > + .ops = &icl_aux_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_aux_power_well_regs,
> > + .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> > + },
> > + },
> > + {
> > + .name = "AUX B",
> > + .domains = TGL_AUX_B_IO_POWER_DOMAINS,
> > + .ops = &icl_aux_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_aux_power_well_regs,
> > + .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> > + },
> > + },
> > + {
> > + .name = "AUX C",
> > + .domains = TGL_AUX_C_IO_POWER_DOMAINS,
> > + .ops = &icl_aux_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_aux_power_well_regs,
> > + .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
> > + },
> > + },
>
> No AUX C on DG1.
>
> > + {
> > + .name = "AUX USBC1",
> > + .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
> > + .ops = &icl_aux_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_aux_power_well_regs,
> > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
> > + .hsw.is_tc_tbt = false,
> > + },
> > + },
> > + {
> > + .name = "AUX USBC2",
> > + .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
> > + .ops = &icl_aux_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_aux_power_well_regs,
> > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
> > + .hsw.is_tc_tbt = false,
> > + },
> > + },
> > + {
> > + .name = "AUX USBC3",
> > + .domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
> > + .ops = &icl_aux_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_aux_power_well_regs,
> > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
> > + .hsw.is_tc_tbt = false,
> > + },
> > + },
> > + {
> > + .name = "AUX USBC4",
> > + .domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
> > + .ops = &icl_aux_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_aux_power_well_regs,
> > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
> > + .hsw.is_tc_tbt = false,
> > + },
> > + },
> > + {
> > + .name = "AUX USBC5",
> > + .domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
> > + .ops = &icl_aux_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_aux_power_well_regs,
> > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
> > + .hsw.is_tc_tbt = false,
> > + },
> > + },
> > + {
> > + .name = "AUX USBC6",
> > + .domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
> > + .ops = &icl_aux_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_aux_power_well_regs,
> > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
> > + .hsw.is_tc_tbt = false,
> > + },
> > + },
>
> Only AUX USBC1/2 on DG1.
>
> > + {
> > + .name = "AUX TBT1",
> > + .domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
> > + .ops = &icl_aux_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_aux_power_well_regs,
> > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
> > + .hsw.is_tc_tbt = true,
> > + },
> > + },
> > + {
> > + .name = "AUX TBT2",
> > + .domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
> > + .ops = &icl_aux_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_aux_power_well_regs,
> > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
> > + .hsw.is_tc_tbt = true,
> > + },
> > + },
> > + {
> > + .name = "AUX TBT3",
> > + .domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
> > + .ops = &icl_aux_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_aux_power_well_regs,
> > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
> > + .hsw.is_tc_tbt = true,
> > + },
> > + },
> > + {
> > + .name = "AUX TBT4",
> > + .domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
> > + .ops = &icl_aux_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_aux_power_well_regs,
> > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
> > + .hsw.is_tc_tbt = true,
> > + },
> > + },
> > + {
> > + .name = "AUX TBT5",
> > + .domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
> > + .ops = &icl_aux_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_aux_power_well_regs,
> > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
> > + .hsw.is_tc_tbt = true,
> > + },
> > + },
> > + {
> > + .name = "AUX TBT6",
> > + .domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
> > + .ops = &icl_aux_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &icl_aux_power_well_regs,
> > + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
> > + .hsw.is_tc_tbt = true,
> > + },
> > + },
>
> No TBT on DG1.
>
> > + {
> > + .name = "power well 4",
> > + .domains = TGL_PW_4_POWER_DOMAINS,
> > + .ops = &hsw_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &hsw_power_well_regs,
> > + .hsw.idx = ICL_PW_CTL_IDX_PW_4,
> > + .hsw.has_fuses = true,
> > + .hsw.irq_pipe_mask = BIT(PIPE_C),
> > + }
> > + },
> > + {
> > + .name = "power well 5",
> > + .domains = TGL_PW_5_POWER_DOMAINS,
> > + .ops = &hsw_power_well_ops,
> > + .id = DISP_PW_ID_NONE,
> > + {
> > + .hsw.regs = &hsw_power_well_regs,
> > + .hsw.idx = TGL_PW_CTL_IDX_PW_5,
> > + .hsw.has_fuses = true,
> > + .hsw.irq_pipe_mask = BIT(PIPE_D),
> > + },
> > + },
> > +};
> > +
> > static const struct i915_power_well_desc rkl_power_wells[] = {
> > {
> > .name = "always-on",
> > @@ -5110,9 +5488,11 @@ int intel_power_domains_init(struct
> drm_i915_private *dev_priv)
> > err = 0;
> > } else if (DISPLAY_VER(dev_priv) >= 13) {
> > err = set_power_wells(power_domains, xelpd_power_wells);
> > - } else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
> > + } else if (IS_ALDERLAKE_S(dev_priv)) {
> > err = set_power_wells_mask(power_domains, tgl_power_wells,
> >
> BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
> > + } else if (IS_DG1(dev_priv)) {
> > + err = set_power_wells(power_domains, dg1_power_wells);
>
> Let's move this after the D13 case.
>
> > } else if (IS_ROCKETLAKE(dev_priv)) {
> > err = set_power_wells(power_domains, rkl_power_wells);
> > } else if (DISPLAY_VER(dev_priv) == 12) { diff --git
> > a/drivers/gpu/drm/i915/display/intel_display_power.h
> > b/drivers/gpu/drm/i915/display/intel_display_power.h
> > index 4f0917df4375..d9c824264ac9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> > @@ -76,6 +76,7 @@ enum intel_display_power_domain {
> > POWER_DOMAIN_PORT_CRT,
> > POWER_DOMAIN_PORT_OTHER,
> > POWER_DOMAIN_VGA,
> > + POWER_DOMAIN_AUDIO_VERBS,
> > POWER_DOMAIN_AUDIO,
> > POWER_DOMAIN_AUX_A,
> > POWER_DOMAIN_AUX_B,
> > --
> > 2.26.2
> >
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2021-06-01 10:02 [Intel-gfx] [RFC v3 0/2] lpsp with hdmi/dp outputs Anshuman Gupta
2021-06-01 10:02 ` [Intel-gfx] [RFC v3 1/2] drm/i915/dg1: Adjust the AUDIO power domain Anshuman Gupta
2021-06-07 15:21 ` Kai Vehmanen
2021-06-28 17:42 ` Imre Deak
2021-06-30 11:44 ` Gupta, Anshuman
2021-06-01 10:02 ` [Intel-gfx] [RFC v3 2/2] drm/i915/display: Use AUDIO_VERBS for crtc power domain mask Anshuman Gupta
2021-06-01 13:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for lpsp with hdmi/dp outputs Patchwork
2021-06-01 14:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-06-01 18:14 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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