From: Daniel Vetter <daniel@ffwll.ch>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 18/30] drm/i915: Add an interface to dynamically change the cache level
Date: Wed, 13 Apr 2011 20:59:46 +0200 [thread overview]
Message-ID: <20110413185945.GD3660@viiv.ffwll.ch> (raw)
In-Reply-To: <1302640318-23165-19-git-send-email-chris@chris-wilson.co.uk>
> @@ -3002,6 +3002,44 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
> return 0;
> }
>
> +int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
> + enum i915_cache_level cache_level)
> +{
> + int ret;
> +
> + if (obj->cache_level == cache_level)
> + return 0;
> +
> + if (obj->gtt_space) {
> + ret = i915_gem_object_flush_gpu(obj);
> + if (ret)
> + return ret;
> +
> + ret = i915_gem_gtt_bind_object(obj, cache_level);
> + if (ret)
> + return ret;
This momentarily confused me till I've noticed that the fake agp driver
does the right thing and does not re-create a dmar mapping if it already
exists. So much for remembering my own code. Still, maybe extract
i915_gem_gtt_rebind_object from restore_gtt_mappings and use that one
here? Should make the intent clearer.
> + /* Ensure that we invalidate the GPU's caches and TLBs. */
> + obj->base.read_domains &= I915_GEM_GPU_DOMAINS;
I can't make sense of this. Either we really want to ensure that the gpu
buffers get invalidated on next use. But then it's probably
read_domains &= ~GPU_DOMAINS
and would fit better grouped together with the call to object_flush_gpu
(the rebind can't actually fail if the dmar mappings already exist). Or
this is something else and I'm blind.
> + }
> +
> + if (cache_level == I915_CACHE_NONE) {
> + /* If we're coming from LLC cached, then we haven't
> + * actually been tracking whether the data is in the
> + * CPU cache or not, since we only allow one bit set
> + * in obj->write_domain and have been skipping the clflushes.
> + * Just set it to the CPU cache for now.
> + */
> + WARN_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
> +
> + obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
This breaks the invariant that write_domain != 0 implies write_domain ==
read_domains. Yes, if nothing prefetches and we clflush in due time the
caches should still be valid, but paranoid me deems that a bit fragile.
Also future patches shoot down fences, so we might as well shoot down the
gtt mapping completely. That seems required for the redirect gtt mappings
patch, too.
> + obj->base.write_domain = I915_GEM_DOMAIN_CPU;
We might end up here with a write_domain == DOMAIN_GTT. Feels a tad bit
unsafe. I'd prefer either a WARN_ON and push the problem out to callers or
to call flush_gtt_write_domain somewhere in set_cache_level.
This looks like the critical part of the whole patch series so perhaps
fold the follow-up patches in here, too (like fence teardown). This way
there's just one spot that requires _really_ careful thinking.
Also, I haven't thought too hard about the uncached->cached transition on
live objects, which is not (yet) required. Maybe some more careful
handling of the gtt domain (mappings teardown) is needed for that.
-Daniel
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
next prev parent reply other threads:[~2011-04-13 18:59 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-12 20:31 i915 next Chris Wilson
2011-04-12 20:31 ` [PATCH 01/30] drm/i915: Split the crtc_mode_set function along HAS_PCH_SPLIT() lines Chris Wilson
2011-04-12 20:31 ` [PATCH 02/30] drm/i915: Move the vblank pre/post modeset to the common crtc_mode_set Chris Wilson
2011-04-12 20:31 ` [PATCH 03/30] drm/i915: Remove the PCH paths from the pre-Ironlake crtc_mode_set() Chris Wilson
2011-04-12 20:31 ` [PATCH 04/30] drm/i915: Drop the eDP paths from the pre-Ironlake crtc_mode_set Chris Wilson
2011-04-12 20:31 ` [PATCH 05/30] drm/i915: Drop the remaining bit of Ironlake code from i9xx_crtc_mode_set() Chris Wilson
2011-04-12 20:31 ` [PATCH 06/30] drm/i915: Drop non-HAS_PCH_SPLIT() code from ironlake_crtc_mode_set() Chris Wilson
2011-04-12 20:31 ` [PATCH 07/30] drm/i915: Drop remaining pre-Ironlake " Chris Wilson
2011-04-12 20:31 ` [PATCH 08/30] drm/i915: Clean up leftover DPLL and LVDS register choice from pch split Chris Wilson
2011-04-12 20:31 ` [PATCH 09/30] drm/i915: Fold the DPLL limit defines into the structs that use them Chris Wilson
2011-04-12 20:31 ` [PATCH 10/30] drm/i915: fix ilk rc6 teardown locking Chris Wilson
2011-04-12 20:31 ` [PATCH 11/30] drm/1915: ringbuffer wait for idle function Chris Wilson
2011-04-12 20:31 ` [PATCH 12/30] drm/i915: fix rc6 initialization on Ironlake Chris Wilson
2011-04-12 20:31 ` [PATCH 13/30] drm/i915: re-enable rc6 for ironlake Chris Wilson
2011-04-12 20:31 ` [PATCH 14/30] drm/i915: use i915_enable_rc6 on SNB too Chris Wilson
2011-04-12 20:31 ` [PATCH 15/30] drm/i915: Rename agp_type to cache_level Chris Wilson
2011-04-13 15:57 ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 16/30] drm/i915: Mark the cursor and the overlay as being part of the display planes Chris Wilson
2011-04-13 16:00 ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 17/30] drm/i915: Do not clflush snooped objects Chris Wilson
2011-04-13 16:04 ` Daniel Vetter
2011-04-13 17:34 ` Chris Wilson
2011-04-13 20:47 ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 18/30] drm/i915: Add an interface to dynamically change the cache level Chris Wilson
2011-04-13 18:59 ` Daniel Vetter [this message]
2011-04-13 19:21 ` Chris Wilson
2011-04-13 22:27 ` [PATCH 1/3] drm/i915: Introduce i915_gem_object_finish_gpu() Chris Wilson
2011-04-13 22:27 ` [PATCH 2/3] drm/i915: Introduce i915_gem_object_finish_gtt() Chris Wilson
2011-04-13 22:27 ` [PATCH 3/3] drm/i915: Add an interface to dynamically change the cache level Chris Wilson
2011-04-12 20:31 ` [PATCH 19/30] drm/i915: Use the uncached domain for the display planes v2 Chris Wilson
2011-04-12 20:31 ` [PATCH 20/30] drm/i915: Use the CPU domain for snooped pwrites Chris Wilson
2011-04-12 20:31 ` [PATCH 21/30] drm/i915: Redirect GTT mappings to the CPU page if cache-coherent Chris Wilson
2011-04-13 15:57 ` Eric Anholt
2011-04-13 16:19 ` Chris Wilson
2011-04-13 18:35 ` [PATCH] " Chris Wilson
2011-04-13 19:13 ` Daniel Vetter
2011-04-13 19:47 ` Chris Wilson
2011-04-13 20:26 ` [PATCH] drm/i915: Prevent mmap access through the GTT of snooped pages Chris Wilson
2011-04-13 20:51 ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 22/30] drm/i915: Use the LLC mode on gen6 for everything but display Chris Wilson
2011-04-13 19:15 ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 23/30] drm/i915: Cache GT fifo count for SandyBridge Chris Wilson
2011-04-14 2:21 ` Ben Widawsky
2011-04-14 4:48 ` Ben Widawsky
2011-04-12 20:31 ` [PATCH 24/30] drm/i915: Refactor pwrite/pread to use single copy of get_user_pages Chris Wilson
2011-04-13 15:59 ` Eric Anholt
2011-04-13 17:24 ` Chris Wilson
2011-04-13 19:35 ` Eric Anholt
2011-04-13 19:26 ` Daniel Vetter
2011-04-13 19:56 ` Chris Wilson
2011-04-13 20:56 ` Daniel Vetter
2011-04-14 23:23 ` Ben Widawsky
2011-04-15 9:48 ` Paul Menzel
2011-04-16 8:03 ` Chris Wilson
2011-04-12 20:31 ` [PATCH 25/30] drm/i915: s/addr & ~PAGE_MASK/offset_in_page(addr)/ Chris Wilson
2011-04-12 20:31 ` [PATCH 26/30] drm/i915: Maintain fenced gpu access until we flush the fence Chris Wilson
2011-04-13 19:37 ` Daniel Vetter
2011-04-13 20:15 ` Chris Wilson
2011-04-13 20:58 ` Daniel Vetter
2011-04-13 21:37 ` Chris Wilson
2011-04-12 20:31 ` [PATCH 27/30] drm/i915: Invalidate fenced read domains upon flush Chris Wilson
2011-04-13 19:43 ` Daniel Vetter
2011-04-13 20:38 ` Chris Wilson
2011-04-13 21:02 ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 28/30] drm/i915: Pass the fence register number to be written Chris Wilson
2011-04-13 19:48 ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 29/30] drm/i915: Track fence setup separately from fenced object lifetime Chris Wilson
2011-04-13 20:42 ` Daniel Vetter
2011-04-13 21:56 ` Chris Wilson
2011-04-12 20:31 ` [PATCH 30/30] drm/i915: Only print out the actual number of fences for i915_error_state Chris Wilson
2011-04-13 7:26 ` i915 next Chris Wilson
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