From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 26/30] drm/i915: Maintain fenced gpu access
 until we flush the fence
Date: Wed, 13 Apr 2011 22:58:26 +0200
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To: Chris Wilson <chris@chris-wilson.co.uk>
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On Wed, Apr 13, 2011 at 09:15:19PM +0100, Chris Wilson wrote:
> On Wed, 13 Apr 2011 21:37:03 +0200, Daniel Vetter <daniel@ffwll.ch> wrote:
> > On Tue, Apr 12, 2011 at 09:31:54PM +0100, Chris Wilson wrote:
> > > We only want to mark the transition from unfenced GPU access by an
> > > execbuffer, so that we are forced to flush any pending writes through
> > > the fence before updating the register.
> > 
> > The idea behind this change sounds good.
> 
> Whilst I have you in agreement, what do I need to do get your r-b on the
> simple bug fix first? ;-)
Oops, that went mia. So if you want to roll the bugfix independently

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Just add a small comment in the commit msg that it essentially disables
that optimization, in case somebody bisects a performance regression to
this.
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48