From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: Updated -next Date: Fri, 27 Apr 2012 13:45:42 +0200 Message-ID: <20120427114542.GC4841@phenom.ffwll.local> References: <20120421164032.GE5019@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id CBFBB9E73F for ; Fri, 27 Apr 2012 04:44:45 -0700 (PDT) Received: by werp11 with SMTP id p11so482544wer.36 for ; Fri, 27 Apr 2012 04:44:44 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20120421164032.GE5019@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development , Dave Airlie Cc: DRI Development List-Id: intel-gfx@lists.freedesktop.org Hi Dave, A new drm-intel-next pull. Highlights: - More gmbus patches from Daniel Kurtz, I think gmbus is now ready, all known issues fixed. - Fencing cleanup and pipelined fencing removal from Chris. - rc6 residency interface from Ben, useful for powertop. - Cleanups and code reorg around the ringbuffer code (Ben&me). - Use hw semaphores in the pageflip code from Ben. - More vlv stuff from Jesse, unfortunately his vlv cpu is doa, so less merged than I've hoped for - we still have the unused function warning :( - More hsw patches from Eugeni, again, not yet enabled fully. - intel_pm.c refactoring from Eugeni. - Ironlake sprite support from Chris. - And various smaller improvements/fixes all over the place. Note that this pull request also contains a backmerge of -rc3 to sort out a few things in -next. I've also had to frob the shortlog a bit to exclude anything that -rc3 brings in with this pull. Regression wise we have a few strange bugs going on, but for all of them closer inspection revealed that they've been pre-existing, just now slightly more likely to be hit. And for most of them we have a patch already. Otherwise QA has not reported any regressions, and I'm also not aware of anything bad happening in 3.4. For 3.4 Ken discovered that one of the snb workarounds in -next is required to fix hangs in google maps and tons of other apps, so expect another -fixes pull. Cheers, Daniel The following changes since commit effbc4fd8e37e41d6f2bb6bcc611c14b4fbdcf9b: Merge branch 'drm-intel-next' of git://people.freedesktop.org/~danvet/drm-intel into drm-core-next (2012-04-12 10:27:01 +0100) are available in the git repository at: git://people.freedesktop.org/~danvet/drm-intel tags/drm-intel-next-2012-04-23 for you to fetch changes up to a85d4bcb8a0cd5b3c754f98ff91ef2b9b3a73bc5: drm/i915: rc6 residency (fix the fix) (2012-04-23 09:30:14 +0200) ---------------------------------------------------------------- Armin Reese (1): drm/i915: Mask reserved bits in display/sprite address registers Ben Widawsky (10): drm/i915: add rc6 residency times to debugfs drm/i915: use semaphores for the display plane drm/i915: rc6 in sysfs drm/i915: i915_gem_object_sync must handle NULL drm/i915: fix for when semaphore updates fail drm/i915: hide (seqno-1) in ringbuffer code drm/i915: [sparse] trivial sparse fixes drm/i915: [sparse] don't use variable size arrays drm/i915: [GEN7] Use HW scheduler for fixed function shaders drm/i915: rc6 residency (fix the fix) Chris Wilson (25): drm/i915: Reorganise rules for get_fence/put_fence drm/i915: Ironlake shares the same video sprite controls as Sandybridge drm/i915: Allow concurrent read access between CPU and GPU domain drm/i915: Trigger hangcheck if we detect more a repeating missed IRQ drm/i915: Refactor the deferred PM_IIR handling into a single function drm/i915: Export the generic, not arch specific, intel_update_watermarks() drm/i915/sprite: Always enable the scaler on IronLake drm/i915/dp: Flush any outstanding work to turn the VDD off drm/i915: Always flush tiling changes before accessing through the GTT drm/i915: Replace open coded MI_BATCH_GTT drm/i915: Unpin the flip target if we fail to queue the flip drm/i915: intel_update_fbc() requires struct_mutex, so no longer atomic drm/i915: Don't set a MBZ bit in gen2/3 MI_FLUSH drm/i915: Wait for all pending operations to the fb before disabling the pipe drm/i915: Remove the pipelined parameter from get_fence() drm/i915: Remove fence pipelining drm/i915: Remove unused ring->setup_seqno drm/i915: Discard the unused obj->last_fenced_ring drm/i915: Simplify fence finding drm/i915: Remove the unsightly "optimisation" from flush_fence() drm/i915: Prepare to consolidate fence writing drm/i915: Refactor put_fence() to use the common fence writing routine drm/i915: Refactor fence clearing to use the common fence writing routine drm/i915: Refactor get_fence() to use the common fence writing routine drm/i915: Silence the change of LVDS sync polarity Daniel Kurtz (9): drm/i915/intel_i2c: handle zero-length writes drm/i915/intel_i2c: use double-buffered writes drm/i915/intel_i2c: always wait for IDLE before clearing NAK drm/i915/intel_i2c: use WAIT cycle, not STOP drm/i915/intel_i2c: use INDEX cycles for i2c read transactions drm/i915/intel_i2c: reuse GMBUS2 value read in polling loop drm/i915/intel_i2c: remove POSTING_READ() from gmbus transfers drm/i915/intel_i2c: handle zero-length reads drm/i915/intel_i2c: reduce verbosity of some messages Daniel Vetter (24): drm/i915: simplify ppgtt setup drm/i915: re-init modeset hw state after gpu reset drm/i915: rip out ring->irq_mask drm/i915: set ring->size in common ring setup code drm/i915: dynamically set up the render ring functions and params drm/i915: dynamically set up bsd ring functions and params drm/i915: dynamically set up blt ring functions and parameters drm/i915: don't set up rings on gen6+ for non-kms drm/i915: consolidate ring->sync-to functions drm/i915: abstract away ring-specific irq_get/put drm/i915: split out the gen5 ring irq get/put functions drm/i915: don't enable the gen6 bsd ring tail write enable on gen7 drm/i915: split up ring->dispatch_execbuffer functions drm/i915: consolidate ring->add_request a bit drm/i915: don't set up gem ring functions on gen5 for !kms drm/i915: inline enable/disable_irq into ring->get/put_irq drm/i915: don't pwrite tiled objects through the gtt Merge tag 'v3.4-rc3' into drm-intel-next-queued drm/i915: implement a media hang w/a drm/i915: set w/a bit for snb pagefaults drm/i915: properly set ppgtt cacheability on snb drm/i915: implement w/a for incorrect guarband clipping drm/i915: set stc evict disable lra evict w/a drm/i915: invalidate render cache on gen2 Dave Airlie (1): drm/i915/tv: fix open-coded ARRAY_SIZE. Eugeni Dodonov (13): drm/i915: add definition of LPT FDI port width registers drm/i915: add WRPLL divider programming bits drm/i915: share forcewaking code between IVB and HSW drm/i915: haswell has 3 pipes as well drm/i915: share IVB cursor routine with Haswell drm/i915: disable rc6 on haswell for now drm/i915: move fbc-related functionality into intel_pm module drm/i915: move watermarks settings into intel_pm module drm/i915: fix line breaks in intel_pm drm/i915: move drps, rps and rc6-related functions to intel_pm drm/i915: move emon functionality into intel_pm module drm/i915: move clock gating functionality into intel_pm module drm/i915: add generic power management initialization Jesse Barnes (6): drm/i915: use register name when disabling VGA drm/i915: make DP configuration vars less confusing in ironlake_crtc_mode_se drm/i915: check PPS regs for sanity when using eDP drm/i915: disable turbo on ValleyView for now drm/i915: allow PCH PWM override on IVB drm/i915: IBX+ doesn't have separate vsync/hsync controls on the VGA DAC -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48