From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Subject: Re: [PATCH] drm/i915: CPT/PPT pch dp transcoder
 workaround
Date: Thu, 1 Nov 2012 08:35:14 -0700
Message-ID: <20121101083514.4c310d47@jbarnes-desktop>
References: <1351720351-2688-4-git-send-email-daniel.vetter@ffwll.ch>
	<1351757730-11463-1-git-send-email-daniel.vetter@ffwll.ch>
	<20121101073736.49cc9c43@jbarnes-desktop>
	<20121101153345.GV5755@phenom.ffwll.local>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org>
Received: from oproxy12-pub.bluehost.com (oproxy12-pub.bluehost.com
	[50.87.16.10])
	by gabe.freedesktop.org (Postfix) with SMTP id A4E619E958
	for <intel-gfx@lists.freedesktop.org>;
	Thu,  1 Nov 2012 08:35:05 -0700 (PDT)
In-Reply-To: <20121101153345.GV5755@phenom.ffwll.local>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
To: Daniel Vetter <daniel@ffwll.ch>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>, Intel Graphics Development <intel-gfx@lists.freedesktop.org>, Arthur Ranyan <arthur.j.runyan@intel.com>
List-Id: intel-gfx@lists.freedesktop.org

On Thu, 1 Nov 2012 16:33:45 +0100
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Thu, Nov 01, 2012 at 07:37:36AM -0700, Jesse Barnes wrote:
> > > v3: Paulo Zanoni pointed out that this workaround is also required on
> > > the LPT PCH. And Arthur Ranyan confirmed that this workaround is
> > > requierd for all ports on the pch, not just DP: The important part
> > > is that the bit is set whenever the pch transcoder is enabled, and
> > > that it is _not_ set while the fdi link is trained. It is also
> > > important that the pch transcoder is fully disabled, i.e. we have to
> > > wait for bit 30 to clear before clearing the w/a bit.
> 
> See above: "Paulo Zanoni pointed out that this workaround is also required
> on the LPT PCH".
> 
> > > +	if (!HAS_PCH_IBX(dev)) {
> > > +		/* Workaround: Set the timing override bit before enabling the
> > > +		 * pch transcoder. */
> > > +		reg = TRANS_CHICKEN2(pipe);
> > > +		val = I915_READ(reg);
> > > +		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> > > +		I915_WRITE(reg, val);
> > > +	}
> > 
> > I'd like this better if it were HAS_PCH_CPT; we use that as a synonym
> > for PPT elsehwere, and it shouldn't apply to LPT right?  I see LPT has
> > the bit, but I don't know if it's needed (the changelong and summary
> > are misleading if so).
> 
> Paulo's vga patch bomb will split this up, so we can use HAS_PCH_CPT
> instead of !IBX. But since I've written this patch against dinq without
> paulo's patches, hence HAS_CPT would be wrong. So:
> 
> What colour would please you most, Sir?

Just fix the changelog summary then!

-- 
Jesse Barnes, Intel Open Source Technology Center