* [PATCH 1/5] drm/i915: check whether the pch is the soulmate of the cpu
2012-10-31 21:52 [PATCH 0/5] ivb fdi b/c fixes Daniel Vetter
@ 2012-10-31 21:52 ` Daniel Vetter
2012-11-01 15:58 ` Paulo Zanoni
2012-10-31 21:52 ` [PATCH 2/5] drm/i915: drop unnecessary check from fdi_link_train code Daniel Vetter
` (3 subsequent siblings)
4 siblings, 1 reply; 17+ messages in thread
From: Daniel Vetter @ 2012-10-31 21:52 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
We don't really support fancy north display/pch combinations, so
put a big yelling WARN_ON in there. It /should/ be impossible, but
alas, the rumours don't stop (mostly due to really early silicon
sometimes using older PCHs).
v2: Fixup the logic fumble noticed by Paulo Zanoni. I should actually
try to test run the patch next time around ...
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6d0afc9..a5ece75 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -423,19 +423,23 @@ void intel_detect_pch(struct drm_device *dev)
dev_priv->pch_type = PCH_IBX;
dev_priv->num_pch_pll = 2;
DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
+ WARN_ON(!IS_GEN5(dev));
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CPT;
dev_priv->num_pch_pll = 2;
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
+ WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
/* PantherPoint is CPT compatible */
dev_priv->pch_type = PCH_CPT;
dev_priv->num_pch_pll = 2;
DRM_DEBUG_KMS("Found PatherPoint PCH\n");
+ WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_LPT;
dev_priv->num_pch_pll = 0;
DRM_DEBUG_KMS("Found LynxPoint PCH\n");
+ WARN_ON(!IS_HASWELL(dev));
}
BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
}
--
1.7.11.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 1/5] drm/i915: check whether the pch is the soulmate of the cpu
2012-10-31 21:52 ` [PATCH 1/5] drm/i915: check whether the pch is the soulmate of the cpu Daniel Vetter
@ 2012-11-01 15:58 ` Paulo Zanoni
0 siblings, 0 replies; 17+ messages in thread
From: Paulo Zanoni @ 2012-11-01 15:58 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
Hi
2012/10/31 Daniel Vetter <daniel.vetter@ffwll.ch>:
> We don't really support fancy north display/pch combinations, so
> put a big yelling WARN_ON in there. It /should/ be impossible, but
> alas, the rumours don't stop (mostly due to really early silicon
> sometimes using older PCHs).
>
> v2: Fixup the logic fumble noticed by Paulo Zanoni. I should actually
> try to test run the patch next time around ...
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 6d0afc9..a5ece75 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -423,19 +423,23 @@ void intel_detect_pch(struct drm_device *dev)
> dev_priv->pch_type = PCH_IBX;
> dev_priv->num_pch_pll = 2;
> DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
> + WARN_ON(!IS_GEN5(dev));
> } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_CPT;
> dev_priv->num_pch_pll = 2;
> DRM_DEBUG_KMS("Found CougarPoint PCH\n");
> + WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
> } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
> /* PantherPoint is CPT compatible */
> dev_priv->pch_type = PCH_CPT;
> dev_priv->num_pch_pll = 2;
> DRM_DEBUG_KMS("Found PatherPoint PCH\n");
> + WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
> } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_LPT;
> dev_priv->num_pch_pll = 0;
> DRM_DEBUG_KMS("Found LynxPoint PCH\n");
> + WARN_ON(!IS_HASWELL(dev));
> }
> BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
> }
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/5] drm/i915: drop unnecessary check from fdi_link_train code
2012-10-31 21:52 [PATCH 0/5] ivb fdi b/c fixes Daniel Vetter
2012-10-31 21:52 ` [PATCH 1/5] drm/i915: check whether the pch is the soulmate of the cpu Daniel Vetter
@ 2012-10-31 21:52 ` Daniel Vetter
2012-10-31 21:52 ` [PATCH 3/5] drm/i915: CPT/PPT pch transcoder workaround Daniel Vetter
` (2 subsequent siblings)
4 siblings, 0 replies; 17+ messages in thread
From: Daniel Vetter @ 2012-10-31 21:52 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
They are all written for a specific north disaplay->pch combination.
So stop pretending otherwise.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_display.c | 14 +++++---------
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3b62999..129059b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2409,11 +2409,9 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
udelay(150);
/* Ironlake workaround, enable clock pointer after FDI enable*/
- if (HAS_PCH_IBX(dev)) {
- I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
- I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
- FDI_RX_PHASE_SYNC_POINTER_EN);
- }
+ I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
+ I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
+ FDI_RX_PHASE_SYNC_POINTER_EN);
reg = FDI_RX_IIR(pipe);
for (tries = 0; tries < 5; tries++) {
@@ -2519,8 +2517,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
POSTING_READ(reg);
udelay(150);
- if (HAS_PCH_CPT(dev))
- cpt_phase_pointer_enable(dev, pipe);
+ cpt_phase_pointer_enable(dev, pipe);
for (i = 0; i < 4; i++) {
reg = FDI_TX_CTL(pipe);
@@ -2654,8 +2651,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
POSTING_READ(reg);
udelay(150);
- if (HAS_PCH_CPT(dev))
- cpt_phase_pointer_enable(dev, pipe);
+ cpt_phase_pointer_enable(dev, pipe);
for (i = 0; i < 4; i++) {
reg = FDI_TX_CTL(pipe);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 3/5] drm/i915: CPT/PPT pch transcoder workaround
2012-10-31 21:52 [PATCH 0/5] ivb fdi b/c fixes Daniel Vetter
2012-10-31 21:52 ` [PATCH 1/5] drm/i915: check whether the pch is the soulmate of the cpu Daniel Vetter
2012-10-31 21:52 ` [PATCH 2/5] drm/i915: drop unnecessary check from fdi_link_train code Daniel Vetter
@ 2012-10-31 21:52 ` Daniel Vetter
2012-11-01 8:15 ` [PATCH] drm/i915: CPT/PPT pch dp " Daniel Vetter
2012-10-31 21:52 ` [PATCH 4/5] drm/i915: implement WADP0ClockGatingDisable Daniel Vetter
2012-10-31 21:52 ` [PATCH 5/5] drm/i915: kill pch_init_clock_gating indirection Daniel Vetter
4 siblings, 1 reply; 17+ messages in thread
From: Daniel Vetter @ 2012-10-31 21:52 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter, Arthur Ranyan
We need to set the timing override chicken bit after fdi link training
has completed and before we enable the transcoder. We also have to
clear that bit again after disabling the pch transcoder.
See "Graphics BSpec: vol4g North Display Engine Registers [IVB],
Display Mode Set Sequence" and "Graphics BSpec: vol4h South Display
Engine Registers [CPT, PPT], South Display Engine Transcoder and FDI
Control, Transcoder Debug and DFT, TRANS_CHICKEN_2" bit 31:
"Workaround : Enable the override prior to enabling the transcoder.
Disable the override after disabling the transcoder."
While at it, use the _PIPE macro for the other TRANS_DP register.
v2: Keep the w/a as-is, but kill the original (but wrongly placed)
workaround introduced in
commit 3bcf603f6d5d18bd9d076dc280de71f48add4101
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Wed Jul 27 11:51:40 2011 -0700
drm/i915: apply timing generator bug workaround on CPT and PPT
and
commit d4270e57efe9e2536798c59e1ed2fd0a1e5cdfcf
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Tue Oct 11 10:43:02 2011 -0700
drm/i915: export a CPT mode set verification function
Note that this old code has unconditionally set the w/a, which might
explain why fdi link training sometimes silently fails, and especially
why the auto-train did not seem to work properly.
v3: Paulo Zanoni pointed out that this workaround is also required on
the LPT PCH. And Arthur Ranyan confirmed that this workaround is
requierd for all ports on the pch, not just DP: The important part
is that the bit is set whenever the pch transcoder is enabled, and
that it is _not_ set while the fdi link is trained. It is also
important that the pch transcoder is fully disabled, i.e. we have to
wait for bit 30 to clear before clearing the w/a bit.
Hence move to workaround into enable/disable_transcoder, where the pch
transcoder gets enabled/disabled.
v4: Whitespace changes dropped.
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Paulo Zanoni <przanoni@gmail.com>
Cc: Arthur Ranyan <arthur.j.runyan@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_display.c | 26 +++++++++++++++++---------
drivers/gpu/drm/i915/intel_pm.c | 4 ----
3 files changed, 20 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2dd880f..f1fe3a0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3806,7 +3806,8 @@
#define _TRANSA_CHICKEN2 0xf0064
#define _TRANSB_CHICKEN2 0xf1064
#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
-#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
+#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
+
#define SOUTH_CHICKEN1 0xc2000
#define FDIA_PHASE_SYNC_SHIFT_OVR 19
@@ -4064,7 +4065,7 @@
#define TRANS_DP_CTL_A 0xe0300
#define TRANS_DP_CTL_B 0xe1300
#define TRANS_DP_CTL_C 0xe2300
-#define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000)
+#define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
#define TRANS_DP_OUTPUT_ENABLE (1<<31)
#define TRANS_DP_PORT_SEL_B (0<<29)
#define TRANS_DP_PORT_SEL_C (1<<29)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 129059b..d27d683 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1673,8 +1673,7 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
- int reg;
- u32 val, pipeconf_val;
+ uint32_t reg, val, pipeconf_val;
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
/* PCH only available on ILK+ */
@@ -1693,6 +1692,14 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
return;
}
+
+ /* Workaround: Set the timing override bit before enabling the
+ * pch transcoder. */
+ reg = TRANS_CHICKEN2(pipe);
+ val = I915_READ(reg);
+ val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
+ I915_WRITE(reg, val);
+
reg = TRANSCONF(pipe);
val = I915_READ(reg);
pipeconf_val = I915_READ(PIPECONF(pipe));
@@ -1724,8 +1731,7 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
- int reg;
- u32 val;
+ uint32_t reg, val;
/* FDI relies on the transcoder */
assert_fdi_tx_disabled(dev_priv, pipe);
@@ -1741,6 +1747,12 @@ static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
/* wait for PCH transcoder off, transcoder state */
if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
DRM_ERROR("failed to disable transcoder %d\n", pipe);
+
+ /* Workaround: Clear the timing override chicken bit again. */
+ reg = TRANS_CHICKEN2(pipe);
+ val = I915_READ(reg);
+ val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
+ I915_WRITE(reg, val);
}
/**
@@ -3217,16 +3229,12 @@ prepare: /* separate function? */
void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
+ int dslreg = PIPEDSL(pipe);
u32 temp;
temp = I915_READ(dslreg);
udelay(500);
if (wait_for(I915_READ(dslreg) != temp, 5)) {
- /* Without this, mode sets may fail silently on FDI */
- I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
- udelay(250);
- I915_WRITE(tc2reg, 0);
if (wait_for(I915_READ(dslreg) != temp, 5))
DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a04b336..3469fbd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3786,7 +3786,6 @@ static void ibx_init_clock_gating(struct drm_device *dev)
static void cpt_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- int pipe;
/*
* On Ibex Peak and Cougar Point, we need to disable clock
@@ -3796,9 +3795,6 @@ static void cpt_init_clock_gating(struct drm_device *dev)
I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
DPLS_EDP_PPS_FIX_DIS);
- /* Without this, mode sets may fail silently on FDI */
- for_each_pipe(pipe)
- I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
}
void intel_init_clock_gating(struct drm_device *dev)
--
1.7.11.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH] drm/i915: CPT/PPT pch dp transcoder workaround
2012-10-31 21:52 ` [PATCH 3/5] drm/i915: CPT/PPT pch transcoder workaround Daniel Vetter
@ 2012-11-01 8:15 ` Daniel Vetter
2012-11-01 14:37 ` Jesse Barnes
2012-11-01 16:12 ` Paulo Zanoni
0 siblings, 2 replies; 17+ messages in thread
From: Daniel Vetter @ 2012-11-01 8:15 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter, Arthur Ranyan
We need to set the timing override chicken bit after fdi link training
has completed and before we enable the dp transcoder. We also have to
clear that bit again after disabling the pch dp transcoder.
See "Graphics BSpec: vol4g North Display Engine Registers [IVB],
Display Mode Set Sequence" and "Graphics BSpec: vol4h South Display
Engine Registers [CPT, PPT], South Display Engine Transcoder and FDI
Control, Transcoder Debug and DFT, TRANS_CHICKEN_2" bit 31:
"Workaround : Enable the override prior to enabling the transcoder.
Disable the override after disabling the transcoder."
While at it, use the _PIPE macro for the other TRANS_DP register.
v2: Keep the w/a as-is, but kill the original (but wrongly placed)
workaround introduced in
commit 3bcf603f6d5d18bd9d076dc280de71f48add4101
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Wed Jul 27 11:51:40 2011 -0700
drm/i915: apply timing generator bug workaround on CPT and PPT
and
commit d4270e57efe9e2536798c59e1ed2fd0a1e5cdfcf
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Tue Oct 11 10:43:02 2011 -0700
drm/i915: export a CPT mode set verification function
Note that this old code has unconditionally set the w/a, which might
explain why fdi link training sometimes silently fails, and especially
why the auto-train did not seem to work properly.
v3: Paulo Zanoni pointed out that this workaround is also required on
the LPT PCH. And Arthur Ranyan confirmed that this workaround is
requierd for all ports on the pch, not just DP: The important part
is that the bit is set whenever the pch transcoder is enabled, and
that it is _not_ set while the fdi link is trained. It is also
important that the pch transcoder is fully disabled, i.e. we have to
wait for bit 30 to clear before clearing the w/a bit.
Hence move to workaround into enable/disable_transcoder, where the pch
transcoder gets enabled/disabled.
v4: Whitespace changes dropped.
v5: Don't run the w/a on IBX, we only need it on CPT/PPT and LPT.
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Paulo Zanoni <przanoni@gmail.com>
Cc: Arthur Ranyan <arthur.j.runyan@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_display.c | 32 +++++++++++++++++++++++---------
drivers/gpu/drm/i915/intel_pm.c | 4 ----
3 files changed, 26 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2dd880f..f1fe3a0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3806,7 +3806,8 @@
#define _TRANSA_CHICKEN2 0xf0064
#define _TRANSB_CHICKEN2 0xf1064
#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
-#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
+#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
+
#define SOUTH_CHICKEN1 0xc2000
#define FDIA_PHASE_SYNC_SHIFT_OVR 19
@@ -4064,7 +4065,7 @@
#define TRANS_DP_CTL_A 0xe0300
#define TRANS_DP_CTL_B 0xe1300
#define TRANS_DP_CTL_C 0xe2300
-#define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000)
+#define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
#define TRANS_DP_OUTPUT_ENABLE (1<<31)
#define TRANS_DP_PORT_SEL_B (0<<29)
#define TRANS_DP_PORT_SEL_C (1<<29)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 129059b..675079a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1673,9 +1673,9 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
- int reg;
- u32 val, pipeconf_val;
+ struct drm_device *dev = dev_priv->dev;
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+ uint32_t reg, val, pipeconf_val;
/* PCH only available on ILK+ */
BUG_ON(dev_priv->info->gen < 5);
@@ -1693,6 +1693,16 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
return;
}
+
+ if (!HAS_PCH_IBX(dev)) {
+ /* Workaround: Set the timing override bit before enabling the
+ * pch transcoder. */
+ reg = TRANS_CHICKEN2(pipe);
+ val = I915_READ(reg);
+ val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
+ I915_WRITE(reg, val);
+ }
+
reg = TRANSCONF(pipe);
val = I915_READ(reg);
pipeconf_val = I915_READ(PIPECONF(pipe));
@@ -1724,8 +1734,8 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
- int reg;
- u32 val;
+ struct drm_device *dev = dev_priv->dev;
+ uint32_t reg, val;
/* FDI relies on the transcoder */
assert_fdi_tx_disabled(dev_priv, pipe);
@@ -1741,6 +1751,14 @@ static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
/* wait for PCH transcoder off, transcoder state */
if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
DRM_ERROR("failed to disable transcoder %d\n", pipe);
+
+ if (!HAS_PCH_IBX(dev)) {
+ /* Workaround: Clear the timing override chicken bit again. */
+ reg = TRANS_CHICKEN2(pipe);
+ val = I915_READ(reg);
+ val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
+ I915_WRITE(reg, val);
+ }
}
/**
@@ -3217,16 +3235,12 @@ prepare: /* separate function? */
void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
+ int dslreg = PIPEDSL(pipe);
u32 temp;
temp = I915_READ(dslreg);
udelay(500);
if (wait_for(I915_READ(dslreg) != temp, 5)) {
- /* Without this, mode sets may fail silently on FDI */
- I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
- udelay(250);
- I915_WRITE(tc2reg, 0);
if (wait_for(I915_READ(dslreg) != temp, 5))
DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a04b336..3469fbd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3786,7 +3786,6 @@ static void ibx_init_clock_gating(struct drm_device *dev)
static void cpt_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- int pipe;
/*
* On Ibex Peak and Cougar Point, we need to disable clock
@@ -3796,9 +3795,6 @@ static void cpt_init_clock_gating(struct drm_device *dev)
I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
DPLS_EDP_PPS_FIX_DIS);
- /* Without this, mode sets may fail silently on FDI */
- for_each_pipe(pipe)
- I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
}
void intel_init_clock_gating(struct drm_device *dev)
--
1.7.11.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH] drm/i915: CPT/PPT pch dp transcoder workaround
2012-11-01 8:15 ` [PATCH] drm/i915: CPT/PPT pch dp " Daniel Vetter
@ 2012-11-01 14:37 ` Jesse Barnes
2012-11-01 15:33 ` Daniel Vetter
2012-11-01 16:12 ` Paulo Zanoni
1 sibling, 1 reply; 17+ messages in thread
From: Jesse Barnes @ 2012-11-01 14:37 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development, Arthur Ranyan
On Thu, 1 Nov 2012 09:15:30 +0100
Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> We need to set the timing override chicken bit after fdi link training
> has completed and before we enable the dp transcoder. We also have to
> clear that bit again after disabling the pch dp transcoder.
>
> See "Graphics BSpec: vol4g North Display Engine Registers [IVB],
> Display Mode Set Sequence" and "Graphics BSpec: vol4h South Display
> Engine Registers [CPT, PPT], South Display Engine Transcoder and FDI
> Control, Transcoder Debug and DFT, TRANS_CHICKEN_2" bit 31:
>
> "Workaround : Enable the override prior to enabling the transcoder.
> Disable the override after disabling the transcoder."
>
> While at it, use the _PIPE macro for the other TRANS_DP register.
>
> v2: Keep the w/a as-is, but kill the original (but wrongly placed)
> workaround introduced in
>
> commit 3bcf603f6d5d18bd9d076dc280de71f48add4101
> Author: Jesse Barnes <jbarnes@virtuousgeek.org>
> Date: Wed Jul 27 11:51:40 2011 -0700
>
> drm/i915: apply timing generator bug workaround on CPT and PPT
>
> and
>
> commit d4270e57efe9e2536798c59e1ed2fd0a1e5cdfcf
> Author: Jesse Barnes <jbarnes@virtuousgeek.org>
> Date: Tue Oct 11 10:43:02 2011 -0700
>
> drm/i915: export a CPT mode set verification function
>
> Note that this old code has unconditionally set the w/a, which might
> explain why fdi link training sometimes silently fails, and especially
> why the auto-train did not seem to work properly.
>
> v3: Paulo Zanoni pointed out that this workaround is also required on
> the LPT PCH. And Arthur Ranyan confirmed that this workaround is
> requierd for all ports on the pch, not just DP: The important part
> is that the bit is set whenever the pch transcoder is enabled, and
> that it is _not_ set while the fdi link is trained. It is also
> important that the pch transcoder is fully disabled, i.e. we have to
> wait for bit 30 to clear before clearing the w/a bit.
>
> Hence move to workaround into enable/disable_transcoder, where the pch
> transcoder gets enabled/disabled.
>
> v4: Whitespace changes dropped.
>
> v5: Don't run the w/a on IBX, we only need it on CPT/PPT and LPT.
>
> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
> Cc: Paulo Zanoni <przanoni@gmail.com>
> Cc: Arthur Ranyan <arthur.j.runyan@intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++--
> drivers/gpu/drm/i915/intel_display.c | 32 +++++++++++++++++++++++---------
> drivers/gpu/drm/i915/intel_pm.c | 4 ----
> 3 files changed, 26 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2dd880f..f1fe3a0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3806,7 +3806,8 @@
> #define _TRANSA_CHICKEN2 0xf0064
> #define _TRANSB_CHICKEN2 0xf1064
> #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> -#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
> +#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
> +
>
> #define SOUTH_CHICKEN1 0xc2000
> #define FDIA_PHASE_SYNC_SHIFT_OVR 19
> @@ -4064,7 +4065,7 @@
> #define TRANS_DP_CTL_A 0xe0300
> #define TRANS_DP_CTL_B 0xe1300
> #define TRANS_DP_CTL_C 0xe2300
> -#define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000)
> +#define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
> #define TRANS_DP_OUTPUT_ENABLE (1<<31)
> #define TRANS_DP_PORT_SEL_B (0<<29)
> #define TRANS_DP_PORT_SEL_C (1<<29)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 129059b..675079a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1673,9 +1673,9 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
> static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> {
> - int reg;
> - u32 val, pipeconf_val;
> + struct drm_device *dev = dev_priv->dev;
> struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
> + uint32_t reg, val, pipeconf_val;
>
> /* PCH only available on ILK+ */
> BUG_ON(dev_priv->info->gen < 5);
> @@ -1693,6 +1693,16 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
> DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
> return;
> }
> +
> + if (!HAS_PCH_IBX(dev)) {
> + /* Workaround: Set the timing override bit before enabling the
> + * pch transcoder. */
> + reg = TRANS_CHICKEN2(pipe);
> + val = I915_READ(reg);
> + val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> + I915_WRITE(reg, val);
> + }
I'd like this better if it were HAS_PCH_CPT; we use that as a synonym
for PPT elsehwere, and it shouldn't apply to LPT right? I see LPT has
the bit, but I don't know if it's needed (the changelong and summary
are misleading if so).
> +
> reg = TRANSCONF(pipe);
> val = I915_READ(reg);
> pipeconf_val = I915_READ(PIPECONF(pipe));
> @@ -1724,8 +1734,8 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
> static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> {
> - int reg;
> - u32 val;
> + struct drm_device *dev = dev_priv->dev;
> + uint32_t reg, val;
>
> /* FDI relies on the transcoder */
> assert_fdi_tx_disabled(dev_priv, pipe);
> @@ -1741,6 +1751,14 @@ static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
> /* wait for PCH transcoder off, transcoder state */
> if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
> DRM_ERROR("failed to disable transcoder %d\n", pipe);
> +
> + if (!HAS_PCH_IBX(dev)) {
> + /* Workaround: Clear the timing override chicken bit again. */
> + reg = TRANS_CHICKEN2(pipe);
> + val = I915_READ(reg);
> + val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
> + I915_WRITE(reg, val);
> + }
> }
>
> /**
> @@ -3217,16 +3235,12 @@ prepare: /* separate function? */
> void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
> + int dslreg = PIPEDSL(pipe);
> u32 temp;
>
> temp = I915_READ(dslreg);
> udelay(500);
> if (wait_for(I915_READ(dslreg) != temp, 5)) {
> - /* Without this, mode sets may fail silently on FDI */
> - I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
> - udelay(250);
> - I915_WRITE(tc2reg, 0);
> if (wait_for(I915_READ(dslreg) != temp, 5))
> DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
> }
Note this was an older version of the workaround. "wrongly placed"
indeed.
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH] drm/i915: CPT/PPT pch dp transcoder workaround
2012-11-01 14:37 ` Jesse Barnes
@ 2012-11-01 15:33 ` Daniel Vetter
2012-11-01 15:35 ` Jesse Barnes
0 siblings, 1 reply; 17+ messages in thread
From: Daniel Vetter @ 2012-11-01 15:33 UTC (permalink / raw)
To: Jesse Barnes; +Cc: Daniel Vetter, Intel Graphics Development, Arthur Ranyan
On Thu, Nov 01, 2012 at 07:37:36AM -0700, Jesse Barnes wrote:
> > v3: Paulo Zanoni pointed out that this workaround is also required on
> > the LPT PCH. And Arthur Ranyan confirmed that this workaround is
> > requierd for all ports on the pch, not just DP: The important part
> > is that the bit is set whenever the pch transcoder is enabled, and
> > that it is _not_ set while the fdi link is trained. It is also
> > important that the pch transcoder is fully disabled, i.e. we have to
> > wait for bit 30 to clear before clearing the w/a bit.
See above: "Paulo Zanoni pointed out that this workaround is also required
on the LPT PCH".
> > + if (!HAS_PCH_IBX(dev)) {
> > + /* Workaround: Set the timing override bit before enabling the
> > + * pch transcoder. */
> > + reg = TRANS_CHICKEN2(pipe);
> > + val = I915_READ(reg);
> > + val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> > + I915_WRITE(reg, val);
> > + }
>
> I'd like this better if it were HAS_PCH_CPT; we use that as a synonym
> for PPT elsehwere, and it shouldn't apply to LPT right? I see LPT has
> the bit, but I don't know if it's needed (the changelong and summary
> are misleading if so).
Paulo's vga patch bomb will split this up, so we can use HAS_PCH_CPT
instead of !IBX. But since I've written this patch against dinq without
paulo's patches, hence HAS_CPT would be wrong. So:
What colour would please you most, Sir?
Cheers, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH] drm/i915: CPT/PPT pch dp transcoder workaround
2012-11-01 15:33 ` Daniel Vetter
@ 2012-11-01 15:35 ` Jesse Barnes
0 siblings, 0 replies; 17+ messages in thread
From: Jesse Barnes @ 2012-11-01 15:35 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Daniel Vetter, Intel Graphics Development, Arthur Ranyan
On Thu, 1 Nov 2012 16:33:45 +0100
Daniel Vetter <daniel@ffwll.ch> wrote:
> On Thu, Nov 01, 2012 at 07:37:36AM -0700, Jesse Barnes wrote:
> > > v3: Paulo Zanoni pointed out that this workaround is also required on
> > > the LPT PCH. And Arthur Ranyan confirmed that this workaround is
> > > requierd for all ports on the pch, not just DP: The important part
> > > is that the bit is set whenever the pch transcoder is enabled, and
> > > that it is _not_ set while the fdi link is trained. It is also
> > > important that the pch transcoder is fully disabled, i.e. we have to
> > > wait for bit 30 to clear before clearing the w/a bit.
>
> See above: "Paulo Zanoni pointed out that this workaround is also required
> on the LPT PCH".
>
> > > + if (!HAS_PCH_IBX(dev)) {
> > > + /* Workaround: Set the timing override bit before enabling the
> > > + * pch transcoder. */
> > > + reg = TRANS_CHICKEN2(pipe);
> > > + val = I915_READ(reg);
> > > + val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> > > + I915_WRITE(reg, val);
> > > + }
> >
> > I'd like this better if it were HAS_PCH_CPT; we use that as a synonym
> > for PPT elsehwere, and it shouldn't apply to LPT right? I see LPT has
> > the bit, but I don't know if it's needed (the changelong and summary
> > are misleading if so).
>
> Paulo's vga patch bomb will split this up, so we can use HAS_PCH_CPT
> instead of !IBX. But since I've written this patch against dinq without
> paulo's patches, hence HAS_CPT would be wrong. So:
>
> What colour would please you most, Sir?
Just fix the changelog summary then!
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH] drm/i915: CPT/PPT pch dp transcoder workaround
2012-11-01 8:15 ` [PATCH] drm/i915: CPT/PPT pch dp " Daniel Vetter
2012-11-01 14:37 ` Jesse Barnes
@ 2012-11-01 16:12 ` Paulo Zanoni
1 sibling, 0 replies; 17+ messages in thread
From: Paulo Zanoni @ 2012-11-01 16:12 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development, Arthur Ranyan
Hi
2012/11/1 Daniel Vetter <daniel.vetter@ffwll.ch>:
> We need to set the timing override chicken bit after fdi link training
> has completed and before we enable the dp transcoder. We also have to
> clear that bit again after disabling the pch dp transcoder.
>
> See "Graphics BSpec: vol4g North Display Engine Registers [IVB],
> Display Mode Set Sequence" and "Graphics BSpec: vol4h South Display
> Engine Registers [CPT, PPT], South Display Engine Transcoder and FDI
> Control, Transcoder Debug and DFT, TRANS_CHICKEN_2" bit 31:
>
> "Workaround : Enable the override prior to enabling the transcoder.
> Disable the override after disabling the transcoder."
>
> While at it, use the _PIPE macro for the other TRANS_DP register.
>
> v2: Keep the w/a as-is, but kill the original (but wrongly placed)
> workaround introduced in
>
> commit 3bcf603f6d5d18bd9d076dc280de71f48add4101
> Author: Jesse Barnes <jbarnes@virtuousgeek.org>
> Date: Wed Jul 27 11:51:40 2011 -0700
>
> drm/i915: apply timing generator bug workaround on CPT and PPT
>
> and
>
> commit d4270e57efe9e2536798c59e1ed2fd0a1e5cdfcf
> Author: Jesse Barnes <jbarnes@virtuousgeek.org>
> Date: Tue Oct 11 10:43:02 2011 -0700
>
> drm/i915: export a CPT mode set verification function
>
> Note that this old code has unconditionally set the w/a, which might
> explain why fdi link training sometimes silently fails, and especially
> why the auto-train did not seem to work properly.
>
> v3: Paulo Zanoni pointed out that this workaround is also required on
> the LPT PCH. And Arthur Ranyan confirmed that this workaround is
> requierd for all ports on the pch, not just DP: The important part
s/requierd/required/
> is that the bit is set whenever the pch transcoder is enabled, and
> that it is _not_ set while the fdi link is trained. It is also
> important that the pch transcoder is fully disabled, i.e. we have to
> wait for bit 30 to clear before clearing the w/a bit.
>
> Hence move to workaround into enable/disable_transcoder, where the pch
> transcoder gets enabled/disabled.
>
> v4: Whitespace changes dropped.
>
> v5: Don't run the w/a on IBX, we only need it on CPT/PPT and LPT.
>
> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
> Cc: Paulo Zanoni <przanoni@gmail.com>
> Cc: Arthur Ranyan <arthur.j.runyan@intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
For me, it doesn't matter if you do !HAS_PCH_IBX or HAS_PCH_CPT, I
will have to fork the functions for LPT anyway, so I will fix that,
independently of what you do here.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++--
> drivers/gpu/drm/i915/intel_display.c | 32 +++++++++++++++++++++++---------
> drivers/gpu/drm/i915/intel_pm.c | 4 ----
> 3 files changed, 26 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2dd880f..f1fe3a0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3806,7 +3806,8 @@
> #define _TRANSA_CHICKEN2 0xf0064
> #define _TRANSB_CHICKEN2 0xf1064
> #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> -#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
> +#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
> +
>
> #define SOUTH_CHICKEN1 0xc2000
> #define FDIA_PHASE_SYNC_SHIFT_OVR 19
> @@ -4064,7 +4065,7 @@
> #define TRANS_DP_CTL_A 0xe0300
> #define TRANS_DP_CTL_B 0xe1300
> #define TRANS_DP_CTL_C 0xe2300
> -#define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000)
> +#define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
> #define TRANS_DP_OUTPUT_ENABLE (1<<31)
> #define TRANS_DP_PORT_SEL_B (0<<29)
> #define TRANS_DP_PORT_SEL_C (1<<29)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 129059b..675079a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1673,9 +1673,9 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
> static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> {
> - int reg;
> - u32 val, pipeconf_val;
> + struct drm_device *dev = dev_priv->dev;
> struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
> + uint32_t reg, val, pipeconf_val;
>
> /* PCH only available on ILK+ */
> BUG_ON(dev_priv->info->gen < 5);
> @@ -1693,6 +1693,16 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
> DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
> return;
> }
> +
> + if (!HAS_PCH_IBX(dev)) {
> + /* Workaround: Set the timing override bit before enabling the
> + * pch transcoder. */
> + reg = TRANS_CHICKEN2(pipe);
> + val = I915_READ(reg);
> + val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> + I915_WRITE(reg, val);
> + }
> +
> reg = TRANSCONF(pipe);
> val = I915_READ(reg);
> pipeconf_val = I915_READ(PIPECONF(pipe));
> @@ -1724,8 +1734,8 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
> static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> {
> - int reg;
> - u32 val;
> + struct drm_device *dev = dev_priv->dev;
> + uint32_t reg, val;
>
> /* FDI relies on the transcoder */
> assert_fdi_tx_disabled(dev_priv, pipe);
> @@ -1741,6 +1751,14 @@ static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
> /* wait for PCH transcoder off, transcoder state */
> if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
> DRM_ERROR("failed to disable transcoder %d\n", pipe);
> +
> + if (!HAS_PCH_IBX(dev)) {
> + /* Workaround: Clear the timing override chicken bit again. */
> + reg = TRANS_CHICKEN2(pipe);
> + val = I915_READ(reg);
> + val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
> + I915_WRITE(reg, val);
> + }
> }
>
> /**
> @@ -3217,16 +3235,12 @@ prepare: /* separate function? */
> void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
> + int dslreg = PIPEDSL(pipe);
> u32 temp;
>
> temp = I915_READ(dslreg);
> udelay(500);
> if (wait_for(I915_READ(dslreg) != temp, 5)) {
> - /* Without this, mode sets may fail silently on FDI */
> - I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
> - udelay(250);
> - I915_WRITE(tc2reg, 0);
> if (wait_for(I915_READ(dslreg) != temp, 5))
> DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
> }
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a04b336..3469fbd 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3786,7 +3786,6 @@ static void ibx_init_clock_gating(struct drm_device *dev)
> static void cpt_init_clock_gating(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - int pipe;
>
> /*
> * On Ibex Peak and Cougar Point, we need to disable clock
> @@ -3796,9 +3795,6 @@ static void cpt_init_clock_gating(struct drm_device *dev)
> I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
> I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
> DPLS_EDP_PPS_FIX_DIS);
> - /* Without this, mode sets may fail silently on FDI */
> - for_each_pipe(pipe)
> - I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
> }
>
> void intel_init_clock_gating(struct drm_device *dev)
> --
> 1.7.11.4
>
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 4/5] drm/i915: implement WADP0ClockGatingDisable
2012-10-31 21:52 [PATCH 0/5] ivb fdi b/c fixes Daniel Vetter
` (2 preceding siblings ...)
2012-10-31 21:52 ` [PATCH 3/5] drm/i915: CPT/PPT pch transcoder workaround Daniel Vetter
@ 2012-10-31 21:52 ` Daniel Vetter
2012-11-01 16:18 ` Paulo Zanoni
2012-10-31 21:52 ` [PATCH 5/5] drm/i915: kill pch_init_clock_gating indirection Daniel Vetter
4 siblings, 1 reply; 17+ messages in thread
From: Daniel Vetter @ 2012-10-31 21:52 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
Found in Bspec vol4h South Display Engine Registers [CPT, PPT],
section "5.3.1 TRANS_CHICKEN_1—Transcoder Chicken Bits 1"
v2: Make it compile.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f1fe3a0..14851ab 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3803,6 +3803,10 @@
#define TRANS_6BPC (2<<5)
#define TRANS_12BPC (3<<5)
+#define _TRANSA_CHICKEN1 0xf0060
+#define _TRANSB_CHICKEN1 0xf1060
+#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
+#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
#define _TRANSA_CHICKEN2 0xf0064
#define _TRANSB_CHICKEN2 0xf1064
#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3469fbd..a0e8f51 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3786,6 +3786,7 @@ static void ibx_init_clock_gating(struct drm_device *dev)
static void cpt_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ int pipe;
/*
* On Ibex Peak and Cougar Point, we need to disable clock
@@ -3795,6 +3796,11 @@ static void cpt_init_clock_gating(struct drm_device *dev)
I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
DPLS_EDP_PPS_FIX_DIS);
+ /* WADP0ClockGatingDisable */
+ for_each_pipe(pipe) {
+ I915_WRITE(TRANS_CHICKEN1(pipe),
+ TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
+ }
}
void intel_init_clock_gating(struct drm_device *dev)
--
1.7.11.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 4/5] drm/i915: implement WADP0ClockGatingDisable
2012-10-31 21:52 ` [PATCH 4/5] drm/i915: implement WADP0ClockGatingDisable Daniel Vetter
@ 2012-11-01 16:18 ` Paulo Zanoni
0 siblings, 0 replies; 17+ messages in thread
From: Paulo Zanoni @ 2012-11-01 16:18 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
Hi
2012/10/31 Daniel Vetter <daniel.vetter@ffwll.ch>:
> Found in Bspec vol4h South Display Engine Registers [CPT, PPT],
> section "5.3.1 TRANS_CHICKEN_1—Transcoder Chicken Bits 1"
>
> v2: Make it compile.
>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
R-B still applies... When I'm reviewing your patches I usually assume
they compile, so I didn't really try to compile this one :)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f1fe3a0..14851ab 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3803,6 +3803,10 @@
> #define TRANS_6BPC (2<<5)
> #define TRANS_12BPC (3<<5)
>
> +#define _TRANSA_CHICKEN1 0xf0060
> +#define _TRANSB_CHICKEN1 0xf1060
> +#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
> +#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
> #define _TRANSA_CHICKEN2 0xf0064
> #define _TRANSB_CHICKEN2 0xf1064
> #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3469fbd..a0e8f51 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3786,6 +3786,7 @@ static void ibx_init_clock_gating(struct drm_device *dev)
> static void cpt_init_clock_gating(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> + int pipe;
>
> /*
> * On Ibex Peak and Cougar Point, we need to disable clock
> @@ -3795,6 +3796,11 @@ static void cpt_init_clock_gating(struct drm_device *dev)
> I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
> I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
> DPLS_EDP_PPS_FIX_DIS);
> + /* WADP0ClockGatingDisable */
> + for_each_pipe(pipe) {
> + I915_WRITE(TRANS_CHICKEN1(pipe),
> + TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
> + }
> }
>
> void intel_init_clock_gating(struct drm_device *dev)
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 5/5] drm/i915: kill pch_init_clock_gating indirection
2012-10-31 21:52 [PATCH 0/5] ivb fdi b/c fixes Daniel Vetter
` (3 preceding siblings ...)
2012-10-31 21:52 ` [PATCH 4/5] drm/i915: implement WADP0ClockGatingDisable Daniel Vetter
@ 2012-10-31 21:52 ` Daniel Vetter
2012-11-01 16:35 ` Paulo Zanoni
4 siblings, 1 reply; 17+ messages in thread
From: Daniel Vetter @ 2012-10-31 21:52 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
Now that we no longer pretend to have flexibility in matching any
north display block with any pch, we can ditch this.
v2: Fix the embarassing rebase fail that Paulo Zanoni spotted.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 78 ++++++++++++++++++++---------------------
2 files changed, 38 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index faf57d6..7186a41a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -270,7 +270,6 @@ struct drm_i915_display_funcs {
struct drm_crtc *crtc);
void (*fdi_link_train)(struct drm_crtc *crtc);
void (*init_clock_gating)(struct drm_device *dev);
- void (*init_pch_clock_gating)(struct drm_device *dev);
int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a0e8f51..058e52e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3324,6 +3324,18 @@ void intel_enable_gt_powersave(struct drm_device *dev)
}
}
+static void ibx_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ /*
+ * On Ibex Peak and Cougar Point, we need to disable clock
+ * gating for the panel power sequencer or it will fail to
+ * start up when no ports are active.
+ */
+ I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
+}
+
static void ironlake_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3382,6 +3394,28 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
I915_WRITE(_3D_CHICKEN2,
_3D_CHICKEN2_WM_READ_PIPELINED << 16 |
_3D_CHICKEN2_WM_READ_PIPELINED);
+
+ ibx_init_clock_gating(dev);
+}
+
+static void cpt_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int pipe;
+
+ /*
+ * On Ibex Peak and Cougar Point, we need to disable clock
+ * gating for the panel power sequencer or it will fail to
+ * start up when no ports are active.
+ */
+ I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
+ I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
+ DPLS_EDP_PPS_FIX_DIS);
+ /* WADP0ClockGatingDisable */
+ for_each_pipe(pipe) {
+ I915_WRITE(TRANS_CHICKEN1(pipe),
+ TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
+ }
}
static void gen6_init_clock_gating(struct drm_device *dev)
@@ -3464,6 +3498,8 @@ static void gen6_init_clock_gating(struct drm_device *dev)
* platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
+
+ cpt_init_clock_gating(dev);
}
static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
@@ -3608,6 +3644,8 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
snpcr &= ~GEN6_MBC_SNPCR_MASK;
snpcr |= GEN6_MBC_SNPCR_MED;
I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
+
+ cpt_init_clock_gating(dev);
}
static void valleyview_init_clock_gating(struct drm_device *dev)
@@ -3771,46 +3809,11 @@ static void i830_init_clock_gating(struct drm_device *dev)
I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
}
-static void ibx_init_clock_gating(struct drm_device *dev)
-{
- struct drm_i915_private *dev_priv = dev->dev_private;
-
- /*
- * On Ibex Peak and Cougar Point, we need to disable clock
- * gating for the panel power sequencer or it will fail to
- * start up when no ports are active.
- */
- I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
-}
-
-static void cpt_init_clock_gating(struct drm_device *dev)
-{
- struct drm_i915_private *dev_priv = dev->dev_private;
- int pipe;
-
- /*
- * On Ibex Peak and Cougar Point, we need to disable clock
- * gating for the panel power sequencer or it will fail to
- * start up when no ports are active.
- */
- I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
- I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
- DPLS_EDP_PPS_FIX_DIS);
- /* WADP0ClockGatingDisable */
- for_each_pipe(pipe) {
- I915_WRITE(TRANS_CHICKEN1(pipe),
- TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
- }
-}
-
void intel_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
dev_priv->display.init_clock_gating(dev);
-
- if (dev_priv->display.init_pch_clock_gating)
- dev_priv->display.init_pch_clock_gating(dev);
}
/* Set up chip specific power management-related functions */
@@ -3843,11 +3846,6 @@ void intel_init_pm(struct drm_device *dev)
/* For FIFO watermark updates */
if (HAS_PCH_SPLIT(dev)) {
- if (HAS_PCH_IBX(dev))
- dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
- else if (HAS_PCH_CPT(dev))
- dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
-
if (IS_GEN5(dev)) {
if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
dev_priv->display.update_wm = ironlake_update_wm;
--
1.7.11.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 5/5] drm/i915: kill pch_init_clock_gating indirection
2012-10-31 21:52 ` [PATCH 5/5] drm/i915: kill pch_init_clock_gating indirection Daniel Vetter
@ 2012-11-01 16:35 ` Paulo Zanoni
2012-11-01 22:03 ` Daniel Vetter
0 siblings, 1 reply; 17+ messages in thread
From: Paulo Zanoni @ 2012-11-01 16:35 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
Hi
2012/10/31 Daniel Vetter <daniel.vetter@ffwll.ch>:
> Now that we no longer pretend to have flexibility in matching any
> north display block with any pch, we can ditch this.
>
> v2: Fix the embarassing rebase fail that Paulo Zanoni spotted.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 -
> drivers/gpu/drm/i915/intel_pm.c | 78 ++++++++++++++++++++---------------------
> 2 files changed, 38 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index faf57d6..7186a41a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -270,7 +270,6 @@ struct drm_i915_display_funcs {
> struct drm_crtc *crtc);
> void (*fdi_link_train)(struct drm_crtc *crtc);
> void (*init_clock_gating)(struct drm_device *dev);
> - void (*init_pch_clock_gating)(struct drm_device *dev);
> int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
> struct drm_framebuffer *fb,
> struct drm_i915_gem_object *obj);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a0e8f51..058e52e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3324,6 +3324,18 @@ void intel_enable_gt_powersave(struct drm_device *dev)
> }
> }
>
> +static void ibx_init_clock_gating(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + /*
> + * On Ibex Peak and Cougar Point, we need to disable clock
> + * gating for the panel power sequencer or it will fail to
> + * start up when no ports are active.
> + */
> + I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
> +}
> +
> static void ironlake_init_clock_gating(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3382,6 +3394,28 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
> I915_WRITE(_3D_CHICKEN2,
> _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
> _3D_CHICKEN2_WM_READ_PIPELINED);
> +
> + ibx_init_clock_gating(dev);
> +}
> +
> +static void cpt_init_clock_gating(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + int pipe;
> +
> + /*
> + * On Ibex Peak and Cougar Point, we need to disable clock
> + * gating for the panel power sequencer or it will fail to
> + * start up when no ports are active.
> + */
> + I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
> + I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
> + DPLS_EDP_PPS_FIX_DIS);
> + /* WADP0ClockGatingDisable */
> + for_each_pipe(pipe) {
> + I915_WRITE(TRANS_CHICKEN1(pipe),
> + TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
> + }
> }
>
> static void gen6_init_clock_gating(struct drm_device *dev)
> @@ -3464,6 +3498,8 @@ static void gen6_init_clock_gating(struct drm_device *dev)
> * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
> I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
> I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
> +
> + cpt_init_clock_gating(dev);
> }
>
> static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
> @@ -3608,6 +3644,8 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> snpcr &= ~GEN6_MBC_SNPCR_MASK;
> snpcr |= GEN6_MBC_SNPCR_MED;
> I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
> +
> + cpt_init_clock_gating(dev);
> }
>
> static void valleyview_init_clock_gating(struct drm_device *dev)
> @@ -3771,46 +3809,11 @@ static void i830_init_clock_gating(struct drm_device *dev)
> I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
> }
>
> -static void ibx_init_clock_gating(struct drm_device *dev)
> -{
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
> - /*
> - * On Ibex Peak and Cougar Point, we need to disable clock
> - * gating for the panel power sequencer or it will fail to
> - * start up when no ports are active.
> - */
> - I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
> -}
> -
> -static void cpt_init_clock_gating(struct drm_device *dev)
> -{
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - int pipe;
> -
> - /*
> - * On Ibex Peak and Cougar Point, we need to disable clock
> - * gating for the panel power sequencer or it will fail to
> - * start up when no ports are active.
> - */
> - I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
> - I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
> - DPLS_EDP_PPS_FIX_DIS);
> - /* WADP0ClockGatingDisable */
> - for_each_pipe(pipe) {
> - I915_WRITE(TRANS_CHICKEN1(pipe),
> - TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
> - }
> -}
> -
> void intel_init_clock_gating(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> dev_priv->display.init_clock_gating(dev);
> -
> - if (dev_priv->display.init_pch_clock_gating)
> - dev_priv->display.init_pch_clock_gating(dev);
> }
>
> /* Set up chip specific power management-related functions */
> @@ -3843,11 +3846,6 @@ void intel_init_pm(struct drm_device *dev)
>
> /* For FIFO watermark updates */
> if (HAS_PCH_SPLIT(dev)) {
> - if (HAS_PCH_IBX(dev))
> - dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
> - else if (HAS_PCH_CPT(dev))
> - dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
> -
> if (IS_GEN5(dev)) {
> if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
> dev_priv->display.update_wm = ironlake_update_wm;
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 5/5] drm/i915: kill pch_init_clock_gating indirection
2012-11-01 16:35 ` Paulo Zanoni
@ 2012-11-01 22:03 ` Daniel Vetter
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Vetter @ 2012-11-01 22:03 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: Daniel Vetter, Intel Graphics Development
On Thu, Nov 01, 2012 at 02:35:13PM -0200, Paulo Zanoni wrote:
> Hi
>
> 2012/10/31 Daniel Vetter <daniel.vetter@ffwll.ch>:
> > Now that we no longer pretend to have flexibility in matching any
> > north display block with any pch, we can ditch this.
> >
> > v2: Fix the embarassing rebase fail that Paulo Zanoni spotted.
> >
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Series merged to dinq, thanks for the review.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 5/5] drm/i915: kill pch_init_clock_gating indirection
2012-10-29 22:23 [PATCH 1/5] drm/i915: check whether the pch is the soulmate of the cpu Daniel Vetter
@ 2012-10-29 22:23 ` Daniel Vetter
2012-10-31 17:52 ` Paulo Zanoni
0 siblings, 1 reply; 17+ messages in thread
From: Daniel Vetter @ 2012-10-29 22:23 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
Now that we no longer pretend to have flexibility in matching any
north display block with any pch, we can ditch this.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 71 +++++++++++++++++++----------------------
2 files changed, 32 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index faf57d6..7186a41a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -270,7 +270,6 @@ struct drm_i915_display_funcs {
struct drm_crtc *crtc);
void (*fdi_link_train)(struct drm_crtc *crtc);
void (*init_clock_gating)(struct drm_device *dev);
- void (*init_pch_clock_gating)(struct drm_device *dev);
int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1d96c1f..919c1f4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3324,6 +3324,18 @@ void intel_enable_gt_powersave(struct drm_device *dev)
}
}
+static void ibx_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ /*
+ * On Ibex Peak and Cougar Point, we need to disable clock
+ * gating for the panel power sequencer or it will fail to
+ * start up when no ports are active.
+ */
+ I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
+}
+
static void ironlake_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3382,6 +3394,22 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
I915_WRITE(_3D_CHICKEN2,
_3D_CHICKEN2_WM_READ_PIPELINED << 16 |
_3D_CHICKEN2_WM_READ_PIPELINED);
+
+ ibx_init_clock_gating(dev);
+}
+
+static void cpt_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ /*
+ * On Ibex Peak and Cougar Point, we need to disable clock
+ * gating for the panel power sequencer or it will fail to
+ * start up when no ports are active.
+ */
+ I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
+ I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
+ DPLS_EDP_PPS_FIX_DIS);
}
static void gen6_init_clock_gating(struct drm_device *dev)
@@ -3464,6 +3492,8 @@ static void gen6_init_clock_gating(struct drm_device *dev)
* platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
+
+ cpt_init_clock_gating(dev);
}
static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
@@ -3608,6 +3638,8 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
snpcr &= ~GEN6_MBC_SNPCR_MASK;
snpcr |= GEN6_MBC_SNPCR_MED;
I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
+
+ cpt_init_clock_gating(dev);
}
static void valleyview_init_clock_gating(struct drm_device *dev)
@@ -3771,45 +3803,11 @@ static void i830_init_clock_gating(struct drm_device *dev)
I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
}
-static void ibx_init_clock_gating(struct drm_device *dev)
-{
- struct drm_i915_private *dev_priv = dev->dev_private;
-
- /*
- * On Ibex Peak and Cougar Point, we need to disable clock
- * gating for the panel power sequencer or it will fail to
- * start up when no ports are active.
- */
- I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
-}
-
-static void cpt_init_clock_gating(struct drm_device *dev)
-{
- struct drm_i915_private *dev_priv = dev->dev_private;
-
- /*
- * On Ibex Peak and Cougar Point, we need to disable clock
- * gating for the panel power sequencer or it will fail to
- * start up when no ports are active.
- */
- I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
- I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
- DPLS_EDP_PPS_FIX_DIS);
- /* WADP0ClockGatingDisable */
- for_each_pipe(pipe) {
- I915_WRITE(TRANS_CHICKEN1(pipe),
- TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
- }
-}
-
void intel_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
dev_priv->display.init_clock_gating(dev);
-
- if (dev_priv->display.init_pch_clock_gating)
- dev_priv->display.init_pch_clock_gating(dev);
}
/* Set up chip specific power management-related functions */
@@ -3842,11 +3840,6 @@ void intel_init_pm(struct drm_device *dev)
/* For FIFO watermark updates */
if (HAS_PCH_SPLIT(dev)) {
- if (HAS_PCH_IBX(dev))
- dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
- else if (HAS_PCH_CPT(dev))
- dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
-
if (IS_GEN5(dev)) {
if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
dev_priv->display.update_wm = ironlake_update_wm;
--
1.7.11.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 5/5] drm/i915: kill pch_init_clock_gating indirection
2012-10-29 22:23 ` [PATCH 5/5] drm/i915: kill pch_init_clock_gating indirection Daniel Vetter
@ 2012-10-31 17:52 ` Paulo Zanoni
0 siblings, 0 replies; 17+ messages in thread
From: Paulo Zanoni @ 2012-10-31 17:52 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
Hi
2012/10/29 Daniel Vetter <daniel.vetter@ffwll.ch>:
> Now that we no longer pretend to have flexibility in matching any
> north display block with any pch, we can ditch this.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 -
> drivers/gpu/drm/i915/intel_pm.c | 71 +++++++++++++++++++----------------------
> 2 files changed, 32 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index faf57d6..7186a41a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -270,7 +270,6 @@ struct drm_i915_display_funcs {
> struct drm_crtc *crtc);
> void (*fdi_link_train)(struct drm_crtc *crtc);
> void (*init_clock_gating)(struct drm_device *dev);
> - void (*init_pch_clock_gating)(struct drm_device *dev);
> int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
> struct drm_framebuffer *fb,
> struct drm_i915_gem_object *obj);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1d96c1f..919c1f4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3324,6 +3324,18 @@ void intel_enable_gt_powersave(struct drm_device *dev)
> }
> }
>
> +static void ibx_init_clock_gating(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + /*
> + * On Ibex Peak and Cougar Point, we need to disable clock
> + * gating for the panel power sequencer or it will fail to
> + * start up when no ports are active.
> + */
> + I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
> +}
> +
> static void ironlake_init_clock_gating(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3382,6 +3394,22 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
> I915_WRITE(_3D_CHICKEN2,
> _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
> _3D_CHICKEN2_WM_READ_PIPELINED);
> +
> + ibx_init_clock_gating(dev);
> +}
> +
> +static void cpt_init_clock_gating(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + /*
> + * On Ibex Peak and Cougar Point, we need to disable clock
> + * gating for the panel power sequencer or it will fail to
> + * start up when no ports are active.
> + */
> + I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
> + I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
> + DPLS_EDP_PPS_FIX_DIS);
> }
You've just reverted patch 4/5 :)
>
> static void gen6_init_clock_gating(struct drm_device *dev)
> @@ -3464,6 +3492,8 @@ static void gen6_init_clock_gating(struct drm_device *dev)
> * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
> I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
> I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
> +
> + cpt_init_clock_gating(dev);
> }
>
> static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
> @@ -3608,6 +3638,8 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> snpcr &= ~GEN6_MBC_SNPCR_MASK;
> snpcr |= GEN6_MBC_SNPCR_MED;
> I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
> +
> + cpt_init_clock_gating(dev);
> }
>
> static void valleyview_init_clock_gating(struct drm_device *dev)
> @@ -3771,45 +3803,11 @@ static void i830_init_clock_gating(struct drm_device *dev)
> I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
> }
>
> -static void ibx_init_clock_gating(struct drm_device *dev)
> -{
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
> - /*
> - * On Ibex Peak and Cougar Point, we need to disable clock
> - * gating for the panel power sequencer or it will fail to
> - * start up when no ports are active.
> - */
> - I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
> -}
> -
> -static void cpt_init_clock_gating(struct drm_device *dev)
> -{
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
> - /*
> - * On Ibex Peak and Cougar Point, we need to disable clock
> - * gating for the panel power sequencer or it will fail to
> - * start up when no ports are active.
> - */
> - I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
> - I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
> - DPLS_EDP_PPS_FIX_DIS);
> - /* WADP0ClockGatingDisable */
> - for_each_pipe(pipe) {
> - I915_WRITE(TRANS_CHICKEN1(pipe),
> - TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
> - }
Here ^
> -}
> -
> void intel_init_clock_gating(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> dev_priv->display.init_clock_gating(dev);
> -
> - if (dev_priv->display.init_pch_clock_gating)
> - dev_priv->display.init_pch_clock_gating(dev);
> }
>
> /* Set up chip specific power management-related functions */
> @@ -3842,11 +3840,6 @@ void intel_init_pm(struct drm_device *dev)
>
> /* For FIFO watermark updates */
> if (HAS_PCH_SPLIT(dev)) {
> - if (HAS_PCH_IBX(dev))
> - dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
> - else if (HAS_PCH_CPT(dev))
> - dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
> -
> if (IS_GEN5(dev)) {
> if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
> dev_priv->display.update_wm = ironlake_update_wm;
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 17+ messages in thread