* [PATCH] drm/i915: Adding YUV444 packed format support for skl+ (V13)
@ 2019-10-28 21:29 Bob Paauwe
2019-10-28 21:29 ` [Intel-gfx] " Bob Paauwe
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Bob Paauwe @ 2019-10-28 21:29 UTC (permalink / raw)
To: intel-gfx
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use XYUV instead of AYUV, as we don't use alpha.
v6: Removed unneeded initializer for new XYUV format.
v7: Added scaling support for DRM_FORMAT_XYUV
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
v10: Added missing XYUV format to sprite planes for skl+.
v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV8888.
v12: Fixed rebase conflicts
V13: Rebased.
Added format to ICL format lists.
v12:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
This has been updated to support GEN11 along with rebasing it to
the latest drm-tip. A patch to igt has also been posted that gives
igt the ability to test this format.
drivers/gpu/drm/i915/display/intel_display.c | 5 +++++
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +++++
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9dce2e9e5376..2018e2714c78 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2996,6 +2996,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_XYUV:
+ return DRM_FORMAT_XYUV8888;
case PLANE_CTL_FORMAT_P010:
return DRM_FORMAT_P010;
case PLANE_CTL_FORMAT_P012:
@@ -4070,6 +4072,8 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
case DRM_FORMAT_XRGB16161616F:
case DRM_FORMAT_ARGB16161616F:
return PLANE_CTL_FORMAT_XRGB_16161616F;
+ case DRM_FORMAT_XYUV8888:
+ return PLANE_CTL_FORMAT_XYUV;
case DRM_FORMAT_YUYV:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
case DRM_FORMAT_YVYU:
@@ -5669,6 +5673,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV8888:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index edc41fc40726..a0e6e7717a65 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2412,6 +2412,7 @@ static const u32 skl_plane_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV8888,
};
static const u32 skl_planar_formats[] = {
@@ -2430,6 +2431,7 @@ static const u32 skl_planar_formats[] = {
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
DRM_FORMAT_NV12,
+ DRM_FORMAT_XYUV8888,
};
static const u32 glk_planar_formats[] = {
@@ -2497,6 +2499,7 @@ static const u32 icl_sdr_uv_plane_formats[] = {
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
+ DRM_FORMAT_XYUV8888,
};
static const u32 icl_hdr_plane_formats[] = {
@@ -2526,6 +2529,7 @@ static const u32 icl_hdr_plane_formats[] = {
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
+ DRM_FORMAT_XYUV8888,
};
static const u64 skl_plane_format_modifiers_noccs[] = {
@@ -2676,6 +2680,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV8888:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb33b164ce55..88cfb22df3dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6687,7 +6687,7 @@ enum {
#define PLANE_CTL_FORMAT_P012 (5 << 24)
#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
#define PLANE_CTL_FORMAT_P016 (7 << 24)
-#define PLANE_CTL_FORMAT_AYUV (8 << 24)
+#define PLANE_CTL_FORMAT_XYUV (8 << 24)
#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread* [Intel-gfx] [PATCH] drm/i915: Adding YUV444 packed format support for skl+ (V13)
2019-10-28 21:29 [PATCH] drm/i915: Adding YUV444 packed format support for skl+ (V13) Bob Paauwe
@ 2019-10-28 21:29 ` Bob Paauwe
2019-10-29 1:01 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Adding YUV444 packed format support for skl+ (rev2) Patchwork
2019-10-29 1:25 ` ✗ Fi.CI.BAT: failure " Patchwork
2 siblings, 0 replies; 7+ messages in thread
From: Bob Paauwe @ 2019-10-28 21:29 UTC (permalink / raw)
To: intel-gfx
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use XYUV instead of AYUV, as we don't use alpha.
v6: Removed unneeded initializer for new XYUV format.
v7: Added scaling support for DRM_FORMAT_XYUV
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
v10: Added missing XYUV format to sprite planes for skl+.
v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV8888.
v12: Fixed rebase conflicts
V13: Rebased.
Added format to ICL format lists.
v12:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
This has been updated to support GEN11 along with rebasing it to
the latest drm-tip. A patch to igt has also been posted that gives
igt the ability to test this format.
drivers/gpu/drm/i915/display/intel_display.c | 5 +++++
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +++++
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9dce2e9e5376..2018e2714c78 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2996,6 +2996,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_XYUV:
+ return DRM_FORMAT_XYUV8888;
case PLANE_CTL_FORMAT_P010:
return DRM_FORMAT_P010;
case PLANE_CTL_FORMAT_P012:
@@ -4070,6 +4072,8 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
case DRM_FORMAT_XRGB16161616F:
case DRM_FORMAT_ARGB16161616F:
return PLANE_CTL_FORMAT_XRGB_16161616F;
+ case DRM_FORMAT_XYUV8888:
+ return PLANE_CTL_FORMAT_XYUV;
case DRM_FORMAT_YUYV:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
case DRM_FORMAT_YVYU:
@@ -5669,6 +5673,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV8888:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index edc41fc40726..a0e6e7717a65 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2412,6 +2412,7 @@ static const u32 skl_plane_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV8888,
};
static const u32 skl_planar_formats[] = {
@@ -2430,6 +2431,7 @@ static const u32 skl_planar_formats[] = {
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
DRM_FORMAT_NV12,
+ DRM_FORMAT_XYUV8888,
};
static const u32 glk_planar_formats[] = {
@@ -2497,6 +2499,7 @@ static const u32 icl_sdr_uv_plane_formats[] = {
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
+ DRM_FORMAT_XYUV8888,
};
static const u32 icl_hdr_plane_formats[] = {
@@ -2526,6 +2529,7 @@ static const u32 icl_hdr_plane_formats[] = {
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
+ DRM_FORMAT_XYUV8888,
};
static const u64 skl_plane_format_modifiers_noccs[] = {
@@ -2676,6 +2680,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV8888:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb33b164ce55..88cfb22df3dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6687,7 +6687,7 @@ enum {
#define PLANE_CTL_FORMAT_P012 (5 << 24)
#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
#define PLANE_CTL_FORMAT_P016 (7 << 24)
-#define PLANE_CTL_FORMAT_AYUV (8 << 24)
+#define PLANE_CTL_FORMAT_XYUV (8 << 24)
#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Adding YUV444 packed format support for skl+ (rev2)
2019-10-28 21:29 [PATCH] drm/i915: Adding YUV444 packed format support for skl+ (V13) Bob Paauwe
2019-10-28 21:29 ` [Intel-gfx] " Bob Paauwe
@ 2019-10-29 1:01 ` Patchwork
2019-10-29 1:01 ` [Intel-gfx] " Patchwork
2019-10-29 1:25 ` ✗ Fi.CI.BAT: failure " Patchwork
2 siblings, 1 reply; 7+ messages in thread
From: Patchwork @ 2019-10-29 1:01 UTC (permalink / raw)
To: Bob Paauwe; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Adding YUV444 packed format support for skl+ (rev2)
URL : https://patchwork.freedesktop.org/series/66770/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d19968439852 drm/i915: Adding YUV444 packed format support for skl+ (V13)
-:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#9:
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification.
total: 0 errors, 1 warnings, 0 checks, 66 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Adding YUV444 packed format support for skl+ (rev2)
2019-10-28 21:29 [PATCH] drm/i915: Adding YUV444 packed format support for skl+ (V13) Bob Paauwe
2019-10-28 21:29 ` [Intel-gfx] " Bob Paauwe
2019-10-29 1:01 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Adding YUV444 packed format support for skl+ (rev2) Patchwork
@ 2019-10-29 1:25 ` Patchwork
2019-10-29 1:25 ` [Intel-gfx] " Patchwork
2 siblings, 1 reply; 7+ messages in thread
From: Patchwork @ 2019-10-29 1:25 UTC (permalink / raw)
To: Bob Paauwe; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Adding YUV444 packed format support for skl+ (rev2)
URL : https://patchwork.freedesktop.org/series/66770/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7206 -> Patchwork_15038
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15038 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15038, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15038:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_blt:
- fi-glk-dsi: [PASS][1] -> [TIMEOUT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-glk-dsi/igt@i915_selftest@live_blt.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-glk-dsi/igt@i915_selftest@live_blt.html
- fi-cml-u2: [PASS][3] -> [TIMEOUT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cml-u2/igt@i915_selftest@live_blt.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-cml-u2/igt@i915_selftest@live_blt.html
- fi-skl-lmem: [PASS][5] -> [TIMEOUT][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-skl-lmem/igt@i915_selftest@live_blt.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-skl-lmem/igt@i915_selftest@live_blt.html
- fi-cfl-guc: [PASS][7] -> [TIMEOUT][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cfl-guc/igt@i915_selftest@live_blt.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-cfl-guc/igt@i915_selftest@live_blt.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_blt:
- {fi-icl-dsi}: NOTRUN -> [TIMEOUT][9]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-icl-dsi/igt@i915_selftest@live_blt.html
Known issues
------------
Here are the changes found in Patchwork_15038 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_gem_contexts:
- fi-bsw-n3050: [PASS][10] -> [INCOMPLETE][11] ([fdo# 111542])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html
* igt@prime_vgem@basic-fence-flip:
- fi-icl-u3: [PASS][12] -> [DMESG-WARN][13] ([fdo#107724]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@prime_vgem@basic-fence-flip.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-icl-u3/igt@prime_vgem@basic-fence-flip.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- {fi-icl-dsi}: [INCOMPLETE][14] ([fdo#107713] / [fdo#109100]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-dsi/igt@gem_ctx_create@basic-files.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-icl-dsi/igt@gem_ctx_create@basic-files.html
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][16] ([fdo#103927] / [fdo#111381]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
* igt@gem_mmap_gtt@basic-read-write-distinct:
- fi-icl-u3: [DMESG-WARN][18] ([fdo#107724]) -> [PASS][19] +2 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html
* igt@i915_selftest@live_blt:
- fi-kbl-guc: [TIMEOUT][20] -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-kbl-guc/igt@i915_selftest@live_blt.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-kbl-guc/igt@i915_selftest@live_blt.html
- fi-apl-guc: [TIMEOUT][22] -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-apl-guc/igt@i915_selftest@live_blt.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-apl-guc/igt@i915_selftest@live_blt.html
- fi-kbl-r: [TIMEOUT][24] -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-kbl-r/igt@i915_selftest@live_blt.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-kbl-r/igt@i915_selftest@live_blt.html
- {fi-icl-u4}: [TIMEOUT][26] -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u4/igt@i915_selftest@live_blt.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-icl-u4/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_client:
- fi-cfl-8700k: [INCOMPLETE][28] -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cfl-8700k/igt@i915_selftest@live_client.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-cfl-8700k/igt@i915_selftest@live_client.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
Participating hosts (50 -> 41)
------------------------------
Missing (9): fi-ilk-m540 fi-cml-s fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7206 -> Patchwork_15038
CI-20190529: 20190529
CI_DRM_7206: 197ff4c24c6762ac5bbd8c5364d6f840fb9929c5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5248: 81e55f1f97d73e48f00caa7e4fb98295023c5afa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15038: d19968439852961be9059a69682681693533af26 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d19968439852 drm/i915: Adding YUV444 packed format support for skl+ (V13)
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/index.html
_______________________________________________
Intel-gfx mailing list
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* [Intel-gfx] [PATCH] drm/i915: Adding YUV444 packed format support for skl+ (V13)
@ 2020-01-27 19:22 Bob Paauwe
0 siblings, 0 replies; 7+ messages in thread
From: Bob Paauwe @ 2020-01-27 19:22 UTC (permalink / raw)
To: intel-gfx
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use XYUV instead of AYUV, as we don't use alpha.
v6: Removed unneeded initializer for new XYUV format.
v7: Added scaling support for DRM_FORMAT_XYUV
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
v10: Added missing XYUV format to sprite planes for skl+.
v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV8888.
v12: Fixed rebase conflicts
V13: Rebased.
Added format to ICL format lists.
v12:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +++++
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +++++
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7f94d5ca4207..b9f993769a4a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3328,6 +3328,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_XYUV:
+ return DRM_FORMAT_XYUV8888;
case PLANE_CTL_FORMAT_P010:
return DRM_FORMAT_P010;
case PLANE_CTL_FORMAT_P012:
@@ -4538,6 +4540,8 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
case DRM_FORMAT_XRGB16161616F:
case DRM_FORMAT_ARGB16161616F:
return PLANE_CTL_FORMAT_XRGB_16161616F;
+ case DRM_FORMAT_XYUV8888:
+ return PLANE_CTL_FORMAT_XYUV;
case DRM_FORMAT_YUYV:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
case DRM_FORMAT_YVYU:
@@ -6147,6 +6151,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV8888:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 2f277d1fc6f1..aafe04b29a61 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2470,6 +2470,7 @@ static const u32 skl_plane_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV8888,
};
static const u32 skl_planar_formats[] = {
@@ -2488,6 +2489,7 @@ static const u32 skl_planar_formats[] = {
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
DRM_FORMAT_NV12,
+ DRM_FORMAT_XYUV8888,
};
static const u32 glk_planar_formats[] = {
@@ -2559,6 +2561,7 @@ static const u32 icl_sdr_uv_plane_formats[] = {
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
+ DRM_FORMAT_XYUV8888,
};
static const u32 icl_hdr_plane_formats[] = {
@@ -2590,6 +2593,7 @@ static const u32 icl_hdr_plane_formats[] = {
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
+ DRM_FORMAT_XYUV8888,
};
static const u64 skl_plane_format_modifiers_noccs[] = {
@@ -2757,6 +2761,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV8888:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b93c4c18f05c..b3848e73de29 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6764,7 +6764,7 @@ enum {
#define PLANE_CTL_FORMAT_P012 (5 << 24)
#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
#define PLANE_CTL_FORMAT_P016 (7 << 24)
-#define PLANE_CTL_FORMAT_AYUV (8 << 24)
+#define PLANE_CTL_FORMAT_XYUV (8 << 24)
#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
--
2.21.0
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2019-10-28 21:29 [PATCH] drm/i915: Adding YUV444 packed format support for skl+ (V13) Bob Paauwe
2019-10-28 21:29 ` [Intel-gfx] " Bob Paauwe
2019-10-29 1:01 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Adding YUV444 packed format support for skl+ (rev2) Patchwork
2019-10-29 1:01 ` [Intel-gfx] " Patchwork
2019-10-29 1:25 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-10-29 1:25 ` [Intel-gfx] " Patchwork
2020-01-27 19:22 [Intel-gfx] [PATCH] drm/i915: Adding YUV444 packed format support for skl+ (V13) Bob Paauwe
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