* [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601
@ 2020-01-31 23:17 Anusha Srivatsa
2020-02-01 2:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Implement Wa_1606931601 (rev4) Patchwork
2020-02-08 7:00 ` [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601 Matt Atwood
0 siblings, 2 replies; 11+ messages in thread
From: Anusha Srivatsa @ 2020-01-31 23:17 UTC (permalink / raw)
To: intel-gfx
Disable Early Read and Src Swap (bit 14) by setting the chicken
register.
BSpec: 46045,52890
v2: Follow the Bspec implementation for the WA.
v3: Have 2 separate defines for bit 14 and 15.
- Rename register definitions with TGL_ prefix
v4: Bspec changed. Again. Add WA to rcs_ WA list.
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 8d7c3191137c..b0bcf8c55da0 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -593,6 +593,7 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
FF_MODE2_TDS_TIMER_MASK);
+
}
static void
@@ -1319,6 +1320,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
+ if (IS_TGL_REVID(i915, TGL_REVID_A0, REVID_FOREVER)) {
+ /* Wa_1606931601:tgl */
+ wa_write_or(wal,
+ GEN7_ROW_CHICKEN2,
+ GEN12_EARLY_READ_SRC0_DISABLE);
+ }
if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
/* Wa_1606700617:tgl */
wa_masked_en(wal,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0bd431f6a011..c46bec8ebd17 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9151,6 +9151,7 @@ enum {
#define DOP_CLOCK_GATING_DISABLE (1 << 0)
#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
+#define GEN12_EARLY_READ_SRC0_DISABLE (1 << 14)
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
--
2.25.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Implement Wa_1606931601 (rev4)
2020-01-31 23:17 [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601 Anusha Srivatsa
@ 2020-02-01 2:33 ` Patchwork
2020-02-08 7:00 ` [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601 Matt Atwood
1 sibling, 0 replies; 11+ messages in thread
From: Patchwork @ 2020-02-01 2:33 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Implement Wa_1606931601 (rev4)
URL : https://patchwork.freedesktop.org/series/72433/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16370
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/index.html
Known issues
------------
Here are the changes found in Patchwork_16370 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [PASS][1] -> [FAIL][2] ([i915#138])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
- fi-skl-6770hq: [PASS][3] -> [FAIL][4] ([i915#178])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_gem_contexts:
- fi-hsw-peppy: [PASS][5] -> [DMESG-FAIL][6] ([i915#722])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_gtt:
- fi-bxt-dsi: [PASS][7] -> [TIMEOUT][8] ([fdo#112271])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-bxt-dsi/igt@i915_selftest@live_gtt.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-bxt-dsi/igt@i915_selftest@live_gtt.html
- fi-icl-dsi: [PASS][9] -> [TIMEOUT][10] ([fdo#112271])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-dsi/igt@i915_selftest@live_gtt.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-icl-dsi/igt@i915_selftest@live_gtt.html
#### Possible fixes ####
* igt@gem_close_race@basic-threads:
- fi-byt-j1900: [TIMEOUT][11] ([fdo#112271] / [i915#1084] / [i915#816]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-byt-j1900/igt@gem_close_race@basic-threads.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-byt-j1900/igt@gem_close_race@basic-threads.html
- fi-byt-n2820: [TIMEOUT][13] ([fdo#112271] / [i915#1084] / [i915#816]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-byt-n2820/igt@gem_close_race@basic-threads.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-byt-n2820/igt@gem_close_race@basic-threads.html
* igt@gem_exec_suspend@basic-s3:
- fi-icl-u2: [FAIL][15] ([fdo#103375]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@gem_exec_suspend@basic-s3.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-icl-u2/igt@gem_exec_suspend@basic-s3.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u2: [FAIL][17] ([fdo#111550]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@gem_exec_suspend@basic-s4-devices.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-icl-u2/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_selftest@live_blt:
- fi-hsw-4770: [DMESG-FAIL][19] ([i915#563]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770/igt@i915_selftest@live_blt.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-hsw-4770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_execlists:
- fi-icl-y: [DMESG-FAIL][21] ([fdo#108569]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-y/igt@i915_selftest@live_execlists.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-icl-y/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][23] ([fdo#111096] / [i915#323]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Warnings ####
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-guc: [FAIL][25] ([i915#579]) -> [SKIP][26] ([fdo#109271])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [FAIL][27] ([fdo#103375]) -> [DMESG-WARN][28] ([IGT#4] / [i915#263])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
[IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111550]: https://bugs.freedesktop.org/show_bug.cgi?id=111550
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084
[i915#138]: https://gitlab.freedesktop.org/drm/intel/issues/138
[i915#178]: https://gitlab.freedesktop.org/drm/intel/issues/178
[i915#263]: https://gitlab.freedesktop.org/drm/intel/issues/263
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
[i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722
[i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
Participating hosts (47 -> 46)
------------------------------
Additional (5): fi-gdg-551 fi-cfl-8109u fi-skl-6600u fi-skl-6700k2 fi-snb-2600
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7853 -> Patchwork_16370
CI-20190529: 20190529
CI_DRM_7853: 1df04205c16923e525efe9c26d6e98612d38c9b3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5409: 93aefe6baa3fabf8c0cabe83e185f7b8f8d8753d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16370: 6b9e4bb91817b1a677a9ffe94729e3382b34e4cd @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6b9e4bb91817 drm/i915/tgl: Implement Wa_1606931601
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16370/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601
2020-01-31 23:17 [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601 Anusha Srivatsa
2020-02-01 2:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Implement Wa_1606931601 (rev4) Patchwork
@ 2020-02-08 7:00 ` Matt Atwood
1 sibling, 0 replies; 11+ messages in thread
From: Matt Atwood @ 2020-02-08 7:00 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx
On Fri, Jan 31, 2020 at 03:17:05PM -0800, Anusha Srivatsa wrote:
> Disable Early Read and Src Swap (bit 14) by setting the chicken
> register.
>
> BSpec: 46045,52890
>
> v2: Follow the Bspec implementation for the WA.
> v3: Have 2 separate defines for bit 14 and 15.
> - Rename register definitions with TGL_ prefix
> v4: Bspec changed. Again. Add WA to rcs_ WA list.
>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
See whitespace fix,
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 8d7c3191137c..b0bcf8c55da0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -593,6 +593,7 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
> FF_MODE2_TDS_TIMER_MASK);
> +
^extra new line
> }
>
> static void
> @@ -1319,6 +1320,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> {
> struct drm_i915_private *i915 = engine->i915;
>
> + if (IS_TGL_REVID(i915, TGL_REVID_A0, REVID_FOREVER)) {
> + /* Wa_1606931601:tgl */
> + wa_write_or(wal,
> + GEN7_ROW_CHICKEN2,
> + GEN12_EARLY_READ_SRC0_DISABLE);
> + }
> if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> /* Wa_1606700617:tgl */
> wa_masked_en(wal,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0bd431f6a011..c46bec8ebd17 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9151,6 +9151,7 @@ enum {
> #define DOP_CLOCK_GATING_DISABLE (1 << 0)
> #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
> #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
> +#define GEN12_EARLY_READ_SRC0_DISABLE (1 << 14)
>
> #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
> #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
> --
> 2.25.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601
@ 2020-02-11 23:44 Anusha Srivatsa
0 siblings, 0 replies; 11+ messages in thread
From: Anusha Srivatsa @ 2020-02-11 23:44 UTC (permalink / raw)
To: intel-gfx
Disable Early Read and Src Swap (bit 14) by setting the chicken
register.
BSpec: 46045,52890
v2: Follow the Bspec implementation for the WA.
v3: Have 2 separate defines for bit 14 and 15.
- Rename register definitions with TGL_ prefix
v4: Bspec changed. Again. Add WA to rcs_ WA list.
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 61106129287f..310f8e1beaab 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1326,6 +1326,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
+ if (IS_TGL_REVID(i915, TGL_REVID_A0, REVID_FOREVER)) {
+ /* Wa_1606931601:tgl */
+ wa_write_or(wal,
+ GEN7_ROW_CHICKEN2,
+ GEN12_EARLY_READ_SRC0_DISABLE);
+ }
if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
/* Wa_1606700617:tgl */
wa_masked_en(wal,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0bd431f6a011..c46bec8ebd17 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9151,6 +9151,7 @@ enum {
#define DOP_CLOCK_GATING_DISABLE (1 << 0)
#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
+#define GEN12_EARLY_READ_SRC0_DISABLE (1 << 14)
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601
2020-01-30 20:42 ` Matt Roper
@ 2020-01-31 0:16 ` Srivatsa, Anusha
0 siblings, 0 replies; 11+ messages in thread
From: Srivatsa, Anusha @ 2020-01-31 0:16 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: intel-gfx
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Thursday, January 30, 2020 12:43 PM
> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Ceraolo Spurio, Daniele
> <daniele.ceraolospurio@intel.com>
> Subject: Re: [PATCH] drm/i915/tgl: Implement Wa_1606931601
>
> On Wed, Jan 29, 2020 at 02:42:06PM -0800, Anusha Srivatsa wrote:
> > Disable Inter and intra Read Suppression (bit 15) and Early Read and
> > Src Swap (bit 14) by setting the chicken register.
> >
> > BSpec: 46045,52890
> >
> > v2: Follow the Bspec implementation for the WA.
> > v3: Have 2 separate defines for bit 14 and 15.
> > - Rename register definitions with TGL_ prefix
>
> The hardware guys changed their mind again and we're back to only needing
> bit 14 now. They updated the bspec and the underlying database yet again.
> :-/
☹
> >
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
> > drivers/gpu/drm/i915/i915_reg.h | 2 ++
> > 2 files changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 5a7db279f702..1f84cd595f88 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -593,6 +593,12 @@ static void tgl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> > wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> > IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
> > FF_MODE2_TDS_TIMER_MASK);
> > +
> > + /* Wa_1606931601:tgl */
> > + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> > + GEN12_EARLY_READ_SRC0_DISABLE |
> > +
> GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE);
>
> I think Daniele already mentioned this on the other discussion, but
> ROW_CHICKEN2 isn't part of the context image on gen12 (see bspec page
> 46255). This is a change from ICL where it *was* part of the context (see
> bspec page 18907), so even though we handled this register in the
> ctx_workarounds_init for ICL, that's not the appropriate place to put it for
> TGL.
Agreed.
> Since this isn't a context workaround, we need to determine whether it's a
> general GT workaround (which would be initialized in
> tgl_gt_workarounds_init) or an engine workaround (which would be
> initialized in {rcs,xcs}_engine_wa_init. In this case the register we're
> modifying is 0xe49c; according to bspec page 52078 this falls in one of the
> forcewake ranges listed under the render engine column (0E000-0E8FF).
The register we are setting is 0xe4f4. This comes under Render engine. Adding this change to rcs_engine_wa_init().
> So I
> believe in this case that means we want to update
> rcs_engine_wa_init() with this workaround --- that ensures that the
> workaround will be re-applied any time the engine is reset (even if it's not a
> full-GPU reset).
Yes. Adding this to rcs_engine_wa_init().
Anusha
>
> Matt
>
> > +
> > }
> >
> > static void
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 4c72b8ac0f2e..70ead809c706
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9149,6 +9149,8 @@ enum {
> > #define DOP_CLOCK_GATING_DISABLE (1 << 0)
> > #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
> > #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
> > +#define GEN12_EARLY_READ_SRC0_DISABLE (1 << 14)
> > +#define GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE (1 <<
> 15)
> >
> > #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
> > #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
> > --
> > 2.25.0
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601
2020-01-29 22:42 Anusha Srivatsa
@ 2020-01-30 20:42 ` Matt Roper
2020-01-31 0:16 ` Srivatsa, Anusha
0 siblings, 1 reply; 11+ messages in thread
From: Matt Roper @ 2020-01-30 20:42 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Wed, Jan 29, 2020 at 02:42:06PM -0800, Anusha Srivatsa wrote:
> Disable Inter and intra Read Suppression (bit 15) and
> Early Read and Src Swap (bit 14) by setting the chicken
> register.
>
> BSpec: 46045,52890
>
> v2: Follow the Bspec implementation for the WA.
> v3: Have 2 separate defines for bit 14 and 15.
> - Rename register definitions with TGL_ prefix
The hardware guys changed their mind again and we're back to only
needing bit 14 now. They updated the bspec and the underlying database
yet again. :-/
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 5a7db279f702..1f84cd595f88 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -593,6 +593,12 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
> FF_MODE2_TDS_TIMER_MASK);
> +
> + /* Wa_1606931601:tgl */
> + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> + GEN12_EARLY_READ_SRC0_DISABLE |
> + GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE);
I think Daniele already mentioned this on the other discussion, but
ROW_CHICKEN2 isn't part of the context image on gen12 (see bspec page
46255). This is a change from ICL where it *was* part of the context
(see bspec page 18907), so even though we handled this register in the
ctx_workarounds_init for ICL, that's not the appropriate place to put it
for TGL.
Since this isn't a context workaround, we need to determine whether it's
a general GT workaround (which would be initialized in
tgl_gt_workarounds_init) or an engine workaround (which would be
initialized in {rcs,xcs}_engine_wa_init. In this case the register
we're modifying is 0xe49c; according to bspec page 52078 this falls in
one of the forcewake ranges listed under the render engine column
(0E000-0E8FF). So I believe in this case that means we want to update
rcs_engine_wa_init() with this workaround --- that ensures that the
workaround will be re-applied any time the engine is reset (even if it's
not a full-GPU reset).
Matt
> +
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4c72b8ac0f2e..70ead809c706 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9149,6 +9149,8 @@ enum {
> #define DOP_CLOCK_GATING_DISABLE (1 << 0)
> #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
> #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
> +#define GEN12_EARLY_READ_SRC0_DISABLE (1 << 14)
> +#define GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE (1 << 15)
>
> #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
> #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
> --
> 2.25.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601
@ 2020-01-29 22:42 Anusha Srivatsa
2020-01-30 20:42 ` Matt Roper
0 siblings, 1 reply; 11+ messages in thread
From: Anusha Srivatsa @ 2020-01-29 22:42 UTC (permalink / raw)
To: intel-gfx
Disable Inter and intra Read Suppression (bit 15) and
Early Read and Src Swap (bit 14) by setting the chicken
register.
BSpec: 46045,52890
v2: Follow the Bspec implementation for the WA.
v3: Have 2 separate defines for bit 14 and 15.
- Rename register definitions with TGL_ prefix
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5a7db279f702..1f84cd595f88 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -593,6 +593,12 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
FF_MODE2_TDS_TIMER_MASK);
+
+ /* Wa_1606931601:tgl */
+ WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ GEN12_EARLY_READ_SRC0_DISABLE |
+ GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE);
+
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4c72b8ac0f2e..70ead809c706 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9149,6 +9149,8 @@ enum {
#define DOP_CLOCK_GATING_DISABLE (1 << 0)
#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
+#define GEN12_EARLY_READ_SRC0_DISABLE (1 << 14)
+#define GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE (1 << 15)
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601
@ 2020-01-24 21:29 Anusha Srivatsa
0 siblings, 0 replies; 11+ messages in thread
From: Anusha Srivatsa @ 2020-01-24 21:29 UTC (permalink / raw)
To: intel-gfx
Disable Early Read and Src Swap by setting the bit 14
and 15 in the chicken register.
BSpec: 46045,52890
v2: Follow the Bspec implementation for the WA.
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5a7db279f702..c1c970b15395 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -593,6 +593,11 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
FF_MODE2_TDS_TIMER_MASK);
+
+ /* Wa_1606931601:tgl */
+ WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ GEN11_EARLY_READ_SRC0_DISABLE);
+
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b93c4c18f05c..c8b51ccfa5e6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9146,6 +9146,7 @@ enum {
#define DOP_CLOCK_GATING_DISABLE (1 << 0)
#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
+#define GEN11_EARLY_READ_SRC0_DISABLE (1 << 14)
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601
2020-01-23 17:50 ` Matt Roper
@ 2020-01-24 19:36 ` Srivatsa, Anusha
0 siblings, 0 replies; 11+ messages in thread
From: Srivatsa, Anusha @ 2020-01-24 19:36 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: intel-gfx
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Thursday, January 23, 2020 9:50 AM
> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601
>
> On Wed, Jan 22, 2020 at 03:40:27PM -0800, Anusha Srivatsa wrote:
> > Disable Early Read and Src Swap by setting the bit 14 and 15 in the
> > chicken register.
> >
> > BSpec: 46045,52890
> > HSDES: 1606931601
>
> Hmm. The bspec WA description (which is very poorly written) only
> mentions setting bit 14, but comments in the HSD indicate that both 14 and
> 15 should be set. Do we have offline confirmation/clarification about which
> we should trust?
>
> If we do need to program both bits, it might still be a good idea to use two
> separate #define's for those rather than a single bitmask to make it more
> clear what we're doing and also to give us the option of just setting one or
> the other in case that winds up being necessary as a workaround for a
> different platform or future stepping.
>
Going ahead with what the BSpec expects us to do - setting just bit 14. Sending v2 version shortly.
Anusha
> Matt
>
> >
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 2 files changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 5a7db279f702..53b448b61a5f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -593,6 +593,11 @@ static void tgl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> > wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> > IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
> > FF_MODE2_TDS_TIMER_MASK);
> > +
> > + /* Wa_1606931601:tgl */
> > + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> > + GEN11_EARLY_READ_SRC0_DISABLE_MASK);
> > +
> > }
> >
> > static void
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index b93c4c18f05c..69a1c2227b91
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9146,6 +9146,7 @@ enum {
> > #define DOP_CLOCK_GATING_DISABLE (1 << 0)
> > #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
> > #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
> > +#define GEN11_EARLY_READ_SRC0_DISABLE_MASK
> REG_GENMASK(15, 14)
> >
> > #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
> > #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
> > --
> > 2.23.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601
2020-01-22 23:40 Anusha Srivatsa
@ 2020-01-23 17:50 ` Matt Roper
2020-01-24 19:36 ` Srivatsa, Anusha
0 siblings, 1 reply; 11+ messages in thread
From: Matt Roper @ 2020-01-23 17:50 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Wed, Jan 22, 2020 at 03:40:27PM -0800, Anusha Srivatsa wrote:
> Disable Early Read and Src Swap by setting the bit 14
> and 15 in the chicken register.
>
> BSpec: 46045,52890
> HSDES: 1606931601
Hmm. The bspec WA description (which is very poorly written) only
mentions setting bit 14, but comments in the HSD indicate that both 14
and 15 should be set. Do we have offline confirmation/clarification
about which we should trust?
If we do need to program both bits, it might still be a good idea to use
two separate #define's for those rather than a single bitmask to make it
more clear what we're doing and also to give us the option of just
setting one or the other in case that winds up being necessary as a
workaround for a different platform or future stepping.
Matt
>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 5a7db279f702..53b448b61a5f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -593,6 +593,11 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
> FF_MODE2_TDS_TIMER_MASK);
> +
> + /* Wa_1606931601:tgl */
> + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> + GEN11_EARLY_READ_SRC0_DISABLE_MASK);
> +
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b93c4c18f05c..69a1c2227b91 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9146,6 +9146,7 @@ enum {
> #define DOP_CLOCK_GATING_DISABLE (1 << 0)
> #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
> #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
> +#define GEN11_EARLY_READ_SRC0_DISABLE_MASK REG_GENMASK(15, 14)
>
> #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
> #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601
@ 2020-01-22 23:40 Anusha Srivatsa
2020-01-23 17:50 ` Matt Roper
0 siblings, 1 reply; 11+ messages in thread
From: Anusha Srivatsa @ 2020-01-22 23:40 UTC (permalink / raw)
To: intel-gfx
Disable Early Read and Src Swap by setting the bit 14
and 15 in the chicken register.
BSpec: 46045,52890
HSDES: 1606931601
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5a7db279f702..53b448b61a5f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -593,6 +593,11 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
FF_MODE2_TDS_TIMER_MASK);
+
+ /* Wa_1606931601:tgl */
+ WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ GEN11_EARLY_READ_SRC0_DISABLE_MASK);
+
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b93c4c18f05c..69a1c2227b91 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9146,6 +9146,7 @@ enum {
#define DOP_CLOCK_GATING_DISABLE (1 << 0)
#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
+#define GEN11_EARLY_READ_SRC0_DISABLE_MASK REG_GENMASK(15, 14)
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-02-11 23:56 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-31 23:17 [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601 Anusha Srivatsa
2020-02-01 2:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Implement Wa_1606931601 (rev4) Patchwork
2020-02-08 7:00 ` [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601 Matt Atwood
-- strict thread matches above, loose matches on Subject: below --
2020-02-11 23:44 Anusha Srivatsa
2020-01-29 22:42 Anusha Srivatsa
2020-01-30 20:42 ` Matt Roper
2020-01-31 0:16 ` Srivatsa, Anusha
2020-01-24 21:29 Anusha Srivatsa
2020-01-22 23:40 Anusha Srivatsa
2020-01-23 17:50 ` Matt Roper
2020-01-24 19:36 ` Srivatsa, Anusha
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