From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 5/8] drm/i915: Use drm_rect to store the pfit window pos/size
Date: Wed, 12 Feb 2020 18:17:35 +0200 [thread overview]
Message-ID: <20200212161738.28141-6-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20200212161738.28141-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make things a bit more abstract by replacing the pch_pfit.pos/size
raw register values with a drm_rect. Makes it slighly more convenient
to eg. compute the scaling factors.
v2: Use drm_rect_init()
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 101 +++++++++++-------
.../drm/i915/display/intel_display_types.h | 3 +-
drivers/gpu/drm/i915/display/intel_panel.c | 13 ++-
3 files changed, 67 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 796e27c4aece..19f3fef11b0d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6108,10 +6108,8 @@ static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
int width, height;
if (crtc_state->pch_pfit.enabled) {
- u32 pfit_size = crtc_state->pch_pfit.size;
-
- width = pfit_size >> 16;
- height = pfit_size & 0xffff;
+ width = drm_rect_width(&crtc_state->pch_pfit.dst);
+ height = drm_rect_height(&crtc_state->pch_pfit.dst);
} else {
width = adjusted_mode->crtc_hdisplay;
height = adjusted_mode->crtc_vdisplay;
@@ -6230,11 +6228,20 @@ static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
const struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
+ struct drm_rect src = {
+ .x2 = crtc_state->pipe_src_w << 16,
+ .y2 = crtc_state->pipe_src_h << 16,
+ };
+ const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
u16 uv_rgb_hphase, uv_rgb_vphase;
- int pfit_w, pfit_h, hscale, vscale;
+ enum pipe pipe = crtc->pipe;
+ int width = drm_rect_width(dst);
+ int height = drm_rect_height(dst);
+ int x = dst->x1;
+ int y = dst->y1;
+ int hscale, vscale;
unsigned long irqflags;
int id;
@@ -6244,11 +6251,8 @@ static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
return;
- pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
- pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
-
- hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
- vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
+ hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
+ vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
@@ -6264,9 +6268,9 @@ static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
- crtc_state->pch_pfit.pos);
+ x << 16 | y);
intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
- crtc_state->pch_pfit.size);
+ width << 16 | height);
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
@@ -6275,7 +6279,12 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
enum pipe pipe = crtc->pipe;
+ int width = drm_rect_width(dst);
+ int height = drm_rect_height(dst);
+ int x = dst->x1;
+ int y = dst->y1;
if (!crtc_state->pch_pfit.enabled)
return;
@@ -6290,10 +6299,8 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
else
intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
PF_FILTER_MED_3x3);
- intel_de_write(dev_priv, PF_WIN_POS(pipe),
- crtc_state->pch_pfit.pos);
- intel_de_write(dev_priv, PF_WIN_SZ(pipe),
- crtc_state->pch_pfit.size);
+ intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
+ intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
}
void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
@@ -7932,8 +7939,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
{
u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock;
- u32 pfit_size = crtc_state->pch_pfit.size;
- u64 pipe_w, pipe_h, pfit_w, pfit_h;
+ unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
/*
* We only use IF-ID interlacing. If we ever use
@@ -7946,8 +7952,9 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
pipe_w = crtc_state->pipe_src_w;
pipe_h = crtc_state->pipe_src_h;
- pfit_w = (pfit_size >> 16) & 0xFFFF;
- pfit_h = pfit_size & 0xFFFF;
+ pfit_w = drm_rect_width(&crtc_state->pch_pfit.dst);
+ pfit_h = drm_rect_height(&crtc_state->pch_pfit.dst);
+
if (pipe_w < pfit_w)
pipe_w = pfit_w;
if (pipe_h < pfit_h)
@@ -10391,6 +10398,14 @@ static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
&pipe_config->fdi_m_n, NULL);
}
+static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
+ u32 pos, u32 size)
+{
+ drm_rect_init(&crtc_state->pch_pfit.dst,
+ pos >> 16, pos & 0xffff,
+ size >> 16, size & 0xffff);
+}
+
static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -10401,18 +10416,20 @@ static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
/* find scaler attached to this pipe */
for (i = 0; i < crtc->num_scalers; i++) {
- u32 tmp;
+ u32 ctl, pos, size;
- tmp = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
- if ((tmp & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
+ ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
+ if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
continue;
id = i;
crtc_state->pch_pfit.enabled = true;
- crtc_state->pch_pfit.pos =
- intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
- crtc_state->pch_pfit.size =
- intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
+
+ pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
+ size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
+
+ ilk_get_pfit_pos_size(crtc_state, pos, size);
+
scaler_state->scalers[i].in_use = true;
break;
}
@@ -10561,17 +10578,18 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- u32 tmp;
+ u32 ctl, pos, size;
- tmp = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
- if ((tmp & PF_ENABLE) == 0)
+ ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
+ if ((ctl & PF_ENABLE) == 0)
return;
crtc_state->pch_pfit.enabled = true;
- crtc_state->pch_pfit.pos =
- intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
- crtc_state->pch_pfit.size =
- intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
+
+ pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
+ size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
+
+ ilk_get_pfit_pos_size(crtc_state, pos, size);
/*
* We currently do not free assignements of panel fitters on
@@ -10579,7 +10597,7 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
* differentiates them) so just WARN about this case for now.
*/
WARN_ON(IS_GEN(dev_priv, 7) &&
- (tmp & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
+ (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
}
static bool ilk_get_pipe_config(struct intel_crtc *crtc,
@@ -13196,9 +13214,8 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
pipe_config->gmch_pfit.lvds_border_bits);
else
drm_dbg_kms(&dev_priv->drm,
- "pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n",
- pipe_config->pch_pfit.pos,
- pipe_config->pch_pfit.size,
+ "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
+ DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
enableddisabled(pipe_config->pch_pfit.enabled),
yesno(pipe_config->pch_pfit.force_thru));
@@ -13949,8 +13966,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
if (current_config->pch_pfit.enabled) {
- PIPE_CONF_CHECK_X(pch_pfit.pos);
- PIPE_CONF_CHECK_X(pch_pfit.size);
+ PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
+ PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
+ PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
+ PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
}
PIPE_CONF_CHECK_I(scaler_state.scaler_id);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 283c622f8ba1..38eb1036f32b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -937,8 +937,7 @@ struct intel_crtc_state {
/* Panel fitter placement and size for Ironlake+ */
struct {
- u32 pos;
- u32 size;
+ struct drm_rect dst;
bool enabled;
bool force_thru;
} pch_pfit;
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 8b0730f4c442..972fff7e2ba0 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -182,13 +182,13 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
int fitting_mode)
{
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
- int x = 0, y = 0, width = 0, height = 0;
+ int x, y, width, height;
/* Native modes don't need fitting */
if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h &&
pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
- goto done;
+ return;
switch (fitting_mode) {
case DRM_MODE_SCALE_CENTER:
@@ -234,14 +234,13 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
break;
default:
- WARN(1, "bad panel fit mode: %d\n", fitting_mode);
+ MISSING_CASE(fitting_mode);
return;
}
-done:
- pipe_config->pch_pfit.pos = (x << 16) | y;
- pipe_config->pch_pfit.size = (width << 16) | height;
- pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0;
+ drm_rect_init(&pipe_config->pch_pfit.dst,
+ x, y, width, height);
+ pipe_config->pch_pfit.enabled = true;
}
static void
--
2.24.1
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next prev parent reply other threads:[~2020-02-12 16:18 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-12 16:17 [Intel-gfx] [PATCH v2 0/8] drm/i915: pfit/scaler rework prep stuff Ville Syrjala
2020-02-12 16:17 ` [Intel-gfx] [PATCH v2 1/8] drm/i915: Parametrize PFIT_PIPE Ville Syrjala
2020-02-12 17:43 ` Jani Nikula
2020-02-13 15:00 ` Ville Syrjälä
2020-04-01 22:48 ` Manasi Navare
2020-04-02 13:55 ` Ville Syrjälä
2020-02-12 16:17 ` [Intel-gfx] [PATCH v2 2/8] drm/i915: Use intel_de_write_fw() for skl+ scaler registers Ville Syrjala
2020-02-12 17:47 ` Jani Nikula
2020-02-12 16:17 ` [Intel-gfx] [PATCH v2 3/8] drm/i915: Fix skl+ non-scaled pfit modes Ville Syrjala
2020-04-01 23:35 ` Manasi Navare
2020-02-12 16:17 ` [Intel-gfx] [PATCH v2 4/8] drm/i915: Flatten a bunch of the pfit functions Ville Syrjala
2020-04-01 23:53 ` Manasi Navare
2020-04-02 13:55 ` Ville Syrjälä
2020-04-21 23:32 ` Manasi Navare
2020-02-12 16:17 ` Ville Syrjala [this message]
2020-02-12 16:17 ` [Intel-gfx] [PATCH v2 6/8] drm/i915: s/pipe_config/crtc_state/ in " Ville Syrjala
2020-02-12 16:17 ` [Intel-gfx] [PATCH v2 7/8] drm/i915: Pass connector state to pfit calculations Ville Syrjala
2020-02-12 16:17 ` [Intel-gfx] [PATCH v2 8/8] drm/i915: Have pfit calculations return an error code Ville Syrjala
2020-02-13 6:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: pfit/scaler rework prep stuff (rev2) Patchwork
2020-02-16 22:45 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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