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From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915/gt: Ensure 'ENABLE_BOOT_FETCH' is enabled before ppGTT
Date: Thu, 13 Feb 2020 15:47:59 +0000	[thread overview]
Message-ID: <20200213154759.3641671-1-chris@chris-wilson.co.uk> (raw)

Cryptic notes in bspec say that "The MBC Driver Boot Enable bit in MBCTL
register must be set before this register is written to upon boot up
(including S3 exit)."

We tried adding it to our list of verified workarounds, but our
self checks spot that the bit does not stick. It's only meant to be
cleared after a FLR. As it fails our verification, just blindly apply
the bit prior to loading the ppGTT.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ring_submission.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index f70b903a98bc..e41a329d435a 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -642,6 +642,9 @@ static void set_pp_dir(struct intel_engine_cs *engine)
 	if (vm) {
 		struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 
+		intel_uncore_rmw(engine->uncore, GEN6_MBCTL,
+				 0, GEN6_MBCTL_ENABLE_BOOT_FETCH)
+
 		ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
 		ENGINE_WRITE(engine, RING_PP_DIR_BASE,
 			     px_base(ppgtt->pd)->ggtt_offset << 10);
-- 
2.25.0

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             reply	other threads:[~2020-02-13 15:48 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-13 15:47 Chris Wilson [this message]
2020-02-13 17:38 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/gt: Ensure 'ENABLE_BOOT_FETCH' is enabled before ppGTT Patchwork
2020-02-13 17:57 ` [Intel-gfx] [PATCH] " Ville Syrjälä
2020-02-13 18:07   ` Chris Wilson

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