From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42DBCC2BA83 for ; Thu, 13 Feb 2020 17:58:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 25B6F206DB for ; Thu, 13 Feb 2020 17:58:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 25B6F206DB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B50D46E3B7; Thu, 13 Feb 2020 17:58:01 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 334356E3B7 for ; Thu, 13 Feb 2020 17:58:00 +0000 (UTC) X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Feb 2020 09:57:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,437,1574150400"; d="scan'208";a="228210530" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga008.fm.intel.com with SMTP; 13 Feb 2020 09:57:57 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 13 Feb 2020 19:57:56 +0200 Date: Thu, 13 Feb 2020 19:57:56 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Chris Wilson Message-ID: <20200213175756.GH13686@intel.com> References: <20200213154759.3641671-1-chris@chris-wilson.co.uk> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200213154759.3641671-1-chris@chris-wilson.co.uk> X-Patchwork-Hint: comment User-Agent: Mutt/1.10.1 (2018-07-13) Subject: Re: [Intel-gfx] [PATCH] drm/i915/gt: Ensure 'ENABLE_BOOT_FETCH' is enabled before ppGTT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, Feb 13, 2020 at 03:47:59PM +0000, Chris Wilson wrote: > Cryptic notes in bspec say that "The MBC Driver Boot Enable bit in MBCTL > register must be set before this register is written to upon boot up > (including S3 exit)." > = > We tried adding it to our list of verified workarounds, but our > self checks spot that the bit does not stick. It's only meant to be > cleared after a FLR. As it fails our verification, just blindly apply > the bit prior to loading the ppGTT. > = > Signed-off-by: Chris Wilson > cc: Mika Kuoppala > --- > drivers/gpu/drm/i915/gt/intel_ring_submission.c | 3 +++ > 1 file changed, 3 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gp= u/drm/i915/gt/intel_ring_submission.c > index f70b903a98bc..e41a329d435a 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > @@ -642,6 +642,9 @@ static void set_pp_dir(struct intel_engine_cs *engine) > if (vm) { > struct i915_ppgtt *ppgtt =3D i915_vm_to_ppgtt(vm); > = > + intel_uncore_rmw(engine->uncore, GEN6_MBCTL, > + 0, GEN6_MBCTL_ENABLE_BOOT_FETCH) Wasn't setting this bit implicated in some regressions long ago? > + > ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G); > ENGINE_WRITE(engine, RING_PP_DIR_BASE, > px_base(ppgtt->pd)->ggtt_offset << 10); > -- = > 2.25.0 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx