From: Aditya Swarup <aditya.swarup@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 0/1] Adding definitions for VRR registers and bitfields
Date: Fri, 14 Feb 2020 04:27:50 -0800 [thread overview]
Message-ID: <20200214122751.18530-1-aditya.swarup@intel.com> (raw)
Add definitions for configuring VRR registers for TGL.
Aditya Swarup (1):
drm/i915/tgl: Add definitions for VRR registers and bits
drivers/gpu/drm/i915/i915_reg.h | 90 +++++++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
--
2.25.0
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next reply other threads:[~2020-02-14 12:28 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-14 12:27 Aditya Swarup [this message]
2020-02-14 12:27 ` [Intel-gfx] [PATCH v2 1/1] drm/i915/tgl: Add definitions for VRR registers and bits Aditya Swarup
2020-02-27 23:07 ` Manasi Navare
2020-02-14 16:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Adding definitions for VRR registers and bitfields (rev2) Patchwork
2020-02-17 20:35 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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