Re: [Intel-gfx] [PATCH v4] drm/i915/tgl: Add Wa_1606054188:tgl

[Matt Roper <matthew.d.roper@intel.com>]

On Wed, Feb 26, 2020 at 02:47:24PM -0800, Souza, Jose wrote:
> On Mon, 2020-02-24 at 14:36 -0800, Matt Roper wrote:
> > From: Matt Atwood <matthew.s.atwood@intel.com>
> > 
> > On Tiger Lake we do not support source keying in the pixel formats
> > P010,
> > P012, P016.
> > 
> > v2: Move WA to end of function. Create helper function for format
> > check. Less verbose debugging messaging.
> > 
> > v3: whitespace
> > 
> > v4(MattR):
> >  - Actually return EINVAL to reject this combination.
> >  - Pass format parameter as u32.
> >  - Make test TGL-specific for now.
> >  - Switch to per-device logging.
> >  - Shorten/simplify comment.
> 
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

Applied to dinq.  Thanks for the review.


Matt

> 
> > 
> > Bspec: 52890
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_sprite.c | 21
> > +++++++++++++++++++++
> >  1 file changed, 21 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index 7abeefe8dce5..dc7d3f3f4eb3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -2077,6 +2077,18 @@ vlv_sprite_check(struct intel_crtc_state
> > *crtc_state,
> >  	return 0;
> >  }
> >  
> > +static bool intel_format_is_p01x(u32 format)
> > +{
> > +	switch (format) {
> > +	case DRM_FORMAT_P010:
> > +	case DRM_FORMAT_P012:
> > +	case DRM_FORMAT_P016:
> > +		return true;
> > +	default:
> > +		return false;
> > +	}
> > +}
> > +
> >  static int skl_plane_check_fb(const struct intel_crtc_state
> > *crtc_state,
> >  			      const struct intel_plane_state
> > *plane_state)
> >  {
> > @@ -2155,6 +2167,15 @@ static int skl_plane_check_fb(const struct
> > intel_crtc_state *crtc_state,
> >  		return -EINVAL;
> >  	}
> >  
> > +	/* Wa_1606054188:tgl */
> > +	if (IS_TIGERLAKE(dev_priv) &&
> > +	    plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
> > +	    intel_format_is_p01x(fb->format->format)) {
> > +		drm_dbg_kms(&dev_priv->drm,
> > +			    "Source color keying not supported with
> > P01x formats\n");
> > +		return -EINVAL;
> > +	}
> > +
> >  	return 0;
> >  }
> >  

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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