From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>,
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: [Intel-gfx] [PATCH v2 2/2] drm/i915/display: Do not write in removed FBC fence registers
Date: Fri, 6 Mar 2020 10:58:33 -0800 [thread overview]
Message-ID: <20200306185833.53984-2-jose.souza@intel.com> (raw)
In-Reply-To: <20200306185833.53984-1-jose.souza@intel.com>
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Platforms without fences don't have FBC host tracking and those
registers are marked as reserved in those platforms.
v2: checking num_fences to write to FBC fence registers (Ville)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 010b1107671f..2e5d835a9eaa 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -321,7 +321,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
SNB_CPU_FENCE_ENABLE | params->fence_id);
intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
params->crtc.fence_y_offset);
- } else {
+ } else if (dev_priv->ggtt.num_fences) {
intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
}
--
2.25.1
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next prev parent reply other threads:[~2020-03-06 18:57 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-06 18:58 [Intel-gfx] [PATCH v2 1/2] drm/i915/display: Deactive FBC in fastsets when disabled by parameter José Roberto de Souza
2020-03-06 18:58 ` José Roberto de Souza [this message]
2020-03-07 1:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] " Patchwork
2020-03-07 1:56 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2020-03-07 2:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-07 20:17 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-03-09 17:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/display: Deactive FBC in fastsets when disabled by parameter (rev2) Patchwork
2020-03-10 14:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-10 18:13 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-03-10 20:44 ` Souza, Jose
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