From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 5/7] drm/i915: Apply Wa_1406680159:icl, ehl as an engine workaround
Date: Mon, 9 Mar 2020 17:49:09 -0700 [thread overview]
Message-ID: <20200310004911.1723239-6-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20200310004911.1723239-1-matthew.d.roper@intel.com>
The register this workaround updates is a render engine register in the
MCR range, so we should initialize this in rcs_engine_wa_init() rather
than gt_wa_init().
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1222
Fixes: 36204d80bacb ("drm/i915/icl: Wa_1406680159")
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index bd90dc5fb35d..700cb6d1f45e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -917,11 +917,6 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
SLICE_UNIT_LEVEL_CLKGATE,
MSCUNIT_CLKGATE_DIS);
- /* Wa_1406680159:icl */
- wa_write_or(wal,
- SUBSLICE_UNIT_LEVEL_CLKGATE,
- GWUNIT_CLKGATE_DIS);
-
/* Wa_1406838659:icl (pre-prod) */
if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
wa_write_or(wal,
@@ -1487,6 +1482,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
/* Wa_1406306137:icl,ehl */
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
+
+ /* Wa_1406680159:icl,ehl */
+ wa_write_or(wal,
+ SUBSLICE_UNIT_LEVEL_CLKGATE,
+ GWUNIT_CLKGATE_DIS);
}
if (IS_GEN_RANGE(i915, 9, 12)) {
--
2.24.1
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next prev parent reply other threads:[~2020-03-10 0:49 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-10 0:49 [Intel-gfx] [PATCH 0/7] Gen11 workarounds Matt Roper
2020-03-10 0:49 ` [Intel-gfx] [PATCH 1/7] drm/i915: Handle all MCR ranges Matt Roper
2020-03-10 0:49 ` [Intel-gfx] [PATCH 2/7] drm/i915: Add Wa_1207131216:icl,ehl Matt Roper
2020-03-10 16:22 ` Mika Kuoppala
2020-03-10 0:49 ` [Intel-gfx] [PATCH 3/7] drm/i915: Add Wa_1604278689:icl,ehl Matt Roper
2020-03-10 16:37 ` Chris Wilson
2020-03-10 16:49 ` Matt Roper
2020-03-10 0:49 ` [Intel-gfx] [PATCH 4/7] drm/i915: Add Wa_1406306137:icl,ehl Matt Roper
2020-03-10 0:49 ` Matt Roper [this message]
2020-03-10 0:49 ` [Intel-gfx] [PATCH 6/7] drm/i915: Add Wa_1605460711 / Wa_1408767742 to ICL and EHL Matt Roper
2020-03-10 0:49 ` [Intel-gfx] [PATCH 7/7] drm/i915: Add Wa_1409178092:icl,ehl Matt Roper
2020-03-10 1:01 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Gen11 workarounds Patchwork
2020-03-10 17:30 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-03-10 22:28 ` Souza, Jose
2020-03-10 23:18 ` Matt Roper
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