From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86A9AC10DCE for ; Fri, 13 Mar 2020 07:39:26 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1A7FE206B1 for ; Fri, 13 Mar 2020 07:39:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1A7FE206B1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9DEAC6EB79; Fri, 13 Mar 2020 07:39:24 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 199F66EB79 for ; Fri, 13 Mar 2020 07:39:23 +0000 (UTC) X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Mar 2020 00:39:22 -0700 X-IronPort-AV: E=Sophos;i="5.70,547,1574150400"; d="scan'208";a="236884666" Received: from wgcrocco-mobl.amr.corp.intel.com (HELO ldmartin-desk1) ([10.252.133.92]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Mar 2020 00:39:17 -0700 Date: Fri, 13 Mar 2020 00:39:17 -0700 From: Lucas De Marchi To: Anshuman Gupta Message-ID: <20200313073917.aeki7lm6zupx7y26@ldmartin-desk1> References: <20200311083632.3249-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200311083632.3249-1-anshuman.gupta@intel.com> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Enable non-contiguous pipe fusing X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1"; Format="flowed" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, Mar 11, 2020 at 02:06:32PM +0530, Anshuman Gupta wrote: >Allow 3-display pipes SKU system with any combination >in INTEL_INFO pipe mask. >B.Spec:50075 > >changes since RFC: >- using intel_pipe_mask_is_valid() function to check integrity of > pipe_mask. [Ville] >v2: >- simplify condition in intel_pipe_mask_is_valid(). [Ville] >v3: >- removed non-contiguous pipe fusing check. [Lucas] I'd also say in the commit message that the support for non-contiguous pipe fusing is *already* supported in the driver. So this check here doesn't make sense anymore and since it's an unlike condition we can just stop checking. Aside from commit message update, Reviewed-by: Lucas De Marchi Lucas De Marchi > >Cc: Ville Syrj=E4l=E4 >Cc: Lucas De Marchi >Signed-off-by: Anshuman Gupta >--- > drivers/gpu/drm/i915/intel_device_info.c | 12 +----------- > 1 file changed, 1 insertion(+), 11 deletions(-) > >diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i9= 15/intel_device_info.c >index d7fe12734db8..9ff89e142ff1 100644 >--- a/drivers/gpu/drm/i915/intel_device_info.c >+++ b/drivers/gpu/drm/i915/intel_device_info.c >@@ -998,17 +998,7 @@ void intel_device_info_runtime_init(struct drm_i915_p= rivate *dev_priv) > (dfsm & TGL_DFSM_PIPE_D_DISABLE)) > enabled_mask &=3D ~BIT(PIPE_D); > >- /* >- * At least one pipe should be enabled and if there are >- * disabled pipes, they should be the last ones, with no holes >- * in the mask. >- */ >- if (enabled_mask =3D=3D 0 || !is_power_of_2(enabled_mask + 1)) >- drm_err(&dev_priv->drm, >- "invalid pipe fuse configuration: enabled_mask=3D0x%x\n", >- enabled_mask); >- else >- info->pipe_mask =3D enabled_mask; >+ info->pipe_mask =3D enabled_mask; > > if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) > info->display.has_hdcp =3D 0; >-- = >2.25.1 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx