[Intel-gfx] [PATCH 5/7] drm/i915/gt: Store the fence details on the fence

[Chris Wilson <chris@chris-wilson.co.uk>]

Make a copy of the object tiling parameters at the point of grabbing the
fence.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 18 ++++++++++--------
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h |  2 ++
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index b6ba68c42546..51984cee18b3 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -88,7 +88,7 @@ static void i965_write_fence_reg(struct i915_fence_reg *fence,
 
 	val = 0;
 	if (vma) {
-		unsigned int stride = i915_gem_object_get_stride(vma->obj);
+		unsigned int stride = fence->stride;
 
 		GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
 		GEM_BUG_ON(!IS_ALIGNED(vma->node.start, I965_FENCE_PAGE));
@@ -98,7 +98,7 @@ static void i965_write_fence_reg(struct i915_fence_reg *fence,
 		val = (vma->node.start + vma->fence_size - I965_FENCE_PAGE) << 32;
 		val |= vma->node.start;
 		val |= (u64)((stride / 128) - 1) << fence_pitch_shift;
-		if (i915_gem_object_get_tiling(vma->obj) == I915_TILING_Y)
+		if (fence->tiling == I915_TILING_Y)
 			val |= BIT(I965_FENCE_TILING_Y_SHIFT);
 		val |= I965_FENCE_REG_VALID;
 	}
@@ -132,9 +132,9 @@ static void i915_write_fence_reg(struct i915_fence_reg *fence,
 
 	val = 0;
 	if (vma) {
-		unsigned int tiling = i915_gem_object_get_tiling(vma->obj);
+		unsigned int stride = fence->stride;
+		unsigned int tiling = fence->tiling;
 		bool is_y_tiled = tiling == I915_TILING_Y;
-		unsigned int stride = i915_gem_object_get_stride(vma->obj);
 
 		GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
 		GEM_BUG_ON(vma->node.start & ~I915_FENCE_START_MASK);
@@ -172,7 +172,7 @@ static void i830_write_fence_reg(struct i915_fence_reg *fence,
 
 	val = 0;
 	if (vma) {
-		unsigned int stride = i915_gem_object_get_stride(vma->obj);
+		unsigned int stride = fence->stride;
 
 		GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
 		GEM_BUG_ON(vma->node.start & ~I830_FENCE_START_MASK);
@@ -181,7 +181,7 @@ static void i830_write_fence_reg(struct i915_fence_reg *fence,
 		GEM_BUG_ON(!IS_ALIGNED(vma->node.start, vma->fence_size));
 
 		val = vma->node.start;
-		if (i915_gem_object_get_tiling(vma->obj) == I915_TILING_Y)
+		if (fence->tiling == I915_TILING_Y)
 			val |= BIT(I830_FENCE_TILING_Y_SHIFT);
 		val |= I830_FENCE_SIZE_BITS(vma->fence_size);
 		val |= ilog2(stride / 128) << I830_FENCE_PITCH_SHIFT;
@@ -219,8 +219,6 @@ static void fence_write(struct i915_fence_reg *fence,
 	 * Access through the fenced region afterwards is
 	 * ordered by the posting reads whilst writing the registers.
 	 */
-
-	fence->dirty = false;
 }
 
 static int fence_update(struct i915_fence_reg *fence,
@@ -240,6 +238,10 @@ static int fence_update(struct i915_fence_reg *fence,
 		ret = i915_vma_sync(vma);
 		if (ret)
 			return ret;
+
+		fence->stride = i915_gem_object_get_stride(vma->obj);
+		fence->tiling = i915_gem_object_get_tiling(vma->obj);
+		WRITE_ONCE(fence->dirty, false);
 	}
 
 	old = xchg(&fence->vma, NULL);
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
index 9850f6a85d2a..ad3acc9b7f37 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
@@ -51,6 +51,8 @@ struct i915_fence_reg {
 	 * command (such as BLT on gen2/3), as a "fence".
 	 */
 	bool dirty;
+	unsigned int stride;
+	unsigned int tiling;
 };
 
 struct i915_fence_reg *i915_reserve_fence(struct i915_ggtt *ggtt);
-- 
2.20.1

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