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From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 10/15] drm/i915/gem: Assign context id for async work
Date: Mon, 16 Mar 2020 11:42:32 +0000	[thread overview]
Message-ID: <20200316114237.5436-10-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <20200316114237.5436-1-chris@chris-wilson.co.uk>

Allocate a few dma fence context id that we can use to associate async work
[for the CPU] launched on behalf of this context. For extra fun, we allow
a configurable concurrency width.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c       | 4 ++++
 drivers/gpu/drm/i915/gem/i915_gem_context.h       | 6 ++++++
 drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 6 ++++++
 3 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 026999b34abd..ade01be32a4a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -721,6 +721,10 @@ __create_context(struct drm_i915_private *i915)
 	ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_NORMAL);
 	mutex_init(&ctx->mutex);
 
+	ctx->async.width = rounddown_pow_of_two(num_online_cpus());
+	ctx->async.context = dma_fence_context_alloc(ctx->async.width);
+	ctx->async.width--;
+
 	spin_lock_init(&ctx->stale.lock);
 	INIT_LIST_HEAD(&ctx->stale.engines);
 
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index 57b7ae2893e1..0919694f4514 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -134,6 +134,12 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
 				       struct drm_file *file);
 
+static inline u64 i915_gem_context_async_id(struct i915_gem_context *ctx)
+{
+	return (ctx->async.context +
+		(atomic_fetch_inc(&ctx->async.cur) & ctx->async.width));
+}
+
 static inline struct i915_gem_context *
 i915_gem_context_get(struct i915_gem_context *ctx)
 {
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index 28760bd03265..5f5cfa3a3e9b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -85,6 +85,12 @@ struct i915_gem_context {
 
 	struct intel_timeline *timeline;
 
+	struct {
+		u64 context;
+		atomic_t cur;
+		unsigned int width;
+	} async;
+
 	/**
 	 * @vm: unique address space (GTT)
 	 *
-- 
2.20.1

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  parent reply	other threads:[~2020-03-16 11:42 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-16 11:42 [Intel-gfx] [PATCH 01/15] drm/i915: Move GGTT fence registers under gt/ Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 02/15] drm/i915/gt: Pull restoration of GGTT fences underneath the GT Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 03/15] drm/i915: Remove manual save/resume of fence register state Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 04/15] drm/i915/gt: Allocate i915_fence_reg array Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 05/15] drm/i915/gt: Only wait for GPU activity before unbinding a GGTT fence Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 06/15] drm/i915/gt: Store the fence details on the fence Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 07/15] drm/i915/gt: Make fence revocation unequivocal Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 08/15] drm/i915/gem: Drop cached obj->bind_count Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 09/15] drm/i915: Immediately execute the fenced work Chris Wilson
2020-03-16 11:42 ` Chris Wilson [this message]
2020-03-16 11:42 ` [Intel-gfx] [PATCH 11/15] drm/i915: Export a preallocate variant of i915_active_acquire() Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 12/15] drm/i915/gem: Split eb_vma into its own allocation Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 13/15] drm/i915/gem: Separate the ww_mutex walker into its own list Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 14/15] drm/i915/gem: Asynchronous GTT unbinding Chris Wilson
2020-03-16 11:42 ` [Intel-gfx] [PATCH 15/15] drm/i915/gem: Bind the fence async for execbuf Chris Wilson
2020-03-16 20:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/15] drm/i915: Move GGTT fence registers under gt/ Patchwork
2020-03-16 20:54 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2020-03-16 21:02 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

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