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From: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v19 4/8] drm/i915: Refactor intel_can_enable_sagv
Date: Thu, 19 Mar 2020 15:09:48 +0200	[thread overview]
Message-ID: <20200319130948.GB29594@intel.com> (raw)
In-Reply-To: <20200318125055.GX13686@intel.com>

On Wed, Mar 18, 2020 at 02:50:55PM +0200, Ville Syrjälä wrote:
> On Wed, Mar 18, 2020 at 11:52:13AM +0000, Lisovskiy, Stanislav wrote:
> > >> @@ -5829,6 +6068,10 @@ skl_compute_wm(struct intel_atomic_state *state)
> > >>                        return ret;
> > >>        }
> > >>
> > >> +     ret = intel_compute_sagv_mask(state);
> > >> +     if (ret)
> > >> +             return ret;
> > 
> > > This seems too early. We haven't even computed the ddb yet.
> > 
> > 
> > I was thinking about our discussion last week and actually I think there are simply two ways how
> > 
> > to do it.
> > 
> > 
> > 1) What I do here is: calculate minimum amount required to fit SAGV wm levels into ddb and
> > 
> > based on that do the ddb allocation accordingly. I.e it is not to early because actually we have
> > 
> > already wm levels for sagv and non-sagv calculated - we already can check if it can fit into L0
> > 
> > and then act accordingly.
> > 
> > However one thing to consider here: as you said besides the minimal requirements for each plane
> > 
> > (with or without sagv) there is an extra space being allocated in proportion to plane data rate,
> > 
> > however here we are actually hitting the prioritization issue - i.e we need to decide whether
> > 
> > it is more important to have SAGV or to have more extra space allocated to different planes
> > 
> > proportionally to their needs.
> > 
> > So in this first approach we always first determine if we fit into minimum SAGV reqs, turn it
> > 
> > on if we do and then rest of extra space is allocated among the planes in proportion to data rate.
> > 
> > So that way we would be more often power efficient but but planes get less extra ddb space.
> > 
> > 
> > 2) In your approach we should calculate ddb first, allocate extra space proportionally to plane
> > 
> > data rate needs and only then check if all planes got enough space for L0 SAGV wm after that.
> > 
> > Then we actually don't even need skl_plane_wm_level accessor, because we first would be allocating
> > 
> > using normal wm levels + extra ddb and only then check if all planes fit into SAGV requirement -
> > 
> > because that extra space is not actually distributed evenly but in proportion to data rate of each
> > 
> > plane, which means that some planes might lack space for SAGV theoretically, because some might be
> > 
> > getting more or less depending on the data_rate/total_data_rate ratio.
> > 
> > 
> > My position is such that I'm really not like "my approach should always win" here, but more searching for
> > 
> > solution which is more correct from product point of view.
> > 
> > 
> > Also could be that it doesn't really matter which approach we do take now,, but matter more like
> > 
> > that how fast we deliver.  Because the actual outcome difference between two
> > 
> > might be minor, while time overhead for changing the approach could be major.
> 
> Pls fix your MUA. Really hard to read this.
> 
> -- 
> Ville Syrjälä
> Intel

I was thinking about our discussion last week and actually I think there are simply two ways how
to do it.

1) What I do here is: calculate minimum amount required to fit SAGV wm levels into ddb and
based on that do the ddb allocation accordingly. I.e it is not to early because actually we have
already wm levels for sagv and non-sagv calculated - we already can check if it can fit into L0
and then act accordingly.
However one thing to consider here: as you said besides the minimal requirements for each plane
(with or without sagv) there is an extra space being allocated in proportion to plane data rate,
however here we are actually hitting the prioritization issue - i.e we need to decide whether
it is more important to have SAGV or to have more extra space allocated to different planes
proportionally to their needs.
So in this first approach we always first determine if we fit into minimum SAGV reqs, turn it
on if we do and then rest of extra space is allocated among the planes in proportion to data rate.
So that way we would be more often power efficient but but planes get less extra ddb space.

2) In your approach we should calculate ddb first, allocate extra space proportionally to plane
data rate needs and only then check if all planes got enough space for L0 SAGV wm after that.
Then we actually don't even need skl_plane_wm_level accessor, because we first would be allocating
using normal wm levels + extra ddb and only then check if all planes fit into SAGV requirement -
because that extra space is not actually distributed evenly but in proportion to data rate of each
plane, which means that some planes might lack space for SAGV theoretically, because some might be
getting more or less depending on the data_rate/total_data_rate ratio.

My position is such that I'm really not like "my approach should always win" here, but more searching for
solution which is more correct from product point of view.

Also could be that it doesn't really matter which approach we do take now,, but matter more like
that how fast we deliver.  Because the actual outcome difference between two
might be minor, while time overhead for changing the approach could be major.

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  reply	other threads:[~2020-03-19 13:13 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-09 16:11 [Intel-gfx] [PATCH v19 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
2020-03-09 16:11 ` [Intel-gfx] [PATCH v19 1/8] drm/i915: Start passing latency as parameter Stanislav Lisovskiy
2020-03-10 14:32   ` Ville Syrjälä
2020-03-10 14:54     ` Lisovskiy, Stanislav
2020-03-10 20:44       ` Ville Syrjälä
2020-03-11  9:16   ` Stanislav Lisovskiy
2020-03-09 16:11 ` [Intel-gfx] [PATCH v19 2/8] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
     [not found]   ` <20200311160727.GA13686@intel.com>
2020-03-13  8:42     ` Lisovskiy, Stanislav
2020-03-09 16:11 ` [Intel-gfx] [PATCH v19 3/8] drm/i915: Add intel_bw_get_*_state helpers Stanislav Lisovskiy
     [not found]   ` <20200311160854.GB13686@intel.com>
2020-03-13  8:49     ` Lisovskiy, Stanislav
2020-03-13 13:26       ` Ville Syrjälä
2020-03-13 13:57         ` Lisovskiy, Stanislav
2020-03-13 14:14           ` Ville Syrjälä
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 4/8] drm/i915: Refactor intel_can_enable_sagv Stanislav Lisovskiy
2020-03-11  9:13   ` Stanislav Lisovskiy
     [not found]   ` <20200311163130.GC13686@intel.com>
2020-03-18 11:52     ` Lisovskiy, Stanislav
2020-03-18 12:50       ` Ville Syrjälä
2020-03-19 13:09         ` Lisovskiy, Stanislav [this message]
2020-03-20 12:51     ` Lisovskiy, Stanislav
2020-03-23 14:18       ` Ville Syrjälä
2020-03-23 14:36         ` Lisovskiy, Stanislav
2020-03-23 14:50           ` Ville Syrjälä
2020-03-23 14:58             ` Lisovskiy, Stanislav
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 5/8] drm/i915: Added required new PCode commands Stanislav Lisovskiy
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 6/8] drm/i915: Rename bw_state to new_bw_state Stanislav Lisovskiy
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 7/8] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 8/8] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
2020-03-09 16:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support Patchwork
2020-03-10 13:58 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-03-11 12:54 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Refactor Gen11+ SAGV support (rev3) Patchwork
2020-03-11 14:20   ` Lisovskiy, Stanislav
2020-03-11 19:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Refactor Gen11+ SAGV support (rev4) Patchwork

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