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From: Vipin Anand <vipin.anand@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 6/7] drm/i915/display: Reduce blanking to support 4k60@10bpp for LSPCON
Date: Fri, 27 Mar 2020 11:41:09 +0530
Message-ID: <20200327061110.17371-7-vipin.anand@intel.com> (raw)
In-Reply-To: <20200327061110.17371-1-vipin.anand@intel.com>

From: Uma Shankar <uma.shankar@intel.com>

Blanking needs to be reduced to incorporate DP and HDMI timing/link
bandwidth limitations for CEA modes (4k@60 at 10 bpp). DP can drive
17.28Gbs while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps.
This will cause mode to blank out. Reduced Htotal by shortening the
back porch and front porch within permissible limits.

v2: This is marked as Not for merge and the responsibilty to program
these custom timings will be on userspace. This patch is just for
reference purposes. This is based on Ville's recommendation.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c7424e2a04a3..3ab1fadb2ea3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -616,9 +616,11 @@ intel_dp_mode_valid(struct drm_connector *connector,
 {
 	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 	struct intel_connector *intel_connector = to_intel_connector(connector);
+	struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector);
 	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
 	int target_clock = mode->clock;
+	struct intel_lspcon *lspcon = enc_to_intel_lspcon(intel_encoder);
 	int max_rate, mode_rate, max_lanes, max_link_clock;
 	int max_dotclk;
 	u16 dsc_max_output_bpp = 0;
@@ -638,6 +640,20 @@ intel_dp_mode_valid(struct drm_connector *connector,
 
 		target_clock = fixed_mode->clock;
 	}
+	/*
+	 * Reducing Blanking to incorporate DP and HDMI timing/link bandwidth
+	 * limitations for CEA modes (4k@60 at 10 bpp). DP can drive 17.28Gbs
+	 * while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will
+	 * cause mode to blank out. Reduced Htotal by shortening the back porch
+	 * and front porch within permissible limits.
+	 */
+	if (lspcon->active && lspcon->hdr_supported &&
+	    mode->clock > 570000) {
+		mode->clock = 570000;
+		mode->htotal -= 180;
+		mode->hsync_start -= 72;
+		mode->hsync_end -= 72;
+	}
 
 	max_link_clock = intel_dp_max_link_rate(intel_dp);
 	max_lanes = intel_dp_max_lane_count(intel_dp);
-- 
2.26.0

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  parent reply index

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-27  6:11 [Intel-gfx] [PATCH v2 0/7] Enable HDR on Gen9 devices with lspcon hdr capability Vipin Anand
2020-03-27  6:11 ` [Intel-gfx] [PATCH v2 1/7] drm/i915/display: Add HDR Capability detection for LSPCON Vipin Anand
2020-03-27  6:08   ` Anshuman Gupta
2020-03-27  6:11 ` [Intel-gfx] [PATCH v2 2/7] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon Vipin Anand
2020-03-27  6:11 ` [Intel-gfx] [PATCH v2 3/7] drm/i915/display: Attach HDR property for capable Gen9 devices Vipin Anand
2020-03-27  6:11 ` [Intel-gfx] [PATCH v2 4/7] drm/i915/display: Set HDR Infoframe for HDR capable LSPCON devices Vipin Anand
2020-03-27  6:11 ` [Intel-gfx] [PATCH v2 5/7] drm/i915/display: Enable BT2020 for HDR on " Vipin Anand
2020-03-27  6:11 ` Vipin Anand [this message]
2020-03-27  6:11 ` [Intel-gfx] [PATCH v2 7/7] drm:i915:display: add checks for Gen9 devices with hdr capability Vipin Anand
2020-03-27  6:33 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Enable HDR on Gen9 devices with lspcon hdr capability (rev2) Patchwork

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