From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 07/22] drm/i915/rkl: Limit number of universal planes to 5
Date: Mon, 4 May 2020 15:52:12 -0700 [thread overview]
Message-ID: <20200504225227.464666-8-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20200504225227.464666-1-matthew.d.roper@intel.com>
RKL only has five universal planes, plus a cursor. Since the
bottom-most universal plane is considered the primary plane, set the
number of sprites available on this platform to 4.
In general, the plane capabilities of the remaining planes stay the same
as TGL. However the NV12 Y-plane support moves down to the new top two
planes and now only the bottom three planes can be used for NV12 UV.
Bspec: 49181
Bspec: 49251
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++++-
drivers/gpu/drm/i915/display/intel_sprite.c | 17 ++++++++++++++++-
drivers/gpu/drm/i915/display/intel_sprite.h | 11 ++---------
drivers/gpu/drm/i915/i915_irq.c | 4 +++-
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
drivers/gpu/drm/i915/intel_device_info.c | 5 ++++-
6 files changed, 35 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index fd6d63b03489..7d7a5b66f2cb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12500,7 +12500,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
continue;
for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
- if (!icl_is_nv12_y_plane(linked->id))
+ if (!icl_is_nv12_y_plane(dev_priv, linked->id))
continue;
if (crtc_state->active_planes & BIT(linked->id))
@@ -12546,6 +12546,10 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
else if (linked->id == PLANE_SPRITE4)
plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
+ else if (linked->id == PLANE_SPRITE3)
+ plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
+ else if (linked->id == PLANE_SPRITE2)
+ plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
else
MISSING_CASE(linked->id);
}
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 0000ec7055f7..571c36f929bd 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -333,6 +333,21 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
return 0;
}
+static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
+{
+ if (IS_ROCKETLAKE(i915))
+ return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
+ else
+ return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
+}
+
+bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
+ enum plane_id plane_id)
+{
+ return INTEL_GEN(dev_priv) >= 11 &&
+ icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id);
+}
+
bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id)
{
return INTEL_GEN(dev_priv) >= 11 &&
@@ -3003,7 +3018,7 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
if (icl_is_hdr_plane(dev_priv, plane_id)) {
*num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
return icl_hdr_plane_formats;
- } else if (icl_is_nv12_y_plane(plane_id)) {
+ } else if (icl_is_nv12_y_plane(dev_priv, plane_id)) {
*num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats);
return icl_sdr_y_plane_formats;
} else {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.h b/drivers/gpu/drm/i915/display/intel_sprite.h
index 5eeaa92420d1..cd2104ba1ca1 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.h
+++ b/drivers/gpu/drm/i915/display/intel_sprite.h
@@ -32,21 +32,14 @@ struct intel_plane *
skl_universal_plane_create(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id);
-static inline bool icl_is_nv12_y_plane(enum plane_id id)
-{
- /* Don't need to do a gen check, these planes are only available on gen11 */
- if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
- return true;
-
- return false;
-}
-
static inline u8 icl_hdr_plane_mask(void)
{
return BIT(PLANE_PRIMARY) |
BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
}
+bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
+ enum plane_id plane_id);
bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index bd722d0650c8..622986759ec6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2221,7 +2221,9 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
{
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_ROCKETLAKE(dev_priv))
+ return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
+ else if (INTEL_GEN(dev_priv) >= 11)
return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
else if (INTEL_GEN(dev_priv) >= 9)
return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fd9f2904d93c..59c1d527cf13 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6907,6 +6907,8 @@ enum {
#define _PLANE_CUS_CTL_1_A 0x701c8
#define _PLANE_CUS_CTL_2_A 0x702c8
#define PLANE_CUS_ENABLE (1 << 31)
+#define PLANE_CUS_PLANE_4_RKL (0 << 30)
+#define PLANE_CUS_PLANE_5_RKL (1 << 30)
#define PLANE_CUS_PLANE_6 (0 << 30)
#define PLANE_CUS_PLANE_7 (1 << 30)
#define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
@@ -7573,6 +7575,9 @@ enum {
GEN11_PIPE_PLANE7_FAULT | \
GEN11_PIPE_PLANE6_FAULT | \
GEN11_PIPE_PLANE5_FAULT)
+#define RKL_DE_PIPE_IRQ_FAULT_ERRORS \
+ (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
+ GEN11_PIPE_PLANE5_FAULT)
#define GEN8_DE_PORT_ISR _MMIO(0x44440)
#define GEN8_DE_PORT_IMR _MMIO(0x44444)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 9862c1185059..a5a92c2728db 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -934,7 +934,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_ROCKETLAKE(dev_priv))
+ for_each_pipe(dev_priv, pipe)
+ runtime->num_sprites[pipe] = 4;
+ else if (INTEL_GEN(dev_priv) >= 11)
for_each_pipe(dev_priv, pipe)
runtime->num_sprites[pipe] = 6;
else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
--
2.24.1
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next prev parent reply other threads:[~2020-05-04 22:52 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 01/22] drm/i915/rkl: Add RKL platform info and PCI ids Matt Roper
2020-05-07 11:18 ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support Matt Roper
2020-05-06 11:51 ` Srivatsa, Anusha
2020-05-19 23:57 ` Lucas De Marchi
2020-05-20 9:30 ` Borislav Petkov
2020-05-20 17:49 ` Lucas De Marchi
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 03/22] drm/i915/rkl: Re-use TGL GuC/HuC firmware Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 04/22] drm/i915/rkl: Load DMC firmware for Rocket Lake Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 05/22] drm/i915/rkl: Add PCH support Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 06/22] drm/i915/rkl: Update memory bandwidth parameters Matt Roper
2020-05-07 12:24 ` Ville Syrjälä
2020-05-04 22:52 ` Matt Roper [this message]
2020-05-07 12:10 ` [Intel-gfx] [PATCH v2 07/22] drm/i915/rkl: Limit number of universal planes to 5 Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 08/22] drm/i915/rkl: Add power well support Matt Roper
2020-05-05 4:50 ` Anshuman Gupta
2020-05-05 14:39 ` Matt Roper
2020-05-05 16:09 ` Imre Deak
2020-05-06 12:13 ` Anshuman Gupta
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 09/22] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B Matt Roper
2020-05-06 13:49 ` Srivatsa, Anusha
2020-05-06 16:49 ` Matt Roper
2020-05-07 11:22 ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 11/22] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs Matt Roper
2020-05-07 11:38 ` Srivatsa, Anusha
2020-05-07 11:59 ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 13/22] drm/i915/rkl: Setup ports/phys Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 14/22] drm/i915/rkl: provide port/phy mapping for vbt Matt Roper
2020-05-07 12:04 ` Ville Syrjälä
2020-05-07 18:05 ` Matt Roper
2020-05-08 9:44 ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 15/22] drm/i915/rkl: Add DDC pin mapping Matt Roper
2020-05-06 9:19 ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 16/22] drm/i915/rkl: Don't try to access transcoder D Matt Roper
2020-05-06 20:34 ` Matt Roper
2020-05-06 21:21 ` [Intel-gfx] [PATCH v3 " Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 17/22] drm/i915/rkl: Don't try to read out DSI transcoders Matt Roper
2020-05-07 11:58 ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 18/22] drm/i915/rkl: Handle comp master/slave relationships for PHYs Matt Roper
2020-05-06 9:20 ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 19/22] drm/i915/rkl: Add DPLL4 support Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 20/22] drm/i915/rkl: Handle HTI Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 21/22] drm/i915/rkl: Disable PSR2 Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 22/22] drm/i915/rkl: Add initial workarounds Matt Roper
2020-05-04 23:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Rocket Lake (rev4) Patchwork
2020-05-04 23:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-05 13:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-05-06 22:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Rocket Lake (rev5) Patchwork
2020-05-06 22:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-07 2:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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