From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 3/7] drm/i915: Fix ivb cpu edp vswing
Date: Tue, 12 May 2020 20:41:41 +0300 [thread overview]
Message-ID: <20200512174145.3186-4-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20200512174145.3186-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
According to the DP spec supporting vswing 1 + preemph 2 is
mandatory. We don't have the hw settings for that though. In
order to pretend to follow the DP spec let's just select
vswing 0 + preemph 2 in this case (the DP spec says to use
the requested preemph in preference to the vswing when the
requested values aren't supported).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0924e041e1bf..4952918d0904 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3960,8 +3960,6 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
(HAS_PCH_SPLIT(dev_priv) && port != PORT_A))
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
- else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
- return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
else
return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
}
@@ -3988,16 +3986,6 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
default:
return DP_TRAIN_PRE_EMPH_LEVEL_0;
}
- } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
- switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
- case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
- return DP_TRAIN_PRE_EMPH_LEVEL_2;
- case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
- case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
- return DP_TRAIN_PRE_EMPH_LEVEL_1;
- default:
- return DP_TRAIN_PRE_EMPH_LEVEL_0;
- }
} else {
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
@@ -4293,6 +4281,7 @@ static u32 ivb_cpu_edp_signal_levels(u8 train_set)
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
+ case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
return EDP_LINK_TRAIN_400MV_6DB_IVB;
case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
--
2.26.2
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next prev parent reply other threads:[~2020-05-12 17:41 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-12 17:41 [Intel-gfx] [PATCH 0/7] drm/i915: DP vswing/preemph fixes Ville Syrjala
2020-05-12 17:41 ` [Intel-gfx] [PATCH 1/7] drm/i915: Fix cpt/ppt max pre-emphasis Ville Syrjala
2020-05-30 1:30 ` Souza, Jose
2020-05-12 17:41 ` [Intel-gfx] [PATCH 2/7] drm/i915: Fix ibx max vswing/preemph Ville Syrjala
2020-06-01 20:23 ` Souza, Jose
2020-05-12 17:41 ` Ville Syrjala [this message]
2020-05-30 1:38 ` [Intel-gfx] [PATCH 3/7] drm/i915: Fix ivb cpu edp vswing Souza, Jose
2020-05-12 17:41 ` [Intel-gfx] [PATCH 4/7] drm/i915: Add {preemph, voltage}_max() vfuncs Ville Syrjala
2020-05-15 19:09 ` Manasi Navare
2020-05-12 17:41 ` [Intel-gfx] [PATCH 5/7] drm/i915: Reverse preemph vs. voltage swing preference Ville Syrjala
2020-05-15 19:18 ` Manasi Navare
2020-05-15 19:59 ` Ville Syrjälä
2020-05-18 18:20 ` Manasi Navare
2020-05-12 17:41 ` [Intel-gfx] [PATCH 6/7] drm/i915: Fix DP_TRAIN_MAX_{PRE_EMPHASIS, SWING}_REACHED handling Ville Syrjala
2020-06-25 21:06 ` Imre Deak
2020-05-12 17:41 ` [Intel-gfx] [PATCH 7/7] drm/i915: Replace some hand rolled max()s Ville Syrjala
2020-05-15 19:21 ` Manasi Navare
2020-05-12 18:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: DP vswing/preemph fixes Patchwork
2020-05-12 20:11 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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