* [Intel-gfx] [PATCH 1/2] drm/i915: Remove PIN_UPDATE for i915_vma_pin
@ 2020-05-16 17:07 Chris Wilson
2020-05-16 17:07 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Stop cross-poluting PIN_GLOBAL with PIN_USER with no-ppgtt Chris Wilson
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Chris Wilson @ 2020-05-16 17:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
As we no longer use PIN_UPDATE (since commit 7d0aa0db4375 ("drm/i915/gem:
Unbind all current vma on changing cache-level")) we can remove
PIN_UPDATE itself. The benefit is just in simplifing the vma bind.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 142 ------------------
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 -
drivers/gpu/drm/i915/i915_vma.c | 9 +-
3 files changed, 3 insertions(+), 149 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index c9988b6d5c88..a0ed2fab0ff3 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1409,147 +1409,6 @@ static int igt_ppgtt_sanity_check(void *arg)
return err;
}
-static int igt_ppgtt_pin_update(void *arg)
-{
- struct i915_gem_context *ctx = arg;
- struct drm_i915_private *dev_priv = ctx->i915;
- unsigned long supported = INTEL_INFO(dev_priv)->page_sizes;
- struct drm_i915_gem_object *obj;
- struct i915_gem_engines_iter it;
- struct i915_address_space *vm;
- struct intel_context *ce;
- struct i915_vma *vma;
- unsigned int flags = PIN_USER | PIN_OFFSET_FIXED;
- unsigned int n;
- int first, last;
- int err = 0;
-
- /*
- * Make sure there's no funny business when doing a PIN_UPDATE -- in the
- * past we had a subtle issue with being able to incorrectly do multiple
- * alloc va ranges on the same object when doing a PIN_UPDATE, which
- * resulted in some pretty nasty bugs, though only when using
- * huge-gtt-pages.
- */
-
- vm = i915_gem_context_get_vm_rcu(ctx);
- if (!i915_vm_is_4lvl(vm)) {
- pr_info("48b PPGTT not supported, skipping\n");
- goto out_vm;
- }
-
- first = ilog2(I915_GTT_PAGE_SIZE_64K);
- last = ilog2(I915_GTT_PAGE_SIZE_2M);
-
- for_each_set_bit_from(first, &supported, last + 1) {
- unsigned int page_size = BIT(first);
-
- obj = i915_gem_object_create_internal(dev_priv, page_size);
- if (IS_ERR(obj)) {
- err = PTR_ERR(obj);
- goto out_vm;
- }
-
- vma = i915_vma_instance(obj, vm, NULL);
- if (IS_ERR(vma)) {
- err = PTR_ERR(vma);
- goto out_put;
- }
-
- err = i915_vma_pin(vma, SZ_2M, 0, flags);
- if (err)
- goto out_put;
-
- if (vma->page_sizes.sg < page_size) {
- pr_info("Unable to allocate page-size %x, finishing test early\n",
- page_size);
- goto out_unpin;
- }
-
- err = igt_check_page_sizes(vma);
- if (err)
- goto out_unpin;
-
- if (vma->page_sizes.gtt != page_size) {
- dma_addr_t addr = i915_gem_object_get_dma_address(obj, 0);
-
- /*
- * The only valid reason for this to ever fail would be
- * if the dma-mapper screwed us over when we did the
- * dma_map_sg(), since it has the final say over the dma
- * address.
- */
- if (IS_ALIGNED(addr, page_size)) {
- pr_err("page_sizes.gtt=%u, expected=%u\n",
- vma->page_sizes.gtt, page_size);
- err = -EINVAL;
- } else {
- pr_info("dma address misaligned, finishing test early\n");
- }
-
- goto out_unpin;
- }
-
- err = i915_vma_bind(vma, I915_CACHE_NONE, PIN_UPDATE, NULL);
- if (err)
- goto out_unpin;
-
- i915_vma_unpin(vma);
- i915_gem_object_put(obj);
- }
-
- obj = i915_gem_object_create_internal(dev_priv, PAGE_SIZE);
- if (IS_ERR(obj)) {
- err = PTR_ERR(obj);
- goto out_vm;
- }
-
- vma = i915_vma_instance(obj, vm, NULL);
- if (IS_ERR(vma)) {
- err = PTR_ERR(vma);
- goto out_put;
- }
-
- err = i915_vma_pin(vma, 0, 0, flags);
- if (err)
- goto out_put;
-
- /*
- * Make sure we don't end up with something like where the pde is still
- * pointing to the 2M page, and the pt we just filled-in is dangling --
- * we can check this by writing to the first page where it would then
- * land in the now stale 2M page.
- */
-
- n = 0;
- for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
- if (!intel_engine_can_store_dword(ce->engine))
- continue;
-
- err = gpu_write(ce, vma, n++, 0xdeadbeaf);
- if (err)
- break;
- }
- i915_gem_context_unlock_engines(ctx);
- if (err)
- goto out_unpin;
-
- while (n--) {
- err = cpu_check(obj, n, 0xdeadbeaf);
- if (err)
- goto out_unpin;
- }
-
-out_unpin:
- i915_vma_unpin(vma);
-out_put:
- i915_gem_object_put(obj);
-out_vm:
- i915_vm_put(vm);
-
- return err;
-}
-
static int igt_tmpfs_fallback(void *arg)
{
struct i915_gem_context *ctx = arg;
@@ -1760,7 +1619,6 @@ int i915_gem_huge_page_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(igt_shrink_thp),
- SUBTEST(igt_ppgtt_pin_update),
SUBTEST(igt_tmpfs_fallback),
SUBTEST(igt_ppgtt_smoke_huge),
SUBTEST(igt_ppgtt_sanity_check),
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index f6226df9f972..c9b0ee5e1d23 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -42,7 +42,6 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
#define PIN_OFFSET_BIAS BIT_ULL(6)
#define PIN_OFFSET_FIXED BIT_ULL(7)
-#define PIN_UPDATE BIT_ULL(9)
#define PIN_GLOBAL BIT_ULL(10) /* I915_VMA_GLOBAL_BIND */
#define PIN_USER BIT_ULL(11) /* I915_VMA_LOCAL_BIND */
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index fc14ebf9a0b7..22198b758459 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -397,17 +397,15 @@ int i915_vma_bind(struct i915_vma *vma,
vma_flags = atomic_read(&vma->flags);
vma_flags &= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
- if (flags & PIN_UPDATE)
- bind_flags |= vma_flags;
- else
- bind_flags &= ~vma_flags;
+
+ bind_flags &= ~vma_flags;
if (bind_flags == 0)
return 0;
GEM_BUG_ON(!vma->pages);
trace_i915_vma_bind(vma, bind_flags);
- if (work && (bind_flags & ~vma_flags) & vma->vm->bind_async_flags) {
+ if (work && bind_flags & vma->vm->bind_async_flags) {
struct dma_fence *prev;
work->vma = vma;
@@ -868,7 +866,6 @@ int i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
BUILD_BUG_ON(PIN_GLOBAL != I915_VMA_GLOBAL_BIND);
BUILD_BUG_ON(PIN_USER != I915_VMA_LOCAL_BIND);
- GEM_BUG_ON(flags & PIN_UPDATE);
GEM_BUG_ON(!(flags & (PIN_USER | PIN_GLOBAL)));
/* First try and grab the pin without rebinding the vma */
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/gt: Stop cross-poluting PIN_GLOBAL with PIN_USER with no-ppgtt
2020-05-16 17:07 [Intel-gfx] [PATCH 1/2] drm/i915: Remove PIN_UPDATE for i915_vma_pin Chris Wilson
@ 2020-05-16 17:07 ` Chris Wilson
2020-05-18 9:39 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Remove PIN_UPDATE for i915_vma_pin Patchwork
2020-05-21 14:36 ` [Intel-gfx] [PATCH 1/2] " Matthew Auld
2 siblings, 0 replies; 4+ messages in thread
From: Chris Wilson @ 2020-05-16 17:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
In order to keep userptr distinct from ggtt mmaps in the eyes of
lockdep, we need to avoid marking those userptr vma as PIN_GLOBAL. (So
long as we comply with only using them as local PIN_USER!)
References: https://gitlab.freedesktop.org/drm/intel/-/issues/1880
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 66165b10256e..325df6b05624 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -424,22 +424,17 @@ static int ggtt_bind_vma(struct i915_vma *vma,
struct drm_i915_gem_object *obj = vma->obj;
u32 pte_flags;
+ if (i915_vma_is_bound(vma, I915_VMA_LOCAL_BIND | I915_VMA_GLOBAL_BIND))
+ return 0;
+
/* Applicable to VLV (gen8+ do not support RO in the GGTT) */
pte_flags = 0;
if (i915_gem_object_is_readonly(obj))
pte_flags |= PTE_READ_ONLY;
vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
-
vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
- /*
- * Without aliasing PPGTT there's no difference between
- * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
- * upgrade to both bound if we bind either to avoid double-binding.
- */
- atomic_or(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND, &vma->flags);
-
return 0;
}
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Remove PIN_UPDATE for i915_vma_pin
2020-05-16 17:07 [Intel-gfx] [PATCH 1/2] drm/i915: Remove PIN_UPDATE for i915_vma_pin Chris Wilson
2020-05-16 17:07 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Stop cross-poluting PIN_GLOBAL with PIN_USER with no-ppgtt Chris Wilson
@ 2020-05-18 9:39 ` Patchwork
2020-05-21 14:36 ` [Intel-gfx] [PATCH 1/2] " Matthew Auld
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2020-05-18 9:39 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: Remove PIN_UPDATE for i915_vma_pin
URL : https://patchwork.freedesktop.org/series/77323/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8493 -> Patchwork_17681
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_17681 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17681, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17681/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17681:
### IGT changes ###
#### Possible regressions ####
* igt@gem_tiled_pread_basic:
- fi-bsw-nick: [PASS][1] -> [FAIL][2] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/fi-bsw-nick/igt@gem_tiled_pread_basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17681/fi-bsw-nick/igt@gem_tiled_pread_basic.html
* igt@i915_selftest@live@gt_lrc:
- fi-bsw-nick: [PASS][3] -> [DMESG-FAIL][4] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/fi-bsw-nick/igt@i915_selftest@live@gt_lrc.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17681/fi-bsw-nick/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@gt_mocs:
- fi-apl-guc: [PASS][5] -> [DMESG-FAIL][6] +5 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/fi-apl-guc/igt@i915_selftest@live@gt_mocs.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17681/fi-apl-guc/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@hangcheck:
- fi-apl-guc: [PASS][7] -> [FAIL][8] +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/fi-apl-guc/igt@i915_selftest@live@hangcheck.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17681/fi-apl-guc/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@mman:
- fi-bsw-kefka: [PASS][9] -> [DMESG-FAIL][10] +4 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/fi-bsw-kefka/igt@i915_selftest@live@mman.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17681/fi-bsw-kefka/igt@i915_selftest@live@mman.html
- fi-bsw-nick: [PASS][11] -> [INCOMPLETE][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/fi-bsw-nick/igt@i915_selftest@live@mman.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17681/fi-bsw-nick/igt@i915_selftest@live@mman.html
* igt@i915_selftest@live@reset:
- fi-bsw-kefka: [PASS][13] -> [FAIL][14] +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/fi-bsw-kefka/igt@i915_selftest@live@reset.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17681/fi-bsw-kefka/igt@i915_selftest@live@reset.html
Known issues
------------
Here are the changes found in Patchwork_17681 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_tiled_fence_blits@basic:
- fi-apl-guc: [PASS][15] -> [SKIP][16] ([fdo#109271]) +28 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/fi-apl-guc/igt@gem_tiled_fence_blits@basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17681/fi-apl-guc/igt@gem_tiled_fence_blits@basic.html
* igt@i915_pm_rps@basic-api:
- fi-bsw-nick: [PASS][17] -> [SKIP][18] ([fdo#109271]) +20 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/fi-bsw-nick/igt@i915_pm_rps@basic-api.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17681/fi-bsw-nick/igt@i915_pm_rps@basic-api.html
* igt@prime_vgem@basic-fence-read:
- fi-bsw-kefka: [PASS][19] -> [SKIP][20] ([fdo#109271]) +24 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/fi-bsw-kefka/igt@prime_vgem@basic-fence-read.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17681/fi-bsw-kefka/igt@prime_vgem@basic-fence-read.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-tgl-y: [INCOMPLETE][21] ([i915#1803]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8493/fi-tgl-y/igt@i915_selftest@live@execlists.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17681/fi-tgl-y/igt@i915_selftest@live@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1803]: https://gitlab.freedesktop.org/drm/intel/issues/1803
Participating hosts (51 -> 44)
------------------------------
Additional (1): fi-kbl-7560u
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_8493 -> Patchwork_17681
CI-20190529: 20190529
CI_DRM_8493: 47e0097b33017be45f6826ef82a1f535b81ab9a3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5657: 649eae5c905a7460b44305800f95db83a6dd47cb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17681: 97083f187a2cfa728684d37443440e1e4aaef143 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
97083f187a2c drm/i915/gt: Stop cross-poluting PIN_GLOBAL with PIN_USER with no-ppgtt
913f5e8c137e drm/i915: Remove PIN_UPDATE for i915_vma_pin
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17681/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Remove PIN_UPDATE for i915_vma_pin
2020-05-16 17:07 [Intel-gfx] [PATCH 1/2] drm/i915: Remove PIN_UPDATE for i915_vma_pin Chris Wilson
2020-05-16 17:07 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Stop cross-poluting PIN_GLOBAL with PIN_USER with no-ppgtt Chris Wilson
2020-05-18 9:39 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Remove PIN_UPDATE for i915_vma_pin Patchwork
@ 2020-05-21 14:36 ` Matthew Auld
2 siblings, 0 replies; 4+ messages in thread
From: Matthew Auld @ 2020-05-21 14:36 UTC (permalink / raw)
To: Chris Wilson; +Cc: Intel Graphics Development
On Sat, 16 May 2020 at 18:07, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> As we no longer use PIN_UPDATE (since commit 7d0aa0db4375 ("drm/i915/gem:
> Unbind all current vma on changing cache-level")) we can remove
> PIN_UPDATE itself. The benefit is just in simplifing the vma bind.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-05-21 14:37 UTC | newest]
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2020-05-16 17:07 [Intel-gfx] [PATCH 1/2] drm/i915: Remove PIN_UPDATE for i915_vma_pin Chris Wilson
2020-05-16 17:07 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Stop cross-poluting PIN_GLOBAL with PIN_USER with no-ppgtt Chris Wilson
2020-05-18 9:39 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Remove PIN_UPDATE for i915_vma_pin Patchwork
2020-05-21 14:36 ` [Intel-gfx] [PATCH 1/2] " Matthew Auld
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