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* [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake
@ 2020-05-04 22:52 Matt Roper
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 01/22] drm/i915/rkl: Add RKL platform info and PCI ids Matt Roper
                   ` (27 more replies)
  0 siblings, 28 replies; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx

Only minor changes since v1, but patchwork got confused by the updates,
so sending the whole series again to ensure proper CI testing.

v2 changes:
 - Drop the cdclk patch.  The bspec was updated since I originally wrote
   that and now RKL's table is identical to the one we use on TGL and
   ICL.  No RKL-specific driver changes are necessary now.
 - Fix a botched mask in the DPCLKA_CFGCR0 clock selection.

See the cover letter from v1 for other details:
  https://lists.freedesktop.org/archives/intel-gfx/2020-May/238498.html


Aditya Swarup (1):
  drm/i915/rkl: Don't try to read out DSI transcoders

José Roberto de Souza (1):
  drm/i915/rkl: Disable PSR2

Lucas De Marchi (1):
  drm/i915/rkl: provide port/phy mapping for vbt

Matt Roper (19):
  drm/i915/rkl: Add RKL platform info and PCI ids
  x86/gpu: add RKL stolen memory support
  drm/i915/rkl: Re-use TGL GuC/HuC firmware
  drm/i915/rkl: Load DMC firmware for Rocket Lake
  drm/i915/rkl: Add PCH support
  drm/i915/rkl: Update memory bandwidth parameters
  drm/i915/rkl: Limit number of universal planes to 5
  drm/i915/rkl: Add power well support
  drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2
  drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B
  drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
  drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs
  drm/i915/rkl: Setup ports/phys
  drm/i915/rkl: Add DDC pin mapping
  drm/i915/rkl: Don't try to access transcoder D
  drm/i915/rkl: Handle comp master/slave relationships for PHYs
  drm/i915/rkl: Add DPLL4 support
  drm/i915/rkl: Handle HTI
  drm/i915/rkl: Add initial workarounds

 arch/x86/kernel/early-quirks.c                |   1 +
 drivers/gpu/drm/i915/display/intel_bios.c     |  72 ++++--
 drivers/gpu/drm/i915/display/intel_bw.c       |  10 +-
 .../gpu/drm/i915/display/intel_combo_phy.c    |  55 +++--
 drivers/gpu/drm/i915/display/intel_csr.c      |  10 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  18 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  82 +++++--
 .../drm/i915/display/intel_display_power.c    | 229 ++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_dp.c       |   8 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  50 +++-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   1 +
 drivers/gpu/drm/i915/display/intel_hdmi.c     |  22 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  15 ++
 drivers/gpu/drm/i915/display/intel_sprite.c   |  22 +-
 drivers/gpu/drm/i915/display/intel_sprite.h   |  11 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     |   4 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |  88 ++++---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c      |   3 +
 drivers/gpu/drm/i915/i915_drv.h               |  13 +
 drivers/gpu/drm/i915/i915_irq.c               |  10 +-
 drivers/gpu/drm/i915/i915_pci.c               |  13 +
 drivers/gpu/drm/i915/i915_reg.h               |  35 ++-
 drivers/gpu/drm/i915/intel_device_info.c      |   6 +-
 drivers/gpu/drm/i915/intel_device_info.h      |   2 +
 drivers/gpu/drm/i915/intel_pch.c              |   8 +-
 include/drm/i915_pciids.h                     |   9 +
 26 files changed, 656 insertions(+), 141 deletions(-)

-- 
2.24.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 01/22] drm/i915/rkl: Add RKL platform info and PCI ids
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-07 11:18   ` Srivatsa, Anusha
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support Matt Roper
                   ` (26 subsequent siblings)
  27 siblings, 1 reply; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

Introduce the basic platform definition, macros, and PCI IDs.

Bspec: 44501
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Caz Yokoyama <caz.yokoyama@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Caz Yokoyama <caz.yokoyama@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          |  8 ++++++++
 drivers/gpu/drm/i915/i915_pci.c          | 10 ++++++++++
 drivers/gpu/drm/i915/intel_device_info.c |  1 +
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 include/drm/i915_pciids.h                |  9 +++++++++
 5 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6af69555733e..1ba77283123d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1406,6 +1406,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
 #define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
 #define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
+#define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 #define IS_BDW_ULT(dev_priv) \
@@ -1514,6 +1515,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_TGL_REVID(p, since, until) \
 	(IS_TIGERLAKE(p) && IS_REVID(p, since, until))
 
+#define RKL_REVID_A0		0x0
+#define RKL_REVID_B0		0x1
+#define RKL_REVID_C0		0x4
+
+#define IS_RKL_REVID(p, since, until) \
+	(IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
+
 #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)	(IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
 #define IS_GEN9_BC(dev_priv)	(IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1faf9d6ec0a4..5a470bab2214 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -863,6 +863,15 @@ static const struct intel_device_info tgl_info = {
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 };
 
+static const struct intel_device_info rkl_info = {
+	GEN12_FEATURES,
+	PLATFORM(INTEL_ROCKETLAKE),
+	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+	.require_force_probe = 1,
+	.engine_mask =
+		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
+};
+
 #define GEN12_DGFX_FEATURES \
 	GEN12_FEATURES, \
 	.is_dgfx = 1
@@ -941,6 +950,7 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_ICL_11_IDS(&icl_info),
 	INTEL_EHL_IDS(&ehl_info),
 	INTEL_TGL_12_IDS(&tgl_info),
+	INTEL_RKL_IDS(&rkl_info),
 	{0, 0, 0}
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 91bb7891c70c..9862c1185059 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -61,6 +61,7 @@ static const char * const platform_names[] = {
 	PLATFORM_NAME(ICELAKE),
 	PLATFORM_NAME(ELKHARTLAKE),
 	PLATFORM_NAME(TIGERLAKE),
+	PLATFORM_NAME(ROCKETLAKE),
 };
 #undef PLATFORM_NAME
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 69c9257c6c6a..a126984cef7f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -80,6 +80,7 @@ enum intel_platform {
 	INTEL_ELKHARTLAKE,
 	/* gen12 */
 	INTEL_TIGERLAKE,
+	INTEL_ROCKETLAKE,
 	INTEL_MAX_PLATFORMS
 };
 
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 662d8351c87a..bc989de2aac2 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -605,4 +605,13 @@
 	INTEL_VGA_DEVICE(0x9AD9, info), \
 	INTEL_VGA_DEVICE(0x9AF8, info)
 
+/* RKL */
+#define INTEL_RKL_IDS(info) \
+	INTEL_VGA_DEVICE(0x4C80, info), \
+	INTEL_VGA_DEVICE(0x4C8A, info), \
+	INTEL_VGA_DEVICE(0x4C8B, info), \
+	INTEL_VGA_DEVICE(0x4C8C, info), \
+	INTEL_VGA_DEVICE(0x4C90, info), \
+	INTEL_VGA_DEVICE(0x4C9A, info)
+
 #endif /* _I915_PCIIDS_H */
-- 
2.24.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 01/22] drm/i915/rkl: Add RKL platform info and PCI ids Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-06 11:51   ` Srivatsa, Anusha
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 03/22] drm/i915/rkl: Re-use TGL GuC/HuC firmware Matt Roper
                   ` (25 subsequent siblings)
  27 siblings, 1 reply; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

RKL re-uses the same stolen memory registers as TGL and ICL.

Bspec: 52055
Bspec: 49589
Bspec: 49636
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 arch/x86/kernel/early-quirks.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 2f9ec14be3b1..a4b5af03dcc1 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -550,6 +550,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
 	INTEL_ICL_11_IDS(&gen11_early_ops),
 	INTEL_EHL_IDS(&gen11_early_ops),
 	INTEL_TGL_12_IDS(&gen11_early_ops),
+	INTEL_RKL_IDS(&gen11_early_ops),
 };
 
 struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
-- 
2.24.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 03/22] drm/i915/rkl: Re-use TGL GuC/HuC firmware
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 01/22] drm/i915/rkl: Add RKL platform info and PCI ids Matt Roper
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 04/22] drm/i915/rkl: Load DMC firmware for Rocket Lake Matt Roper
                   ` (24 subsequent siblings)
  27 siblings, 0 replies; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx

RKL uses the same GuC and HuC as TGL and should load the same firmwares.

Bspec: 50668
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index e1caae93996d..9b6218128d09 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -47,8 +47,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
  * TGL 35.2 is interface-compatible with 33.0 for previous Gens. The deltas
  * between 33.0 and 35.2 are only related to new additions to support new Gen12
  * features.
+ *
+ * Note that RKL uses the same firmware as TGL.
  */
 #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
+	fw_def(ROCKETLAKE,  0, guc_def(tgl, 35, 2, 0), huc_def(tgl,  7, 0, 12)) \
 	fw_def(TIGERLAKE,   0, guc_def(tgl, 35, 2, 0), huc_def(tgl,  7, 0, 12)) \
 	fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl,  9, 0, 0)) \
 	fw_def(ICELAKE,     0, guc_def(icl, 33, 0, 0), huc_def(icl,  9, 0, 0)) \
-- 
2.24.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 04/22] drm/i915/rkl: Load DMC firmware for Rocket Lake
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (2 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 03/22] drm/i915/rkl: Re-use TGL GuC/HuC firmware Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 05/22] drm/i915/rkl: Add PCH support Matt Roper
                   ` (23 subsequent siblings)
  27 siblings, 0 replies; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_csr.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index 3112572cfb7d..319932b03e88 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -40,6 +40,10 @@
 
 #define GEN12_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE
 
+#define RKL_CSR_PATH			"i915/rkl_dmc_ver2_01.bin"
+#define RKL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 1)
+MODULE_FIRMWARE(RKL_CSR_PATH);
+
 #define TGL_CSR_PATH			"i915/tgl_dmc_ver2_06.bin"
 #define TGL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 6)
 #define TGL_CSR_MAX_FW_SIZE		0x6000
@@ -682,7 +686,11 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 	 */
 	intel_csr_runtime_pm_get(dev_priv);
 
-	if (INTEL_GEN(dev_priv) >= 12) {
+	if (IS_ROCKETLAKE(dev_priv)) {
+		csr->fw_path = RKL_CSR_PATH;
+		csr->required_version = RKL_CSR_VERSION_REQUIRED;
+		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+	} else if (INTEL_GEN(dev_priv) >= 12) {
 		csr->fw_path = TGL_CSR_PATH;
 		csr->required_version = TGL_CSR_VERSION_REQUIRED;
 		/* Allow to load fw via parameter using the last known size */
-- 
2.24.1

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 05/22] drm/i915/rkl: Add PCH support
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (3 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 04/22] drm/i915/rkl: Load DMC firmware for Rocket Lake Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 06/22] drm/i915/rkl: Update memory bandwidth parameters Matt Roper
                   ` (22 subsequent siblings)
  27 siblings, 0 replies; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

Rocket Lake can pair with either TGP or CMP.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_pch.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index 20ab9a5023b5..102b03d24f90 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -88,7 +88,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 	case INTEL_PCH_CMP_DEVICE_ID_TYPE:
 	case INTEL_PCH_CMP2_DEVICE_ID_TYPE:
 		drm_dbg_kms(&dev_priv->drm, "Found Comet Lake PCH (CMP)\n");
-		drm_WARN_ON(&dev_priv->drm, !IS_COFFEELAKE(dev_priv));
+		drm_WARN_ON(&dev_priv->drm, !IS_COFFEELAKE(dev_priv) &&
+			    !IS_ROCKETLAKE(dev_priv));
 		/* CometPoint is CNP Compatible */
 		return PCH_CNP;
 	case INTEL_PCH_CMP_V_DEVICE_ID_TYPE:
@@ -107,7 +108,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 	case INTEL_PCH_TGP_DEVICE_ID_TYPE:
 	case INTEL_PCH_TGP2_DEVICE_ID_TYPE:
 		drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n");
-		drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv));
+		drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) &&
+			    !IS_ROCKETLAKE(dev_priv));
 		return PCH_TGP;
 	case INTEL_PCH_JSP_DEVICE_ID_TYPE:
 	case INTEL_PCH_JSP2_DEVICE_ID_TYPE:
@@ -141,7 +143,7 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
 	 * make an educated guess as to which PCH is really there.
 	 */
 
-	if (IS_TIGERLAKE(dev_priv))
+	if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
 		id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
 	else if (IS_ELKHARTLAKE(dev_priv))
 		id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
-- 
2.24.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 06/22] drm/i915/rkl: Update memory bandwidth parameters
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (4 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 05/22] drm/i915/rkl: Add PCH support Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-07 12:24   ` Ville Syrjälä
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 07/22] drm/i915/rkl: Limit number of universal planes to 5 Matt Roper
                   ` (21 subsequent siblings)
  27 siblings, 1 reply; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx

The RKL platform has different memory characteristics from past
platforms.  Update the values used by our memory bandwidth calculations
accordingly.

Bspec: 53998
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 6e7cc3a4f1aa..d435cc6019e4 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -176,6 +176,12 @@ static const struct intel_sa_info tgl_sa_info = {
 	.displayrtids = 256,
 };
 
+static const struct intel_sa_info rkl_sa_info = {
+	.deburst = 16,
+	.deprogbwlimit = 20, /* GB/s */
+	.displayrtids = 128,
+};
+
 static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
 {
 	struct intel_qgv_info qi = {};
@@ -271,7 +277,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
 	if (!HAS_DISPLAY(dev_priv))
 		return;
 
-	if (IS_GEN(dev_priv, 12))
+	if (IS_ROCKETLAKE(dev_priv))
+		icl_get_bw_info(dev_priv, &rkl_sa_info);
+	else if (IS_GEN(dev_priv, 12))
 		icl_get_bw_info(dev_priv, &tgl_sa_info);
 	else if (IS_GEN(dev_priv, 11))
 		icl_get_bw_info(dev_priv, &icl_sa_info);
-- 
2.24.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 07/22] drm/i915/rkl: Limit number of universal planes to 5
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (5 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 06/22] drm/i915/rkl: Update memory bandwidth parameters Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-07 12:10   ` Ville Syrjälä
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 08/22] drm/i915/rkl: Add power well support Matt Roper
                   ` (20 subsequent siblings)
  27 siblings, 1 reply; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx

RKL only has five universal planes, plus a cursor.  Since the
bottom-most universal plane is considered the primary plane, set the
number of sprites available on this platform to 4.

In general, the plane capabilities of the remaining planes stay the same
as TGL.  However the NV12 Y-plane support moves down to the new top two
planes and now only the bottom three planes can be used for NV12 UV.

Bspec: 49181
Bspec: 49251
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  6 +++++-
 drivers/gpu/drm/i915/display/intel_sprite.c  | 17 ++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_sprite.h  | 11 ++---------
 drivers/gpu/drm/i915/i915_irq.c              |  4 +++-
 drivers/gpu/drm/i915/i915_reg.h              |  5 +++++
 drivers/gpu/drm/i915/intel_device_info.c     |  5 ++++-
 6 files changed, 35 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index fd6d63b03489..7d7a5b66f2cb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12500,7 +12500,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
 			continue;
 
 		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
-			if (!icl_is_nv12_y_plane(linked->id))
+			if (!icl_is_nv12_y_plane(dev_priv, linked->id))
 				continue;
 
 			if (crtc_state->active_planes & BIT(linked->id))
@@ -12546,6 +12546,10 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
 				plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
 			else if (linked->id == PLANE_SPRITE4)
 				plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
+			else if (linked->id == PLANE_SPRITE3)
+				plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
+			else if (linked->id == PLANE_SPRITE2)
+				plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
 			else
 				MISSING_CASE(linked->id);
 		}
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 0000ec7055f7..571c36f929bd 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -333,6 +333,21 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 	return 0;
 }
 
+static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
+{
+	if (IS_ROCKETLAKE(i915))
+		return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
+	else
+		return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
+}
+
+bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
+			 enum plane_id plane_id)
+{
+	return INTEL_GEN(dev_priv) >= 11 &&
+		icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id);
+}
+
 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id)
 {
 	return INTEL_GEN(dev_priv) >= 11 &&
@@ -3003,7 +3018,7 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
 	if (icl_is_hdr_plane(dev_priv, plane_id)) {
 		*num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
 		return icl_hdr_plane_formats;
-	} else if (icl_is_nv12_y_plane(plane_id)) {
+	} else if (icl_is_nv12_y_plane(dev_priv, plane_id)) {
 		*num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats);
 		return icl_sdr_y_plane_formats;
 	} else {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.h b/drivers/gpu/drm/i915/display/intel_sprite.h
index 5eeaa92420d1..cd2104ba1ca1 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.h
+++ b/drivers/gpu/drm/i915/display/intel_sprite.h
@@ -32,21 +32,14 @@ struct intel_plane *
 skl_universal_plane_create(struct drm_i915_private *dev_priv,
 			   enum pipe pipe, enum plane_id plane_id);
 
-static inline bool icl_is_nv12_y_plane(enum plane_id id)
-{
-	/* Don't need to do a gen check, these planes are only available on gen11 */
-	if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
-		return true;
-
-	return false;
-}
-
 static inline u8 icl_hdr_plane_mask(void)
 {
 	return BIT(PLANE_PRIMARY) |
 		BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
 }
 
+bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
+			 enum plane_id plane_id);
 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
 
 int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index bd722d0650c8..622986759ec6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2221,7 +2221,9 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
 
 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) >= 11)
+	if (IS_ROCKETLAKE(dev_priv))
+		return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
+	else if (INTEL_GEN(dev_priv) >= 11)
 		return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
 	else if (INTEL_GEN(dev_priv) >= 9)
 		return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fd9f2904d93c..59c1d527cf13 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6907,6 +6907,8 @@ enum {
 #define _PLANE_CUS_CTL_1_A			0x701c8
 #define _PLANE_CUS_CTL_2_A			0x702c8
 #define  PLANE_CUS_ENABLE			(1 << 31)
+#define  PLANE_CUS_PLANE_4_RKL			(0 << 30)
+#define  PLANE_CUS_PLANE_5_RKL			(1 << 30)
 #define  PLANE_CUS_PLANE_6			(0 << 30)
 #define  PLANE_CUS_PLANE_7			(1 << 30)
 #define  PLANE_CUS_HPHASE_SIGN_NEGATIVE		(1 << 19)
@@ -7573,6 +7575,9 @@ enum {
 	 GEN11_PIPE_PLANE7_FAULT | \
 	 GEN11_PIPE_PLANE6_FAULT | \
 	 GEN11_PIPE_PLANE5_FAULT)
+#define RKL_DE_PIPE_IRQ_FAULT_ERRORS \
+	(GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
+	 GEN11_PIPE_PLANE5_FAULT)
 
 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 9862c1185059..a5a92c2728db 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -934,7 +934,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 
 	BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
 
-	if (INTEL_GEN(dev_priv) >= 11)
+	if (IS_ROCKETLAKE(dev_priv))
+		for_each_pipe(dev_priv, pipe)
+			runtime->num_sprites[pipe] = 4;
+	else if (INTEL_GEN(dev_priv) >= 11)
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_sprites[pipe] = 6;
 	else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
-- 
2.24.1

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 08/22] drm/i915/rkl: Add power well support
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (6 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 07/22] drm/i915/rkl: Limit number of universal planes to 5 Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-05  4:50   ` Anshuman Gupta
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 09/22] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 Matt Roper
                   ` (19 subsequent siblings)
  27 siblings, 1 reply; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

RKL power wells are similar to TGL power wells, but have some important
differences:

 * PG1 now has pipe A's VDSC (rather than sticking it in PG2)
 * PG2 no longer exists
 * DDI-C (aka TC-1) moves from PG1 -> PG3
 * PG5 no longer exists due to the lack of a fourth pipe

Also note that what we refer to as 'DDI-C' and 'DDI-D' need to actually
be programmed as TC-1 and TC-2 even though this platform doesn't have TC
outputs.

Bspec: 49234
Cc: Imre Deak <imre.deak@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 185 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vdsc.c     |   4 +-
 2 files changed, 186 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 49998906cc61..71691919d101 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -2913,6 +2913,53 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	BIT_ULL(POWER_DOMAIN_AUX_I_TBT)	|	\
 	BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
 
+#define RKL_PW_4_POWER_DOMAINS (			\
+	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
+	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
+	BIT_ULL(POWER_DOMAIN_INIT))
+
+#define RKL_PW_3_POWER_DOMAINS (			\
+	RKL_PW_4_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
+	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
+	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
+	BIT_ULL(POWER_DOMAIN_VGA) |			\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |	\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |	\
+	BIT_ULL(POWER_DOMAIN_AUX_D) |			\
+	BIT_ULL(POWER_DOMAIN_AUX_E) |			\
+	BIT_ULL(POWER_DOMAIN_INIT))
+
+/*
+ * There is no PW_2/PG_2 on RKL.
+ *
+ * RKL PW_1/PG_1 domains (under HW/DMC control):
+ * - DBUF function (note: registers are in PW0)
+ * - PIPE_A and its planes and VDSC/joining, except VGA
+ * - transcoder A
+ * - DDI_A and DDI_B
+ * - FBC
+ *
+ * RKL PW_0/PG_0 domains (under HW/DMC control):
+ * - PCI
+ * - clocks except port PLL
+ * - shared functions:
+ *     * interrupts except pipe interrupts
+ *     * MBus except PIPE_MBUS_DBOX_CTL
+ *     * DBUF registers
+ * - central power except FBC
+ * - top-level GTC (DDI-level GTC is in the well associated with the DDI)
+ */
+
+#define RKL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
+	RKL_PW_3_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_MODESET) |			\
+	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
+	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
+	BIT_ULL(POWER_DOMAIN_INIT))
+
 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
 	.sync_hw = i9xx_power_well_sync_hw_noop,
 	.enable = i9xx_always_on_power_well_noop,
@@ -4283,6 +4330,140 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 	},
 };
 
+static const struct i915_power_well_desc rkl_power_wells[] = {
+	{
+		.name = "always-on",
+		.always_on = true,
+		.domains = POWER_DOMAIN_MASK,
+		.ops = &i9xx_always_on_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+	},
+	{
+		.name = "power well 1",
+		/* Handled by the DMC firmware */
+		.always_on = true,
+		.domains = 0,
+		.ops = &hsw_power_well_ops,
+		.id = SKL_DISP_PW_1,
+		{
+			.hsw.regs = &hsw_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_PW_1,
+			.hsw.has_fuses = true,
+		},
+	},
+	{
+		.name = "DC off",
+		.domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
+		.ops = &gen9_dc_off_power_well_ops,
+		.id = SKL_DISP_DC_OFF,
+	},
+	{
+		.name = "power well 3",
+		.domains = RKL_PW_3_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = ICL_DISP_PW_3,
+		{
+			.hsw.regs = &hsw_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
+			.hsw.irq_pipe_mask = BIT(PIPE_B),
+			.hsw.has_vga = true,
+			.hsw.has_fuses = true,
+		},
+	},
+	{
+		.name = "power well 4",
+		.domains = RKL_PW_4_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &hsw_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_PW_4,
+			.hsw.has_fuses = true,
+			.hsw.irq_pipe_mask = BIT(PIPE_C),
+		}
+	},
+	{
+		.name = "DDI A IO",
+		.domains = ICL_DDI_IO_A_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+		}
+	},
+	{
+		.name = "DDI B IO",
+		.domains = ICL_DDI_IO_B_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+		}
+	},
+	{
+		.name = "DDI D TC1 IO",
+		.domains = TGL_DDI_IO_D_TC1_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
+		},
+	},
+	{
+		.name = "DDI E TC2 IO",
+		.domains = TGL_DDI_IO_E_TC2_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
+		},
+	},
+	{
+		.name = "AUX A",
+		.domains = ICL_AUX_A_IO_POWER_DOMAINS,
+		.ops = &icl_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+		},
+	},
+	{
+		.name = "AUX B",
+		.domains = ICL_AUX_B_IO_POWER_DOMAINS,
+		.ops = &icl_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+		},
+	},
+	{
+		.name = "AUX D TC1",
+		.domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
+		.ops = &icl_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+		},
+	},
+	{
+		.name = "AUX E TC2",
+		.domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
+		.ops = &icl_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
+		},
+	},
+};
+
 static int
 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
 				   int disable_power_well)
@@ -4428,7 +4609,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 	 * The enabling order will be from lower to higher indexed wells,
 	 * the disabling order is reversed.
 	 */
-	if (IS_GEN(dev_priv, 12)) {
+	if (IS_ROCKETLAKE(dev_priv)) {
+		err = set_power_wells(power_domains, rkl_power_wells);
+	} else if (IS_GEN(dev_priv, 12)) {
 		err = set_power_wells(power_domains, tgl_power_wells);
 	} else if (IS_GEN(dev_priv, 11)) {
 		err = set_power_wells(power_domains, icl_power_wells);
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 95ad87d4ccb3..d145fe2bed81 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -476,13 +476,13 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
 	 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:
 	 *
 	 *  - ICL eDP/DSI transcoder
-	 *  - TGL pipe A
+	 *  - Gen12+ (except RKL) pipe A
 	 *
 	 * For any other pipe, VDSC/joining uses the power well associated with
 	 * the pipe in use. Hence another reference on the pipe power domain
 	 * will suffice. (Except no VDSC/joining on ICL pipe A.)
 	 */
-	if (INTEL_GEN(i915) >= 12 && pipe == PIPE_A)
+	if (INTEL_GEN(i915) >= 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
 		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
 	else if (is_pipe_dsc(crtc_state))
 		return POWER_DOMAIN_PIPE(pipe);
-- 
2.24.1

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^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 09/22] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (7 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 08/22] drm/i915/rkl: Add power well support Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B Matt Roper
                   ` (18 subsequent siblings)
  27 siblings, 0 replies; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx

RKL uses the same BW_BUDDY programming table as TGL, but programs the
values into a single set BUDDY0 set of registers rather than the
BUDDY1/BUDDY2 sets used by TGL.

Bspec: 49218
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 44 +++++++++++--------
 drivers/gpu/drm/i915/i915_reg.h               | 14 ++++--
 2 files changed, 35 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 71691919d101..a83e1bc0e3a7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5249,7 +5249,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 	enum intel_dram_type type = dev_priv->dram_info.type;
 	u8 num_channels = dev_priv->dram_info.num_channels;
 	const struct buddy_page_mask *table;
-	int i;
+	int config, min_buddy, max_buddy, i;
 
 	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
 		/* Wa_1409767108: tgl */
@@ -5257,29 +5257,35 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 	else
 		table = tgl_buddy_page_masks;
 
-	for (i = 0; table[i].page_mask != 0; i++)
-		if (table[i].num_channels == num_channels &&
-		    table[i].type == type)
+	if (IS_ROCKETLAKE(dev_priv)) {
+		min_buddy = max_buddy = 0;
+	} else {
+		min_buddy = 1;
+		max_buddy = 2;
+	}
+
+	for (config = 0; table[config].page_mask != 0; config++)
+		if (table[config].num_channels == num_channels &&
+		    table[config].type == type)
 			break;
 
-	if (table[i].page_mask == 0) {
+	if (table[config].page_mask == 0) {
 		drm_dbg(&dev_priv->drm,
 			"Unknown memory configuration; disabling address buddy logic.\n");
-		intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE);
-		intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE);
+		for (i = min_buddy; i <= max_buddy; i++)
+			intel_de_write(dev_priv, BW_BUDDY_CTL(i),
+				       BW_BUDDY_DISABLE);
 	} else {
-		intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK,
-			       table[i].page_mask);
-		intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK,
-			       table[i].page_mask);
-
-		/* Wa_22010178259:tgl */
-		intel_de_rmw(dev_priv, BW_BUDDY1_CTL,
-			     BW_BUDDY_TLB_REQ_TIMER_MASK,
-			     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
-		intel_de_rmw(dev_priv, BW_BUDDY2_CTL,
-			     BW_BUDDY_TLB_REQ_TIMER_MASK,
-			     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
+		for (i = min_buddy; i <= max_buddy; i++) {
+			intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i),
+				       table[config].page_mask);
+
+			/* Wa_22010178259:tgl,rkl */
+			intel_de_rmw(dev_priv, BW_BUDDY_CTL(i),
+				     BW_BUDDY_TLB_REQ_TIMER_MASK,
+				     REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK,
+						    0x8));
+		}
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 59c1d527cf13..2266f9fc2d79 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7832,13 +7832,19 @@ enum {
 #define  WAIT_FOR_PCH_RESET_ACK		(1 << 1)
 #define  WAIT_FOR_PCH_FLR_ACK		(1 << 0)
 
-#define BW_BUDDY1_CTL			_MMIO(0x45140)
-#define BW_BUDDY2_CTL			_MMIO(0x45150)
+#define _BW_BUDDY0_CTL			0x45130
+#define _BW_BUDDY1_CTL			0x45140
+#define BW_BUDDY_CTL(x)			_MMIO(_PICK_EVEN(x, \
+							 _BW_BUDDY0_CTL, \
+							 _BW_BUDDY1_CTL))
 #define   BW_BUDDY_DISABLE		REG_BIT(31)
 #define   BW_BUDDY_TLB_REQ_TIMER_MASK	REG_GENMASK(21, 16)
 
-#define BW_BUDDY1_PAGE_MASK		_MMIO(0x45144)
-#define BW_BUDDY2_PAGE_MASK		_MMIO(0x45154)
+#define _BW_BUDDY0_PAGE_MASK		0x45134
+#define _BW_BUDDY1_PAGE_MASK		0x45144
+#define BW_BUDDY_PAGE_MASK(x)		_MMIO(_PICK_EVEN(x, \
+							 _BW_BUDDY0_PAGE_MASK, \
+							 _BW_BUDDY1_PAGE_MASK))
 
 #define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)
 #define  RESET_PCH_HANDSHAKE_ENABLE	(1 << 4)
-- 
2.24.1

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^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (8 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 09/22] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-06 13:49   ` Srivatsa, Anusha
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 11/22] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout Matt Roper
                   ` (17 subsequent siblings)
  27 siblings, 1 reply; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx

Since the number of platforms with this restriction are growing, let's
separate out the platform logic into a has_phy_misc() function.

Bspec: 50107
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 .../gpu/drm/i915/display/intel_combo_phy.c    | 30 +++++++++++--------
 1 file changed, 17 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 9ff05ec12115..43d8784f6fa0 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -181,11 +181,25 @@ static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)
 	intel_de_write(dev_priv, CHICKEN_MISC_2, val);
 }
 
+static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
+{
+	/*
+	 * Some platforms only expect PHY_MISC to be programmed for PHY-A and
+	 * PHY-B and may not even have instances of the register for the
+	 * other combo PHY's.
+	 */
+	if (IS_ELKHARTLAKE(i915) ||
+	    IS_ROCKETLAKE(i915))
+		return phy < PHY_C;
+
+	return true;
+}
+
 static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
 				  enum phy phy)
 {
 	/* The PHY C added by EHL has no PHY_MISC register */
-	if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
+	if (!has_phy_misc(dev_priv, phy))
 		return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
 	else
 		return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) &
@@ -317,12 +331,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 			continue;
 		}
 
-		/*
-		 * Although EHL adds a combo PHY C, there's no PHY_MISC
-		 * register for it and no need to program the
-		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
-		 */
-		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
+		if (!has_phy_misc(dev_priv, phy))
 			goto skip_phy_misc;
 
 		/*
@@ -376,12 +385,7 @@ static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
 				 "Combo PHY %c HW state changed unexpectedly\n",
 				 phy_name(phy));
 
-		/*
-		 * Although EHL adds a combo PHY C, there's no PHY_MISC
-		 * register for it and no need to program the
-		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
-		 */
-		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
+		if (!has_phy_misc(dev_priv, phy))
 			goto skip_phy_misc;
 
 		val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
-- 
2.24.1

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^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 11/22] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (9 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs Matt Roper
                   ` (16 subsequent siblings)
  27 siblings, 0 replies; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx

RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register.

v2:
 - Fix inverted mask application when updating ICL_DPCLKA_CFGCR0
 - Checkpatch style fixes

Bspec: 50287
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     | 18 +++++++++++++++---
 drivers/gpu/drm/i915/display/intel_display.c | 15 ++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h              |  6 ++++++
 3 files changed, 33 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5601673c3f30..0ab03282c397 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2732,7 +2732,9 @@ hsw_set_signal_levels(struct intel_dp *intel_dp)
 static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
 				     enum phy phy)
 {
-	if (intel_phy_is_combo(dev_priv, phy)) {
+	if (IS_ROCKETLAKE(dev_priv)) {
+		return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+	} else if (intel_phy_is_combo(dev_priv, phy)) {
 		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 	} else if (intel_phy_is_tc(dev_priv, phy)) {
 		enum tc_port tc_port = intel_port_to_tc(dev_priv,
@@ -2759,6 +2761,16 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 		    (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
 
 	if (intel_phy_is_combo(dev_priv, phy)) {
+		u32 mask, sel;
+
+		if (IS_ROCKETLAKE(dev_priv)) {
+			mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+			sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+		} else {
+			mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+			sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+		}
+
 		/*
 		 * Even though this register references DDIs, note that we
 		 * want to pass the PHY rather than the port (DDI).  For
@@ -2769,8 +2781,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 		 *   Clock Select chooses the PLL for both DDIA and DDID and
 		 *   drives port A in all cases."
 		 */
-		val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-		val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+		val &= ~mask;
+		val |= sel;
 		intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
 		intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7d7a5b66f2cb..e30b765d271d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10773,9 +10773,18 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
 	u32 temp;
 
 	if (intel_phy_is_combo(dev_priv, phy)) {
-		temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) &
-			ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-		id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
+		u32 mask, shift;
+
+		if (IS_ROCKETLAKE(dev_priv)) {
+			mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+			shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
+		} else {
+			mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+			shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
+		}
+
+		temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask;
+		id = temp >> shift;
 		port_dpll_id = ICL_PORT_DPLL_DEFAULT;
 	} else if (intel_phy_is_tc(dev_priv, phy)) {
 		u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2266f9fc2d79..516bfbad0eb9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10163,12 +10163,18 @@ enum skl_power_gate {
 
 #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24))
+#define  RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	REG_BIT((phy) + 10)
 #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
 						       (tc_port) + 12 : \
 						       (tc_port) - PORT_TC4 + 21))
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	((phy) * 2)
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+#define  RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	_PICK(phy, 0, 2, 4, 27)
+#define  RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
+	(3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+#define  RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
+	((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
 
 /* CNL PLL */
 #define DPLL0_ENABLE		0x46010
-- 
2.24.1

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^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (10 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 11/22] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-07 11:38   ` Srivatsa, Anusha
  2020-05-07 11:59   ` Ville Syrjälä
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 13/22] drm/i915/rkl: Setup ports/phys Matt Roper
                   ` (15 subsequent siblings)
  27 siblings, 2 replies; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

When Rocket Lake is paired with a TGP PCH, the last two outputs utilize
the TC1 and TC2 hpd pins, even though these are combo outputs.

Bspec: 49181
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6952b0295096..d32bbcd99b8a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6172,8 +6172,12 @@ static bool bxt_digital_port_connected(struct intel_encoder *encoder)
 static bool intel_combo_phy_connected(struct drm_i915_private *dev_priv,
 				      enum phy phy)
 {
-	if (HAS_PCH_MCC(dev_priv) && phy == PHY_C)
-		return intel_de_read(dev_priv, SDEISR) & SDE_TC_HOTPLUG_ICP(PORT_TC1);
+	if (IS_ROCKETLAKE(dev_priv) && phy >= PHY_C)
+		return intel_de_read(dev_priv, SDEISR) &
+			SDE_TC_HOTPLUG_ICP(phy - PHY_C);
+	else if (HAS_PCH_MCC(dev_priv) && phy == PHY_C)
+		return intel_de_read(dev_priv, SDEISR) &
+			SDE_TC_HOTPLUG_ICP(PORT_TC1);
 
 	return intel_de_read(dev_priv, SDEISR) & SDE_DDI_HOTPLUG_ICP(phy);
 }
-- 
2.24.1

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^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 13/22] drm/i915/rkl: Setup ports/phys
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (11 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 14/22] drm/i915/rkl: provide port/phy mapping for vbt Matt Roper
                   ` (14 subsequent siblings)
  27 siblings, 0 replies; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

RKL uses DDI's A, B, TC1, and TC2 which need to map to combo PHY's A-D.

Bspec: 49181
Cc: Imre Deak <imre.deak@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 34 ++++++++++++--------
 drivers/gpu/drm/i915/i915_reg.h              |  4 ++-
 2 files changed, 24 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e30b765d271d..fcfc3812ef28 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7212,30 +7212,33 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 {
 	if (phy == PHY_NONE)
 		return false;
-
-	if (IS_ELKHARTLAKE(dev_priv))
+	else if (IS_ROCKETLAKE(dev_priv))
+		return phy <= PHY_D;
+	else if (IS_ELKHARTLAKE(dev_priv))
 		return phy <= PHY_C;
-
-	if (INTEL_GEN(dev_priv) >= 11)
+	else if (INTEL_GEN(dev_priv) >= 11)
 		return phy <= PHY_B;
-
-	return false;
+	else
+		return false;
 }
 
 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 {
-	if (INTEL_GEN(dev_priv) >= 12)
+	if (IS_ROCKETLAKE(dev_priv))
+		return false;
+	else if (INTEL_GEN(dev_priv) >= 12)
 		return phy >= PHY_D && phy <= PHY_I;
-
-	if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
+	else if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
 		return phy >= PHY_C && phy <= PHY_F;
-
-	return false;
+	else
+		return false;
 }
 
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 {
-	if (IS_ELKHARTLAKE(i915) && port == PORT_D)
+	if (IS_ROCKETLAKE(i915) && port >= PORT_D)
+		return (enum phy)port - 1;
+	else if (IS_ELKHARTLAKE(i915) && port == PORT_D)
 		return PHY_A;
 
 	return (enum phy)port;
@@ -16691,7 +16694,12 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 	if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
 		return;
 
-	if (INTEL_GEN(dev_priv) >= 12) {
+	if (IS_ROCKETLAKE(dev_priv)) {
+		intel_ddi_init(dev_priv, PORT_A);
+		intel_ddi_init(dev_priv, PORT_B);
+		intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
+		intel_ddi_init(dev_priv, PORT_E);	/* DDI TC2 */
+	} else if (INTEL_GEN(dev_priv) >= 12) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_D);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 516bfbad0eb9..e1db65dc5a87 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1869,9 +1869,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _ICL_COMBOPHY_A			0x162000
 #define _ICL_COMBOPHY_B			0x6C000
 #define _EHL_COMBOPHY_C			0x160000
+#define _RKL_COMBOPHY_D			0x161000
 #define _ICL_COMBOPHY(phy)		_PICK(phy, _ICL_COMBOPHY_A, \
 					      _ICL_COMBOPHY_B, \
-					      _EHL_COMBOPHY_C)
+					      _EHL_COMBOPHY_C, \
+					      _RKL_COMBOPHY_D)
 
 /* CNL/ICL Port CL_DW registers */
 #define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
-- 
2.24.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 14/22] drm/i915/rkl: provide port/phy mapping for vbt
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (12 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 13/22] drm/i915/rkl: Setup ports/phys Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-07 12:04   ` Ville Syrjälä
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 15/22] drm/i915/rkl: Add DDC pin mapping Matt Roper
                   ` (13 subsequent siblings)
  27 siblings, 1 reply; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

From: Lucas De Marchi <lucas.demarchi@intel.com>

RKL uses the DDI A, DDI B, DDI USBC1, DDI USBC2 from the DE point of
view, so all DDI/pipe/transcoder register use these indexes to refer to
them. Combo phy and IO functions follow another namespace that we keep
as "enum phy". The VBT in theory would use the DE point of view, but
that does not happen in practice.

Provide a table to convert the child devices to the "correct" port
numbering we use. Now this is the output we get while reading the VBT:

DDIA:
[drm:intel_bios_port_aux_ch [i915]] using AUX A for port A (VBT)
[drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:275:DDI A]
[drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:275:DDI A]
[drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x1 for port A (VBT)

DDIB:
[drm:intel_bios_port_aux_ch [i915]] using AUX B for port B (platform default)
[drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:291:DDI B]
[drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x2 for port B (VBT)

DDI USBC1:
[drm:intel_bios_port_aux_ch [i915]] using AUX D for port D (VBT)
[drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:295:DDI D]
[drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:295:DDI D]
[drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x3 for port D (VBT)

DDI USBC2:
[drm:intel_bios_port_aux_ch [i915]] using AUX E for port E (VBT)
[drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:306:DDI E]
[drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:306:DDI E]
[drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x9 for port E (VBT)

Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c | 72 ++++++++++++++++-------
 1 file changed, 51 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 839124647202..4f1a72a90b8f 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1619,30 +1619,18 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
 	return 0;
 }
 
-static enum port dvo_port_to_port(u8 dvo_port)
+static enum port __dvo_port_to_port(int n_ports, int n_dvo,
+				    const int port_mapping[][3], u8 dvo_port)
 {
-	/*
-	 * Each DDI port can have more than one value on the "DVO Port" field,
-	 * so look for all the possible values for each port.
-	 */
-	static const int dvo_ports[][3] = {
-		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1},
-		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1},
-		[PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1},
-		[PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1},
-		[PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
-		[PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1},
-		[PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1},
-	};
 	enum port port;
 	int i;
 
-	for (port = PORT_A; port < ARRAY_SIZE(dvo_ports); port++) {
-		for (i = 0; i < ARRAY_SIZE(dvo_ports[port]); i++) {
-			if (dvo_ports[port][i] == -1)
+	for (port = PORT_A; port < n_ports; port++) {
+		for (i = 0; i < n_dvo; i++) {
+			if (port_mapping[port][i] == -1)
 				break;
 
-			if (dvo_port == dvo_ports[port][i])
+			if (dvo_port == port_mapping[port][i])
 				return port;
 		}
 	}
@@ -1650,6 +1638,48 @@ static enum port dvo_port_to_port(u8 dvo_port)
 	return PORT_NONE;
 }
 
+static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
+				  u8 dvo_port)
+{
+	/*
+	 * Each DDI port can have more than one value on the "DVO Port" field,
+	 * so look for all the possible values for each port.
+	 */
+	static const int port_mapping[][3] = {
+		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
+		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
+		[PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+		[PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+		[PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, -1 },
+		[PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },
+		[PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },
+	};
+	/*
+	 * Bspec lists the ports as A, B, C, D - however internally in our
+	 * driver we keep them as PORT_A, PORT_B, PORT_D and PORT_E so the
+	 * registers in Display Engine match the right offsets. Apply the
+	 * mapping here to translate from VBT to internal convention.
+	 */
+	static const int rkl_port_mapping[][3] = {
+		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
+		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
+		[PORT_C] = { -1 },
+		[PORT_D] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+		[PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+	};
+
+	if (IS_ROCKETLAKE(dev_priv))
+		return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
+					  ARRAY_SIZE(rkl_port_mapping[0]),
+					  rkl_port_mapping,
+					  dvo_port);
+	else
+		return __dvo_port_to_port(ARRAY_SIZE(port_mapping),
+					  ARRAY_SIZE(port_mapping[0]),
+					  port_mapping,
+					  dvo_port);
+}
+
 static void parse_ddi_port(struct drm_i915_private *dev_priv,
 			   struct display_device_data *devdata,
 			   u8 bdb_version)
@@ -1659,7 +1689,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv,
 	bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
 	enum port port;
 
-	port = dvo_port_to_port(child->dvo_port);
+	port = dvo_port_to_port(dev_priv, child->dvo_port);
 	if (port == PORT_NONE)
 		return;
 
@@ -2603,10 +2633,10 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
 		aux_ch = AUX_CH_B;
 		break;
 	case DP_AUX_C:
-		aux_ch = AUX_CH_C;
+		aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C;
 		break;
 	case DP_AUX_D:
-		aux_ch = AUX_CH_D;
+		aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D;
 		break;
 	case DP_AUX_E:
 		aux_ch = AUX_CH_E;
-- 
2.24.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 15/22] drm/i915/rkl: Add DDC pin mapping
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (13 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 14/22] drm/i915/rkl: provide port/phy mapping for vbt Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-06  9:19   ` Srivatsa, Anusha
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 16/22] drm/i915/rkl: Don't try to access transcoder D Matt Roper
                   ` (12 subsequent siblings)
  27 siblings, 1 reply; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx

The pin mapping for the final two outputs varies according to which PCH
is present on the platform:  with TGP the pins are remapped into the TC
range, whereas with CMP they stay in the traditional combo output range.

Bspec: 49181
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 010f37240710..a31a98d26882 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3082,6 +3082,24 @@ static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
 	return ddc_pin;
 }
 
+static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
+{
+	enum phy phy = intel_port_to_phy(dev_priv, port);
+
+	WARN_ON(port == PORT_C);
+
+	/*
+	 * Pin mapping for RKL depends on which PCH is present.  With TGP, the
+	 * final two outputs use type-c pins, even though they're actually
+	 * combo outputs.  With CMP, the traditional DDI A-D pins are used for
+	 * all outputs.
+	 */
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
+		return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
+
+	return GMBUS_PIN_1_BXT + phy;
+}
+
 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
 			      enum port port)
 {
@@ -3119,7 +3137,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
 		return ddc_pin;
 	}
 
-	if (HAS_PCH_MCC(dev_priv))
+	if (IS_ROCKETLAKE(dev_priv))
+		ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
+	else if (HAS_PCH_MCC(dev_priv))
 		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
-- 
2.24.1

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 16/22] drm/i915/rkl: Don't try to access transcoder D
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (14 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 15/22] drm/i915/rkl: Add DDC pin mapping Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-06 20:34   ` Matt Roper
  2020-05-06 21:21   ` [Intel-gfx] [PATCH v3 " Matt Roper
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 17/22] drm/i915/rkl: Don't try to read out DSI transcoders Matt Roper
                   ` (11 subsequent siblings)
  27 siblings, 2 replies; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx

There are a couple places in our driver that loop over transcoders A..D
for gen11+; since RKL only has three pipes/transcoders, this can lead to
unclaimed register reads/writes.  We should add checks for transcoder
existence where appropriate.

Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 +++
 drivers/gpu/drm/i915/i915_irq.c              | 6 ++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index fcfc3812ef28..2eeafda82188 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11007,6 +11007,9 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
 		else
 			cpu_transcoder = TRANSCODER_DSI_C;
 
+		if (!HAS_TRANSCODER(dev_priv, cpu_transcoder))
+			continue;
+
 		power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 		drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 622986759ec6..1381cb530c2f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2849,6 +2849,9 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
 		for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
 			enum intel_display_power_domain domain;
 
+			if (!HAS_TRANSCODER(dev_priv, trans))
+				continue;
+
 			domain = POWER_DOMAIN_TRANSCODER(trans);
 			if (!intel_display_power_is_enabled(dev_priv, domain))
 				continue;
@@ -3399,6 +3402,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 		for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
 			enum intel_display_power_domain domain;
 
+			if (!HAS_TRANSCODER(dev_priv, trans))
+				continue;
+
 			domain = POWER_DOMAIN_TRANSCODER(trans);
 			if (!intel_display_power_is_enabled(dev_priv, domain))
 				continue;
-- 
2.24.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 17/22] drm/i915/rkl: Don't try to read out DSI transcoders
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (15 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 16/22] drm/i915/rkl: Don't try to access transcoder D Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-07 11:58   ` Ville Syrjälä
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 18/22] drm/i915/rkl: Handle comp master/slave relationships for PHYs Matt Roper
                   ` (10 subsequent siblings)
  27 siblings, 1 reply; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx

From: Aditya Swarup <aditya.swarup@intel.com>

RKL doesn't have DSI outputs, so we shouldn't try to read out the DSI
transcoder registers.

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2eeafda82188..e63221b8a9a6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10901,7 +10901,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
 	intel_wakeref_t wf;
 	u32 tmp;
 
-	if (INTEL_GEN(dev_priv) >= 11)
+	if (!IS_ROCKETLAKE(dev_priv) && INTEL_GEN(dev_priv) >= 11)
 		panel_transcoder_mask |=
 			BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
 
-- 
2.24.1

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 18/22] drm/i915/rkl: Handle comp master/slave relationships for PHYs
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (16 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 17/22] drm/i915/rkl: Don't try to read out DSI transcoders Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-06  9:20   ` Srivatsa, Anusha
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 19/22] drm/i915/rkl: Add DPLL4 support Matt Roper
                   ` (9 subsequent siblings)
  27 siblings, 1 reply; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

Certain combo PHYs act as a compensation master to other PHYs and need
to be initialized with a special irefgen bit in the PORT_COMP_DW8
register.  Previously PHY A was the only compensation master (for PHYs
B & C), but RKL adds a fourth PHY which is slaved to PHY C instead.

Bspec: 49291
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 .../gpu/drm/i915/display/intel_combo_phy.c    | 25 +++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 43d8784f6fa0..77b04bb3ec62 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -234,6 +234,27 @@ static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915)
 	return false;
 }
 
+static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
+{
+	/*
+	 * Certain PHYs are connected to compensation resistors and act
+	 * as masters to other PHYs.
+	 *
+	 * ICL,TGL:
+	 *   A(master) -> B(slave), C(slave)
+	 * RKL:
+	 *   A(master) -> B(slave)
+	 *   C(master) -> D(slave)
+	 *
+	 * We must set the IREFGEN bit for any PHY acting as a master
+	 * to another PHY.
+	 */
+	if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C)
+		return true;
+
+	return phy == PHY_A;
+}
+
 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
 				       enum phy phy)
 {
@@ -245,7 +266,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
 
 	ret = cnl_verify_procmon_ref_values(dev_priv, phy);
 
-	if (phy == PHY_A) {
+	if (phy_is_master(dev_priv, phy)) {
 		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
 				     IREFGEN, IREFGEN);
 
@@ -356,7 +377,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 skip_phy_misc:
 		cnl_set_procmon_ref_values(dev_priv, phy);
 
-		if (phy == PHY_A) {
+		if (phy_is_master(dev_priv, phy)) {
 			val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy));
 			val |= IREFGEN;
 			intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val);
-- 
2.24.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 19/22] drm/i915/rkl: Add DPLL4 support
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (17 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 18/22] drm/i915/rkl: Handle comp master/slave relationships for PHYs Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 20/22] drm/i915/rkl: Handle HTI Matt Roper
                   ` (8 subsequent siblings)
  27 siblings, 0 replies; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

Rocket Lake has a third DPLL (called 'DPLL4') that must be used to
enable a third display.  Unlike EHL's variant of DPLL4, the RKL variant
behaves the same as DPLL0/1.  And despite its name, the DPLL4 registers
are offset as if it were DPLL2, so no extra offset handling is needed
either.

Bspec: 49202
Bspec: 49443
Bspec: 50288
Bspec: 50289
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 28 +++++++++++++++++--
 1 file changed, 25 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index b45185b80bec..196d9eb3a77b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3506,13 +3506,19 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 		return false;
 	}
 
-	if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
+	if (IS_ROCKETLAKE(dev_priv)) {
 		dpll_mask =
 			BIT(DPLL_ID_EHL_DPLL4) |
 			BIT(DPLL_ID_ICL_DPLL1) |
 			BIT(DPLL_ID_ICL_DPLL0);
-	else
+	} else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) {
+		dpll_mask =
+			BIT(DPLL_ID_EHL_DPLL4) |
+			BIT(DPLL_ID_ICL_DPLL1) |
+			BIT(DPLL_ID_ICL_DPLL0);
+	} else {
 		dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0);
+	}
 
 	port_dpll->pll = intel_find_shared_dpll(state, crtc,
 						&port_dpll->hw_state,
@@ -4275,6 +4281,20 @@ static const struct intel_dpll_mgr tgl_pll_mgr = {
 	.dump_hw_state = icl_dump_hw_state,
 };
 
+static const struct dpll_info rkl_plls[] = {
+	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+	{ "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
+	{ },
+};
+
+static const struct intel_dpll_mgr rkl_pll_mgr = {
+	.dpll_info = rkl_plls,
+	.get_dplls = icl_get_dplls,
+	.put_dplls = icl_put_dplls,
+	.dump_hw_state = icl_dump_hw_state,
+};
+
 /**
  * intel_shared_dpll_init - Initialize shared DPLLs
  * @dev: drm device
@@ -4288,7 +4308,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
 	const struct dpll_info *dpll_info;
 	int i;
 
-	if (INTEL_GEN(dev_priv) >= 12)
+	if (IS_ROCKETLAKE(dev_priv))
+		dpll_mgr = &rkl_pll_mgr;
+	else if (INTEL_GEN(dev_priv) >= 12)
 		dpll_mgr = &tgl_pll_mgr;
 	else if (IS_ELKHARTLAKE(dev_priv))
 		dpll_mgr = &ehl_pll_mgr;
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 20/22] drm/i915/rkl: Handle HTI
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (18 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 19/22] drm/i915/rkl: Add DPLL4 support Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 21/22] drm/i915/rkl: Disable PSR2 Matt Roper
                   ` (7 subsequent siblings)
  27 siblings, 0 replies; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

If HTI (also sometimes called HDPORT) is enabled at startup, it may be
using some of the PHYs and DPLLs making them unavailable for general
usage.  Let's read out the HDPORT_STATE register and avoid making use of
resources that HTI is already using.

Bspec: 49189
Bspec: 53707
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 30 ++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 22 ++++++++++++++
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  1 +
 drivers/gpu/drm/i915/i915_drv.h               |  3 ++
 drivers/gpu/drm/i915/i915_reg.h               |  6 ++++
 5 files changed, 58 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e63221b8a9a6..12cdb1b77f64 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -46,6 +46,7 @@
 #include "display/intel_ddi.h"
 #include "display/intel_dp.h"
 #include "display/intel_dp_mst.h"
+#include "display/intel_dpll_mgr.h"
 #include "display/intel_dsi.h"
 #include "display/intel_dvo.h"
 #include "display/intel_gmbus.h"
@@ -16687,6 +16688,13 @@ static void intel_pps_init(struct drm_i915_private *dev_priv)
 	intel_pps_unlock_regs_wa(dev_priv);
 }
 
+static bool hti_uses_phy(u32 hdport_state, enum phy phy)
+{
+	return hdport_state & HDPORT_ENABLED &&
+		(hdport_state & HDPORT_PHY_USED_DP(phy) ||
+		 hdport_state & HDPORT_PHY_USED_HDMI(phy));
+}
+
 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 {
 	struct intel_encoder *encoder;
@@ -16698,10 +16706,22 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 		return;
 
 	if (IS_ROCKETLAKE(dev_priv)) {
-		intel_ddi_init(dev_priv, PORT_A);
-		intel_ddi_init(dev_priv, PORT_B);
-		intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
-		intel_ddi_init(dev_priv, PORT_E);	/* DDI TC2 */
+		/*
+		 * If HTI (aka HDPORT) is enabled at boot, it may have taken
+		 * over some of the PHYs and made them unavailable to the
+		 * driver.  In that case we should skip initializing the
+		 * corresponding outputs.
+		 */
+		u32 hdport_state = intel_de_read(dev_priv, HDPORT_STATE);
+
+		if (!hti_uses_phy(hdport_state, PHY_A))
+			intel_ddi_init(dev_priv, PORT_A);
+		if (!hti_uses_phy(hdport_state, PHY_B))
+			intel_ddi_init(dev_priv, PORT_B);
+		if (!hti_uses_phy(hdport_state, PHY_C))
+			intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
+		if (!hti_uses_phy(hdport_state, PHY_D))
+			intel_ddi_init(dev_priv, PORT_E);	/* DDI TC2 */
 	} else if (INTEL_GEN(dev_priv) >= 12) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
@@ -18220,6 +18240,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 
 	intel_dpll_readout_hw_state(dev_priv);
 
+	dev_priv->hti_pll_mask = intel_get_hti_plls(dev_priv);
+
 	for_each_intel_encoder(dev, encoder) {
 		pipe = 0;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 196d9eb3a77b..f8078a288379 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -265,6 +265,25 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
 	mutex_unlock(&dev_priv->dpll.lock);
 }
 
+/*
+ * HTI (aka HDPORT) may be using some of the platform's PLL's, making them
+ * unavailable for use.
+ */
+u32 intel_get_hti_plls(struct drm_i915_private *dev_priv)
+{
+
+	u32 hdport_state;
+
+	if (!IS_ROCKETLAKE(dev_priv))
+		return 0;
+
+	hdport_state = intel_de_read(dev_priv, HDPORT_STATE);
+	if (!(hdport_state & HDPORT_ENABLED))
+		return 0;
+
+	return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, hdport_state);
+}
+
 static struct intel_shared_dpll *
 intel_find_shared_dpll(struct intel_atomic_state *state,
 		       const struct intel_crtc *crtc,
@@ -280,6 +299,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
 
 	drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
 
+	/* Eliminate DPLLs from consideration if reserved by HTI */
+	dpll_mask &= ~dev_priv->hti_pll_mask;
+
 	for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) {
 		pll = &dev_priv->dpll.shared_dplls[i];
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 5d9a2bc371e7..ac2238646fe7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -390,6 +390,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
 void intel_shared_dpll_init(struct drm_device *dev);
 void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv);
 void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
+u32 intel_get_hti_plls(struct drm_i915_private *dev_priv);
 
 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
 			      const struct intel_dpll_hw_state *hw_state);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1ba77283123d..06802f2f1cd5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1025,6 +1025,9 @@ struct drm_i915_private {
 
 	struct intel_l3_parity l3_parity;
 
+	/* Mask of PLLs reserved for use by HTI and unavailable to driver. */
+	u32 hti_pll_mask;
+
 	/*
 	 * edram size in MB.
 	 * Cannot be determined by PCIID. You must always read a register.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e1db65dc5a87..1d3b137c77db 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2898,6 +2898,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MBUS_BBOX_CTL_S1		_MMIO(0x45040)
 #define MBUS_BBOX_CTL_S2		_MMIO(0x45044)
 
+#define HDPORT_STATE			_MMIO(0x45050)
+#define   HDPORT_DPLL_USED_MASK		REG_GENMASK(14, 12)
+#define   HDPORT_PHY_USED_DP(phy)	REG_BIT(2*phy + 2)
+#define   HDPORT_PHY_USED_HDMI(phy)	REG_BIT(2*phy + 1)
+#define   HDPORT_ENABLED		REG_BIT(0)
+
 /* Make render/texture TLB fetches lower priorty than associated data
  *   fetches. This is not turned on by default
  */
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 21/22] drm/i915/rkl: Disable PSR2
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (19 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 20/22] drm/i915/rkl: Handle HTI Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 22/22] drm/i915/rkl: Add initial workarounds Matt Roper
                   ` (6 subsequent siblings)
  27 siblings, 0 replies; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx; +Cc: Dhinakaran Pandiyan

From: José Roberto de Souza <jose.souza@intel.com>

RKL doesn't have PSR2 HW tracking, it was replaced by software/manual
tracking.  The driver is required to track the areas that needs update
and program hardware to send selective updates.

So until the software tracking is implemented, PSR2 needs to be disabled
for platforms without PSR2 HW tracking.

BSpec: 50422
BSpec: 50424

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 15 +++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h          |  2 ++
 drivers/gpu/drm/i915/i915_pci.c          |  3 +++
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 4 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index a0569fdfeb16..31a04570d262 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -678,6 +678,21 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
+	/*
+	 * Some platforms lack PSR2 HW tracking and instead require manual
+	 * tracking by software.  In this case, the driver is required to track
+	 * the areas that need updates and program hardware to send selective
+	 * updates.
+	 *
+	 * So until the software tracking is implemented, PSR2 needs to be
+	 * disabled for platforms without PSR2 HW tracking.
+	 */
+	if (!HAS_PSR_HW_TRACKING(dev_priv)) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "No PSR2 HW tracking in the platform\n");
+		return false;
+	}
+
 	/*
 	 * DSC and PSR2 cannot be enabled simultaneously. If a requested
 	 * resolution requires DSC to be enabled, priority is given to DSC
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 06802f2f1cd5..88b524399c8f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1618,6 +1618,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
 #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
+#define HAS_PSR_HW_TRACKING(dev_priv) \
+	(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
 #define HAS_TRANSCODER(dev_priv, trans)	 ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
 
 #define HAS_RC6(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 5a470bab2214..2c3b0a7d577d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -536,6 +536,7 @@ static const struct intel_device_info vlv_info = {
 	.display.has_ddi = 1, \
 	.has_fpga_dbg = 1, \
 	.display.has_psr = 1, \
+	.display.has_psr_hw_tracking = 1, \
 	.display.has_dp_mst = 1, \
 	.has_rc6p = 0 /* RC6p removed-by HSW */, \
 	HSW_PIPE_OFFSETS, \
@@ -690,6 +691,7 @@ static const struct intel_device_info skl_gt4_info = {
 	.display.has_fbc = 1, \
 	.display.has_hdcp = 1, \
 	.display.has_psr = 1, \
+	.display.has_psr_hw_tracking = 1, \
 	.has_runtime_pm = 1, \
 	.display.has_csr = 1, \
 	.has_rc6 = 1, \
@@ -868,6 +870,7 @@ static const struct intel_device_info rkl_info = {
 	PLATFORM(INTEL_ROCKETLAKE),
 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 	.require_force_probe = 1,
+	.display.has_psr_hw_tracking = 0,
 	.engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
 };
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index a126984cef7f..b336b50d3e0b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -147,6 +147,7 @@ enum intel_ppgtt_type {
 	func(has_modular_fia); \
 	func(has_overlay); \
 	func(has_psr); \
+	func(has_psr_hw_tracking); \
 	func(overlay_needs_physical); \
 	func(supports_tv);
 
-- 
2.24.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v2 22/22] drm/i915/rkl: Add initial workarounds
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (20 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 21/22] drm/i915/rkl: Disable PSR2 Matt Roper
@ 2020-05-04 22:52 ` Matt Roper
  2020-05-04 23:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Rocket Lake (rev4) Patchwork
                   ` (5 subsequent siblings)
  27 siblings, 0 replies; 53+ messages in thread
From: Matt Roper @ 2020-05-04 22:52 UTC (permalink / raw)
  To: intel-gfx

RKL and TGL share some general gen12 workarounds, but each platform also
has its own platform-specific workarounds.

Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_sprite.c |  5 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 +++++++++++++--------
 2 files changed, 59 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 571c36f929bd..20eea81118da 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2842,8 +2842,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
 					enum plane_id plane_id)
 {
-	/* Wa_14010477008:tgl[a0..c0] */
-	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
+	/* Wa_14010477008:tgl[a0..c0],rkl[all] */
+	if (IS_ROCKETLAKE(dev_priv) ||
+	    IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
 		return false;
 
 	return plane_id < PLANE_SPRITE4;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index aa90e6b7a118..0132728c4e60 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -575,8 +575,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
 }
 
-static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
-				     struct i915_wa_list *wal)
+static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
+				       struct i915_wa_list *wal)
 {
 	/*
 	 * Wa_1409142259:tgl
@@ -586,12 +586,28 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	 * Wa_1409207793:tgl
 	 * Wa_1409178076:tgl
 	 * Wa_1408979724:tgl
+	 * Wa_14010443199:rkl
+	 * Wa_14010698770:rkl
 	 */
 	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
 
+	/* WaDisableGPGPUMidThreadPreemption:gen12 */
+	WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
+			    GEN9_PREEMPT_GPGPU_LEVEL_MASK,
+			    GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
+}
+
+static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
+				     struct i915_wa_list *wal)
+{
+	gen12_ctx_workarounds_init(engine, wal);
+
 	/*
-	 * Wa_1604555607:gen12 and Wa_1608008084:gen12
+	 * Wa_1604555607:tgl
+	 *
+	 * Note that the implementation of this workaround is further modified
+	 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
 	 * FF_MODE2 register will return the wrong value when read. The default
 	 * value for this register is zero for all fields and there are no bit
 	 * masks. So instead of doing a RMW we should just write the TDS timer
@@ -599,11 +615,6 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	 */
 	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
 	       FF_MODE2_TDS_TIMER_128, 0);
-
-	/* WaDisableGPGPUMidThreadPreemption:tgl */
-	WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
-			    GEN9_PREEMPT_GPGPU_LEVEL_MASK,
-			    GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
 }
 
 static void
@@ -618,8 +629,10 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 
 	wa_init_start(wal, name, engine->name);
 
-	if (IS_GEN(i915, 12))
+	if (IS_TIGERLAKE(i915))
 		tgl_ctx_workarounds_init(engine, wal);
+	else if (IS_GEN(i915, 12))
+		gen12_ctx_workarounds_init(engine, wal);
 	else if (IS_GEN(i915, 11))
 		icl_ctx_workarounds_init(engine, wal);
 	else if (IS_CANNONLAKE(i915))
@@ -924,9 +937,16 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 }
 
 static void
-tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+gen12_gt_workarounds_init(struct drm_i915_private *i915,
+			  struct i915_wa_list *wal)
 {
 	wa_init_mcr(i915, wal);
+}
+
+static void
+tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+	gen12_gt_workarounds_init(i915, wal);
 
 	/* Wa_1409420604:tgl */
 	if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
@@ -944,8 +964,10 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 static void
 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
-	if (IS_GEN(i915, 12))
+	if (IS_TIGERLAKE(i915))
 		tgl_gt_workarounds_init(i915, wal);
+	else if (IS_GEN(i915, 12))
+		gen12_gt_workarounds_init(i915, wal);
 	else if (IS_GEN(i915, 11))
 		icl_gt_workarounds_init(i915, wal);
 	else if (IS_CANNONLAKE(i915))
@@ -1340,18 +1362,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    GEN9_CTX_PREEMPT_REG,
 			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
 
-		/*
-		 * Wa_1607030317:tgl
-		 * Wa_1607186500:tgl
-		 * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2
-		 * of then says it is fixed on B0 the other one says it is
-		 * permanent
-		 */
-		wa_masked_en(wal,
-			     GEN6_RC_SLEEP_PSMI_CONTROL,
-			     GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
-			     GEN8_RC_SEMA_IDLE_MSG_DISABLE);
-
 		/*
 		 * Wa_1606679103:tgl
 		 * (see also Wa_1606682166:icl)
@@ -1370,24 +1380,38 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    VSUNIT_CLKGATE_DIS_TGL);
 	}
 
-	if (IS_TIGERLAKE(i915)) {
-		/* Wa_1606931601:tgl */
+	if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+		/* Wa_1606931601:tgl,rkl */
 		wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
 
-		/* Wa_1409804808:tgl */
+		/* Wa_1409804808:tgl,rkl */
 		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
 			     GEN12_PUSH_CONST_DEREF_HOLD_DIS);
 
-		/* Wa_1606700617:tgl */
-		wa_masked_en(wal,
-			     GEN9_CS_DEBUG_MODE1,
-			     FF_DOP_CLOCK_GATE_DISABLE);
-
 		/*
 		 * Wa_1409085225:tgl
-		 * Wa_14010229206:tgl
+		 * Wa_14010229206:tgl,rkl
 		 */
 		wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
+
+		/*
+		 * Wa_1607030317:tgl
+		 * Wa_1607186500:tgl
+		 * Wa_1607297627:tgl,rkl there are multiple entries for this
+		 * WA in the BSpec; some indicate this is an A0-only WA,
+		 * others indicate it applies to all steppings.
+		 */
+		wa_masked_en(wal,
+			     GEN6_RC_SLEEP_PSMI_CONTROL,
+			     GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
+			     GEN8_RC_SEMA_IDLE_MSG_DISABLE);
+	}
+
+	if (IS_TIGERLAKE(i915)) {
+		/* Wa_1606700617:tgl */
+		wa_masked_en(wal,
+			     GEN9_CS_DEBUG_MODE1,
+			     FF_DOP_CLOCK_GATE_DISABLE);
 	}
 
 	if (IS_GEN(i915, 11)) {
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Rocket Lake (rev4)
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (21 preceding siblings ...)
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 22/22] drm/i915/rkl: Add initial workarounds Matt Roper
@ 2020-05-04 23:10 ` Patchwork
  2020-05-04 23:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
                   ` (4 subsequent siblings)
  27 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2020-05-04 23:10 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

== Series Details ==

Series: Introduce Rocket Lake (rev4)
URL   : https://patchwork.freedesktop.org/series/76826/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
e6bef4e2c937 drm/i915/rkl: Add RKL platform info and PCI ids
-:35: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#35: FILE: drivers/gpu/drm/i915/i915_drv.h:1522:
+#define IS_RKL_REVID(p, since, until) \
+	(IS_ROCKETLAKE(p) && IS_REVID(p, since, until))

-:102: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#102: FILE: include/drm/i915_pciids.h:609:
+#define INTEL_RKL_IDS(info) \
+	INTEL_VGA_DEVICE(0x4C80, info), \
+	INTEL_VGA_DEVICE(0x4C8A, info), \
+	INTEL_VGA_DEVICE(0x4C8B, info), \
+	INTEL_VGA_DEVICE(0x4C8C, info), \
+	INTEL_VGA_DEVICE(0x4C90, info), \
+	INTEL_VGA_DEVICE(0x4C9A, info)

-:102: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#102: FILE: include/drm/i915_pciids.h:609:
+#define INTEL_RKL_IDS(info) \
+	INTEL_VGA_DEVICE(0x4C80, info), \
+	INTEL_VGA_DEVICE(0x4C8A, info), \
+	INTEL_VGA_DEVICE(0x4C8B, info), \
+	INTEL_VGA_DEVICE(0x4C8C, info), \
+	INTEL_VGA_DEVICE(0x4C90, info), \
+	INTEL_VGA_DEVICE(0x4C9A, info)

total: 1 errors, 0 warnings, 2 checks, 69 lines checked
803b4f04888a x86/gpu: add RKL stolen memory support
630f1d4d8718 drm/i915/rkl: Re-use TGL GuC/HuC firmware
90f79585717f drm/i915/rkl: Load DMC firmware for Rocket Lake
1c85ab4847be drm/i915/rkl: Add PCH support
dc4048963014 drm/i915/rkl: Update memory bandwidth parameters
a445dde7ad9f drm/i915/rkl: Limit number of universal planes to 5
f02fc9990788 drm/i915/rkl: Add power well support
fda2d4b25173 drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2
-:36: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#36: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:5261:
+		min_buddy = max_buddy = 0;

total: 0 errors, 0 warnings, 1 checks, 84 lines checked
7846d1a805b9 drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B
02aa4c0c4f8f drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
1c3381316fe1 drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs
a8c3d67dc688 drm/i915/rkl: Setup ports/phys
196dbf07dad1 drm/i915/rkl: provide port/phy mapping for vbt
-:17: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#17: 
[drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:275:DDI A]

total: 0 errors, 1 warnings, 0 checks, 104 lines checked
3c2d8a199e89 drm/i915/rkl: Add DDC pin mapping
b8b1dbd88b20 drm/i915/rkl: Don't try to access transcoder D
6906840e8b24 drm/i915/rkl: Don't try to read out DSI transcoders
5018930e1944 drm/i915/rkl: Handle comp master/slave relationships for PHYs
69bfbb9c7a02 drm/i915/rkl: Add DPLL4 support
8b97223a1c60 drm/i915/rkl: Handle HTI
-:92: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#92: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:274:
+{
+

-:154: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#154: FILE: drivers/gpu/drm/i915/i915_reg.h:2903:
+#define   HDPORT_PHY_USED_DP(phy)	REG_BIT(2*phy + 2)
                                  	         ^

-:154: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'phy' may be better as '(phy)' to avoid precedence issues
#154: FILE: drivers/gpu/drm/i915/i915_reg.h:2903:
+#define   HDPORT_PHY_USED_DP(phy)	REG_BIT(2*phy + 2)

-:155: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#155: FILE: drivers/gpu/drm/i915/i915_reg.h:2904:
+#define   HDPORT_PHY_USED_HDMI(phy)	REG_BIT(2*phy + 1)
                                    	         ^

-:155: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'phy' may be better as '(phy)' to avoid precedence issues
#155: FILE: drivers/gpu/drm/i915/i915_reg.h:2904:
+#define   HDPORT_PHY_USED_HDMI(phy)	REG_BIT(2*phy + 1)

total: 0 errors, 0 warnings, 5 checks, 116 lines checked
0126c509f30f drm/i915/rkl: Disable PSR2
9b58f54fa37e drm/i915/rkl: Add initial workarounds

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for Introduce Rocket Lake (rev4)
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (22 preceding siblings ...)
  2020-05-04 23:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Rocket Lake (rev4) Patchwork
@ 2020-05-04 23:33 ` Patchwork
  2020-05-05 13:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
                   ` (3 subsequent siblings)
  27 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2020-05-04 23:33 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

== Series Details ==

Series: Introduce Rocket Lake (rev4)
URL   : https://patchwork.freedesktop.org/series/76826/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8424 -> Patchwork_17577
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/index.html

Known issues
------------

  Here are the changes found in Patchwork_17577 that come from known issues:

### IGT changes ###

#### Warnings ####

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-x1275:       [FAIL][1] ([i915#62]) -> [FAIL][2] ([i915#62] / [i915#95])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html

  
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (51 -> 44)
------------------------------

  Additional (1): fi-kbl-7560u 
  Missing    (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-tgl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8424 -> Patchwork_17577

  CI-20190529: 20190529
  CI_DRM_8424: 69ecf47ef1aabcdc8a4e070584d0a717bbabf4fe @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5628: 652a3fd8966345fa5498904ce80a2027a6782783 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17577: 9b58f54fa37eab9fb17fe54e748b8194eac9f57b @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

9b58f54fa37e drm/i915/rkl: Add initial workarounds
0126c509f30f drm/i915/rkl: Disable PSR2
8b97223a1c60 drm/i915/rkl: Handle HTI
69bfbb9c7a02 drm/i915/rkl: Add DPLL4 support
5018930e1944 drm/i915/rkl: Handle comp master/slave relationships for PHYs
6906840e8b24 drm/i915/rkl: Don't try to read out DSI transcoders
b8b1dbd88b20 drm/i915/rkl: Don't try to access transcoder D
3c2d8a199e89 drm/i915/rkl: Add DDC pin mapping
196dbf07dad1 drm/i915/rkl: provide port/phy mapping for vbt
a8c3d67dc688 drm/i915/rkl: Setup ports/phys
1c3381316fe1 drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs
02aa4c0c4f8f drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
7846d1a805b9 drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B
fda2d4b25173 drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2
f02fc9990788 drm/i915/rkl: Add power well support
a445dde7ad9f drm/i915/rkl: Limit number of universal planes to 5
dc4048963014 drm/i915/rkl: Update memory bandwidth parameters
1c85ab4847be drm/i915/rkl: Add PCH support
90f79585717f drm/i915/rkl: Load DMC firmware for Rocket Lake
630f1d4d8718 drm/i915/rkl: Re-use TGL GuC/HuC firmware
803b4f04888a x86/gpu: add RKL stolen memory support
e6bef4e2c937 drm/i915/rkl: Add RKL platform info and PCI ids

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 08/22] drm/i915/rkl: Add power well support
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 08/22] drm/i915/rkl: Add power well support Matt Roper
@ 2020-05-05  4:50   ` Anshuman Gupta
  2020-05-05 14:39     ` Matt Roper
  0 siblings, 1 reply; 53+ messages in thread
From: Anshuman Gupta @ 2020-05-05  4:50 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx, Lucas De Marchi

On 2020-05-04 at 15:52:13 -0700, Matt Roper wrote:
> RKL power wells are similar to TGL power wells, but have some important
> differences:
> 
>  * PG1 now has pipe A's VDSC (rather than sticking it in PG2)
>  * PG2 no longer exists
>  * DDI-C (aka TC-1) moves from PG1 -> PG3
>  * PG5 no longer exists due to the lack of a fourth pipe
> 
> Also note that what we refer to as 'DDI-C' and 'DDI-D' need to actually
> be programmed as TC-1 and TC-2 even though this platform doesn't have TC
> outputs.
> 
> Bspec: 49234
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  .../drm/i915/display/intel_display_power.c    | 185 +++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_vdsc.c     |   4 +-
>  2 files changed, 186 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 49998906cc61..71691919d101 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -2913,6 +2913,53 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>  	BIT_ULL(POWER_DOMAIN_AUX_I_TBT)	|	\
>  	BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
>  
> +#define RKL_PW_4_POWER_DOMAINS (			\
> +	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
> +	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define RKL_PW_3_POWER_DOMAINS (			\
> +	RKL_PW_4_POWER_DOMAINS |			\
> +	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
> +	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
> +	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
> +	BIT_ULL(POWER_DOMAIN_VGA) |			\
> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |	\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |	\
> +	BIT_ULL(POWER_DOMAIN_AUX_D) |			\
> +	BIT_ULL(POWER_DOMAIN_AUX_E) |			\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +
> +/*
> + * There is no PW_2/PG_2 on RKL.
> + *
> + * RKL PW_1/PG_1 domains (under HW/DMC control):
> + * - DBUF function (note: registers are in PW0)
> + * - PIPE_A and its planes and VDSC/joining, except VGA
> + * - transcoder A
> + * - DDI_A and DDI_B
> + * - FBC
> + *
> + * RKL PW_0/PG_0 domains (under HW/DMC control):
> + * - PCI
> + * - clocks except port PLL
> + * - shared functions:
> + *     * interrupts except pipe interrupts
> + *     * MBus except PIPE_MBUS_DBOX_CTL
> + *     * DBUF registers
> + * - central power except FBC
> + * - top-level GTC (DDI-level GTC is in the well associated with the DDI)
> + */
> +
> +#define RKL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
> +	RKL_PW_3_POWER_DOMAINS |			\
> +	BIT_ULL(POWER_DOMAIN_MODESET) |			\
> +	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> +	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +
>  static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
>  	.sync_hw = i9xx_power_well_sync_hw_noop,
>  	.enable = i9xx_always_on_power_well_noop,
> @@ -4283,6 +4330,140 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
>  	},
>  };
>  
> +static const struct i915_power_well_desc rkl_power_wells[] = {
> +	{
> +		.name = "always-on",
> +		.always_on = true,
> +		.domains = POWER_DOMAIN_MASK,
> +		.ops = &i9xx_always_on_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +	},
> +	{
> +		.name = "power well 1",
> +		/* Handled by the DMC firmware */
> +		.always_on = true,
> +		.domains = 0,
> +		.ops = &hsw_power_well_ops,
> +		.id = SKL_DISP_PW_1,
> +		{
> +			.hsw.regs = &hsw_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_PW_1,
> +			.hsw.has_fuses = true,
> +		},
> +	},
> +	{
> +		.name = "DC off",
> +		.domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> +		.ops = &gen9_dc_off_power_well_ops,
> +		.id = SKL_DISP_DC_OFF,
> +	},
> +	{
> +		.name = "power well 3",
> +		.domains = RKL_PW_3_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = ICL_DISP_PW_3,
> +		{
> +			.hsw.regs = &hsw_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
> +			.hsw.irq_pipe_mask = BIT(PIPE_B),
> +			.hsw.has_vga = true,
> +			.hsw.has_fuses = true,
> +		},
> +	},
> +	{
> +		.name = "power well 4",
> +		.domains = RKL_PW_4_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &hsw_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_PW_4,
> +			.hsw.has_fuses = true,
> +			.hsw.irq_pipe_mask = BIT(PIPE_C),
> +		}
> +	},
IMHO the order of power well is differs from TGL/ICL,
TGL/ICL PW_4 comes after DDI and AUX IO power wells.
Why the order is different on RKL.
Thanks,
Anshuman Gupta.
> +	{
> +		.name = "DDI A IO",
> +		.domains = ICL_DDI_IO_A_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_ddi_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> +		}
> +	},
> +	{
> +		.name = "DDI B IO",
> +		.domains = ICL_DDI_IO_B_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_ddi_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> +		}
> +	},
> +	{
> +		.name = "DDI D TC1 IO",
> +		.domains = TGL_DDI_IO_D_TC1_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_ddi_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
> +		},
> +	},
> +	{
> +		.name = "DDI E TC2 IO",
> +		.domains = TGL_DDI_IO_E_TC2_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_ddi_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
> +		},
> +	},
> +	{
> +		.name = "AUX A",
> +		.domains = ICL_AUX_A_IO_POWER_DOMAINS,
> +		.ops = &icl_aux_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> +		},
> +	},
> +	{
> +		.name = "AUX B",
> +		.domains = ICL_AUX_B_IO_POWER_DOMAINS,
> +		.ops = &icl_aux_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> +		},
> +	},
> +	{
> +		.name = "AUX D TC1",
> +		.domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
> +		.ops = &icl_aux_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
> +		},
> +	},
> +	{
> +		.name = "AUX E TC2",
> +		.domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
> +		.ops = &icl_aux_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
> +		},
> +	},
> +};
> +
>  static int
>  sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
>  				   int disable_power_well)
> @@ -4428,7 +4609,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
>  	 * The enabling order will be from lower to higher indexed wells,
>  	 * the disabling order is reversed.
>  	 */
> -	if (IS_GEN(dev_priv, 12)) {
> +	if (IS_ROCKETLAKE(dev_priv)) {
> +		err = set_power_wells(power_domains, rkl_power_wells);
> +	} else if (IS_GEN(dev_priv, 12)) {
>  		err = set_power_wells(power_domains, tgl_power_wells);
>  	} else if (IS_GEN(dev_priv, 11)) {
>  		err = set_power_wells(power_domains, icl_power_wells);
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 95ad87d4ccb3..d145fe2bed81 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -476,13 +476,13 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
>  	 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:
>  	 *
>  	 *  - ICL eDP/DSI transcoder
> -	 *  - TGL pipe A
> +	 *  - Gen12+ (except RKL) pipe A
>  	 *
>  	 * For any other pipe, VDSC/joining uses the power well associated with
>  	 * the pipe in use. Hence another reference on the pipe power domain
>  	 * will suffice. (Except no VDSC/joining on ICL pipe A.)
>  	 */
> -	if (INTEL_GEN(i915) >= 12 && pipe == PIPE_A)
> +	if (INTEL_GEN(i915) >= 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
>  		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
>  	else if (is_pipe_dsc(crtc_state))
>  		return POWER_DOMAIN_PIPE(pipe);
> -- 
> 2.24.1
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce Rocket Lake (rev4)
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (23 preceding siblings ...)
  2020-05-04 23:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-05-05 13:35 ` Patchwork
  2020-05-06 22:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Rocket Lake (rev5) Patchwork
                   ` (2 subsequent siblings)
  27 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2020-05-05 13:35 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

== Series Details ==

Series: Introduce Rocket Lake (rev4)
URL   : https://patchwork.freedesktop.org/series/76826/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8424_full -> Patchwork_17577_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_17577_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_17577_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_17577_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_mmap_offset@open-flood:
    - shard-kbl:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-kbl2/igt@gem_mmap_offset@open-flood.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-kbl7/igt@gem_mmap_offset@open-flood.html

  
Known issues
------------

  Here are the changes found in Patchwork_17577_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@in-flight-suspend:
    - shard-apl:          [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-apl1/igt@gem_eio@in-flight-suspend.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-apl4/igt@gem_eio@in-flight-suspend.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [PASS][5] -> [DMESG-WARN][6] ([i915#180])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge:
    - shard-apl:          [PASS][7] -> [FAIL][8] ([i915#70] / [i915#95])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-apl4/igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-apl7/igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge.html

  * igt@kms_flip_tiling@flip-changes-tiling-y:
    - shard-apl:          [PASS][9] -> [FAIL][10] ([i915#95])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-apl6/igt@kms_flip_tiling@flip-changes-tiling-y.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-apl6/igt@kms_flip_tiling@flip-changes-tiling-y.html
    - shard-kbl:          [PASS][11] -> [FAIL][12] ([i915#699] / [i915#93] / [i915#95])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-kbl2/igt@kms_flip_tiling@flip-changes-tiling-y.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-kbl4/igt@kms_flip_tiling@flip-changes-tiling-y.html

  * igt@kms_hdr@bpc-switch:
    - shard-skl:          [PASS][13] -> [FAIL][14] ([i915#1188])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-skl1/igt@kms_hdr@bpc-switch.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-skl5/igt@kms_hdr@bpc-switch.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-iclb:         [PASS][15] -> [SKIP][16] ([fdo#109441])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-iclb7/igt@kms_psr@psr2_sprite_blt.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-apl:          [PASS][17] -> [DMESG-WARN][18] ([i915#180] / [i915#95])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@legacy-engines-mixed-process@render:
    - shard-apl:          [FAIL][19] ([i915#1528]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-apl7/igt@gem_ctx_persistence@legacy-engines-mixed-process@render.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-apl1/igt@gem_ctx_persistence@legacy-engines-mixed-process@render.html

  * igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox:
    - shard-skl:          [FAIL][21] ([i915#1528]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-skl10/igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-skl1/igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-apl:          [DMESG-WARN][23] ([i915#716]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-apl6/igt@gen9_exec_parse@allowed-all.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-apl7/igt@gen9_exec_parse@allowed-all.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          [FAIL][25] ([IGT#5]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [SKIP][27] ([fdo#109349]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-iclb6/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  * igt@kms_fence_pin_leak:
    - shard-kbl:          [DMESG-WARN][29] ([i915#165] / [i915#78]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-kbl2/igt@kms_fence_pin_leak.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-kbl4/igt@kms_fence_pin_leak.html

  * {igt@kms_flip@flip-vs-suspend-interruptible@c-dp1}:
    - shard-apl:          [DMESG-WARN][31] ([i915#180]) -> [PASS][32] +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
    - shard-kbl:          [DMESG-WARN][33] ([i915#180]) -> [PASS][34] +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
    - shard-skl:          [FAIL][35] ([i915#49]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [FAIL][37] ([i915#1188]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [FAIL][39] ([fdo#108145] / [i915#265]) -> [PASS][40] +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_plane_lowres@pipe-a-tiling-none:
    - shard-glk:          [FAIL][41] ([i915#899]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-glk8/igt@kms_plane_lowres@pipe-a-tiling-none.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-glk9/igt@kms_plane_lowres@pipe-a-tiling-none.html

  * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
    - shard-skl:          [INCOMPLETE][43] ([i915#69]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-skl8/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-skl3/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-kbl:          [INCOMPLETE][45] ([i915#155] / [i915#794]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-kbl4/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-kbl7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc6-dpms:
    - shard-tglb:         [FAIL][47] ([i915#454]) -> [SKIP][48] ([i915#468])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/shard-tglb3/igt@i915_pm_dc@dc6-dpms.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
  [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
  [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699
  [i915#70]: https://gitlab.freedesktop.org/drm/intel/issues/70
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
  [i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
  [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
  [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (11 -> 10)
------------------------------

  Missing    (1): pig-icl-1065g7 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8424 -> Patchwork_17577

  CI-20190529: 20190529
  CI_DRM_8424: 69ecf47ef1aabcdc8a4e070584d0a717bbabf4fe @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5628: 652a3fd8966345fa5498904ce80a2027a6782783 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17577: 9b58f54fa37eab9fb17fe54e748b8194eac9f57b @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 08/22] drm/i915/rkl: Add power well support
  2020-05-05  4:50   ` Anshuman Gupta
@ 2020-05-05 14:39     ` Matt Roper
  2020-05-05 16:09       ` Imre Deak
  0 siblings, 1 reply; 53+ messages in thread
From: Matt Roper @ 2020-05-05 14:39 UTC (permalink / raw)
  To: Anshuman Gupta; +Cc: intel-gfx, Lucas De Marchi

On Tue, May 05, 2020 at 10:20:58AM +0530, Anshuman Gupta wrote:
> On 2020-05-04 at 15:52:13 -0700, Matt Roper wrote:
> > RKL power wells are similar to TGL power wells, but have some important
> > differences:
> > 
> >  * PG1 now has pipe A's VDSC (rather than sticking it in PG2)
> >  * PG2 no longer exists
> >  * DDI-C (aka TC-1) moves from PG1 -> PG3
> >  * PG5 no longer exists due to the lack of a fourth pipe
> > 
> > Also note that what we refer to as 'DDI-C' and 'DDI-D' need to actually
> > be programmed as TC-1 and TC-2 even though this platform doesn't have TC
> > outputs.
> > 
> > Bspec: 49234
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  .../drm/i915/display/intel_display_power.c    | 185 +++++++++++++++++-
> >  drivers/gpu/drm/i915/display/intel_vdsc.c     |   4 +-
> >  2 files changed, 186 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 49998906cc61..71691919d101 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -2913,6 +2913,53 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> >  	BIT_ULL(POWER_DOMAIN_AUX_I_TBT)	|	\
> >  	BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
> >  
> > +#define RKL_PW_4_POWER_DOMAINS (			\
> > +	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
> > +	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
> > +	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
> > +	BIT_ULL(POWER_DOMAIN_INIT))
> > +
> > +#define RKL_PW_3_POWER_DOMAINS (			\
> > +	RKL_PW_4_POWER_DOMAINS |			\
> > +	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
> > +	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
> > +	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
> > +	BIT_ULL(POWER_DOMAIN_VGA) |			\
> > +	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
> > +	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |	\
> > +	BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |	\
> > +	BIT_ULL(POWER_DOMAIN_AUX_D) |			\
> > +	BIT_ULL(POWER_DOMAIN_AUX_E) |			\
> > +	BIT_ULL(POWER_DOMAIN_INIT))
> > +
> > +/*
> > + * There is no PW_2/PG_2 on RKL.
> > + *
> > + * RKL PW_1/PG_1 domains (under HW/DMC control):
> > + * - DBUF function (note: registers are in PW0)
> > + * - PIPE_A and its planes and VDSC/joining, except VGA
> > + * - transcoder A
> > + * - DDI_A and DDI_B
> > + * - FBC
> > + *
> > + * RKL PW_0/PG_0 domains (under HW/DMC control):
> > + * - PCI
> > + * - clocks except port PLL
> > + * - shared functions:
> > + *     * interrupts except pipe interrupts
> > + *     * MBus except PIPE_MBUS_DBOX_CTL
> > + *     * DBUF registers
> > + * - central power except FBC
> > + * - top-level GTC (DDI-level GTC is in the well associated with the DDI)
> > + */
> > +
> > +#define RKL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
> > +	RKL_PW_3_POWER_DOMAINS |			\
> > +	BIT_ULL(POWER_DOMAIN_MODESET) |			\
> > +	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> > +	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
> > +	BIT_ULL(POWER_DOMAIN_INIT))
> > +
> >  static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> >  	.sync_hw = i9xx_power_well_sync_hw_noop,
> >  	.enable = i9xx_always_on_power_well_noop,
> > @@ -4283,6 +4330,140 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> >  	},
> >  };
> >  
> > +static const struct i915_power_well_desc rkl_power_wells[] = {
> > +	{
> > +		.name = "always-on",
> > +		.always_on = true,
> > +		.domains = POWER_DOMAIN_MASK,
> > +		.ops = &i9xx_always_on_power_well_ops,
> > +		.id = DISP_PW_ID_NONE,
> > +	},
> > +	{
> > +		.name = "power well 1",
> > +		/* Handled by the DMC firmware */
> > +		.always_on = true,
> > +		.domains = 0,
> > +		.ops = &hsw_power_well_ops,
> > +		.id = SKL_DISP_PW_1,
> > +		{
> > +			.hsw.regs = &hsw_power_well_regs,
> > +			.hsw.idx = ICL_PW_CTL_IDX_PW_1,
> > +			.hsw.has_fuses = true,
> > +		},
> > +	},
> > +	{
> > +		.name = "DC off",
> > +		.domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> > +		.ops = &gen9_dc_off_power_well_ops,
> > +		.id = SKL_DISP_DC_OFF,
> > +	},
> > +	{
> > +		.name = "power well 3",
> > +		.domains = RKL_PW_3_POWER_DOMAINS,
> > +		.ops = &hsw_power_well_ops,
> > +		.id = ICL_DISP_PW_3,
> > +		{
> > +			.hsw.regs = &hsw_power_well_regs,
> > +			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
> > +			.hsw.irq_pipe_mask = BIT(PIPE_B),
> > +			.hsw.has_vga = true,
> > +			.hsw.has_fuses = true,
> > +		},
> > +	},
> > +	{
> > +		.name = "power well 4",
> > +		.domains = RKL_PW_4_POWER_DOMAINS,
> > +		.ops = &hsw_power_well_ops,
> > +		.id = DISP_PW_ID_NONE,
> > +		{
> > +			.hsw.regs = &hsw_power_well_regs,
> > +			.hsw.idx = ICL_PW_CTL_IDX_PW_4,
> > +			.hsw.has_fuses = true,
> > +			.hsw.irq_pipe_mask = BIT(PIPE_C),
> > +		}
> > +	},
> IMHO the order of power well is differs from TGL/ICL,
> TGL/ICL PW_4 comes after DDI and AUX IO power wells.
> Why the order is different on RKL.
> Thanks,
> Anshuman Gupta.

I'm not aware of any specific reason why PW_4 was placed after the
DDI/AUX wells on ICL, but that order seems to have been copy/pasted to
TGL too.

It seems more natural to keep the main power wells together, so I wrote
them in what I considered to be a more intuitive order here.  But
ultimately the order of the power wells in the array shouldn't have any
functional impact.


Matt

> > +	{
> > +		.name = "DDI A IO",
> > +		.domains = ICL_DDI_IO_A_POWER_DOMAINS,
> > +		.ops = &hsw_power_well_ops,
> > +		.id = DISP_PW_ID_NONE,
> > +		{
> > +			.hsw.regs = &icl_ddi_power_well_regs,
> > +			.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> > +		}
> > +	},
> > +	{
> > +		.name = "DDI B IO",
> > +		.domains = ICL_DDI_IO_B_POWER_DOMAINS,
> > +		.ops = &hsw_power_well_ops,
> > +		.id = DISP_PW_ID_NONE,
> > +		{
> > +			.hsw.regs = &icl_ddi_power_well_regs,
> > +			.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> > +		}
> > +	},
> > +	{
> > +		.name = "DDI D TC1 IO",
> > +		.domains = TGL_DDI_IO_D_TC1_POWER_DOMAINS,
> > +		.ops = &hsw_power_well_ops,
> > +		.id = DISP_PW_ID_NONE,
> > +		{
> > +			.hsw.regs = &icl_ddi_power_well_regs,
> > +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
> > +		},
> > +	},
> > +	{
> > +		.name = "DDI E TC2 IO",
> > +		.domains = TGL_DDI_IO_E_TC2_POWER_DOMAINS,
> > +		.ops = &hsw_power_well_ops,
> > +		.id = DISP_PW_ID_NONE,
> > +		{
> > +			.hsw.regs = &icl_ddi_power_well_regs,
> > +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
> > +		},
> > +	},
> > +	{
> > +		.name = "AUX A",
> > +		.domains = ICL_AUX_A_IO_POWER_DOMAINS,
> > +		.ops = &icl_aux_power_well_ops,
> > +		.id = DISP_PW_ID_NONE,
> > +		{
> > +			.hsw.regs = &icl_aux_power_well_regs,
> > +			.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> > +		},
> > +	},
> > +	{
> > +		.name = "AUX B",
> > +		.domains = ICL_AUX_B_IO_POWER_DOMAINS,
> > +		.ops = &icl_aux_power_well_ops,
> > +		.id = DISP_PW_ID_NONE,
> > +		{
> > +			.hsw.regs = &icl_aux_power_well_regs,
> > +			.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> > +		},
> > +	},
> > +	{
> > +		.name = "AUX D TC1",
> > +		.domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
> > +		.ops = &icl_aux_power_well_ops,
> > +		.id = DISP_PW_ID_NONE,
> > +		{
> > +			.hsw.regs = &icl_aux_power_well_regs,
> > +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
> > +		},
> > +	},
> > +	{
> > +		.name = "AUX E TC2",
> > +		.domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
> > +		.ops = &icl_aux_power_well_ops,
> > +		.id = DISP_PW_ID_NONE,
> > +		{
> > +			.hsw.regs = &icl_aux_power_well_regs,
> > +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
> > +		},
> > +	},
> > +};
> > +
> >  static int
> >  sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
> >  				   int disable_power_well)
> > @@ -4428,7 +4609,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> >  	 * The enabling order will be from lower to higher indexed wells,
> >  	 * the disabling order is reversed.
> >  	 */
> > -	if (IS_GEN(dev_priv, 12)) {
> > +	if (IS_ROCKETLAKE(dev_priv)) {
> > +		err = set_power_wells(power_domains, rkl_power_wells);
> > +	} else if (IS_GEN(dev_priv, 12)) {
> >  		err = set_power_wells(power_domains, tgl_power_wells);
> >  	} else if (IS_GEN(dev_priv, 11)) {
> >  		err = set_power_wells(power_domains, icl_power_wells);
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index 95ad87d4ccb3..d145fe2bed81 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -476,13 +476,13 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> >  	 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:
> >  	 *
> >  	 *  - ICL eDP/DSI transcoder
> > -	 *  - TGL pipe A
> > +	 *  - Gen12+ (except RKL) pipe A
> >  	 *
> >  	 * For any other pipe, VDSC/joining uses the power well associated with
> >  	 * the pipe in use. Hence another reference on the pipe power domain
> >  	 * will suffice. (Except no VDSC/joining on ICL pipe A.)
> >  	 */
> > -	if (INTEL_GEN(i915) >= 12 && pipe == PIPE_A)
> > +	if (INTEL_GEN(i915) >= 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
> >  		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
> >  	else if (is_pipe_dsc(crtc_state))
> >  		return POWER_DOMAIN_PIPE(pipe);
> > -- 
> > 2.24.1
> > 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 08/22] drm/i915/rkl: Add power well support
  2020-05-05 14:39     ` Matt Roper
@ 2020-05-05 16:09       ` Imre Deak
  2020-05-06 12:13         ` Anshuman Gupta
  0 siblings, 1 reply; 53+ messages in thread
From: Imre Deak @ 2020-05-05 16:09 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx, Lucas De Marchi

On Tue, May 05, 2020 at 07:39:04AM -0700, Matt Roper wrote:
> On Tue, May 05, 2020 at 10:20:58AM +0530, Anshuman Gupta wrote:
> > On 2020-05-04 at 15:52:13 -0700, Matt Roper wrote:
> > > RKL power wells are similar to TGL power wells, but have some important
> > > differences:
> > > 
> > >  * PG1 now has pipe A's VDSC (rather than sticking it in PG2)
> > >  * PG2 no longer exists
> > >  * DDI-C (aka TC-1) moves from PG1 -> PG3
> > >  * PG5 no longer exists due to the lack of a fourth pipe
> > > 
> > > Also note that what we refer to as 'DDI-C' and 'DDI-D' need to actually
> > > be programmed as TC-1 and TC-2 even though this platform doesn't have TC
> > > outputs.
> > > 
> > > Bspec: 49234
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > > Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > ---
> > >  .../drm/i915/display/intel_display_power.c    | 185 +++++++++++++++++-
> > >  drivers/gpu/drm/i915/display/intel_vdsc.c     |   4 +-
> > >  2 files changed, 186 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index 49998906cc61..71691919d101 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -2913,6 +2913,53 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > >  	BIT_ULL(POWER_DOMAIN_AUX_I_TBT)	|	\
> > >  	BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
> > >  
> > > +#define RKL_PW_4_POWER_DOMAINS (			\
> > > +	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
> > > +	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
> > > +	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
> > > +	BIT_ULL(POWER_DOMAIN_INIT))
> > > +
> > > +#define RKL_PW_3_POWER_DOMAINS (			\
> > > +	RKL_PW_4_POWER_DOMAINS |			\
> > > +	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
> > > +	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
> > > +	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
> > > +	BIT_ULL(POWER_DOMAIN_VGA) |			\
> > > +	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
> > > +	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |	\
> > > +	BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |	\
> > > +	BIT_ULL(POWER_DOMAIN_AUX_D) |			\
> > > +	BIT_ULL(POWER_DOMAIN_AUX_E) |			\
> > > +	BIT_ULL(POWER_DOMAIN_INIT))
> > > +
> > > +/*
> > > + * There is no PW_2/PG_2 on RKL.
> > > + *
> > > + * RKL PW_1/PG_1 domains (under HW/DMC control):
> > > + * - DBUF function (note: registers are in PW0)
> > > + * - PIPE_A and its planes and VDSC/joining, except VGA
> > > + * - transcoder A
> > > + * - DDI_A and DDI_B
> > > + * - FBC
> > > + *
> > > + * RKL PW_0/PG_0 domains (under HW/DMC control):
> > > + * - PCI
> > > + * - clocks except port PLL
> > > + * - shared functions:
> > > + *     * interrupts except pipe interrupts
> > > + *     * MBus except PIPE_MBUS_DBOX_CTL
> > > + *     * DBUF registers
> > > + * - central power except FBC
> > > + * - top-level GTC (DDI-level GTC is in the well associated with the DDI)
> > > + */
> > > +
> > > +#define RKL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
> > > +	RKL_PW_3_POWER_DOMAINS |			\
> > > +	BIT_ULL(POWER_DOMAIN_MODESET) |			\
> > > +	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> > > +	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
> > > +	BIT_ULL(POWER_DOMAIN_INIT))
> > > +
> > >  static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> > >  	.sync_hw = i9xx_power_well_sync_hw_noop,
> > >  	.enable = i9xx_always_on_power_well_noop,
> > > @@ -4283,6 +4330,140 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > >  	},
> > >  };
> > >  
> > > +static const struct i915_power_well_desc rkl_power_wells[] = {
> > > +	{
> > > +		.name = "always-on",
> > > +		.always_on = true,
> > > +		.domains = POWER_DOMAIN_MASK,
> > > +		.ops = &i9xx_always_on_power_well_ops,
> > > +		.id = DISP_PW_ID_NONE,
> > > +	},
> > > +	{
> > > +		.name = "power well 1",
> > > +		/* Handled by the DMC firmware */
> > > +		.always_on = true,
> > > +		.domains = 0,
> > > +		.ops = &hsw_power_well_ops,
> > > +		.id = SKL_DISP_PW_1,
> > > +		{
> > > +			.hsw.regs = &hsw_power_well_regs,
> > > +			.hsw.idx = ICL_PW_CTL_IDX_PW_1,
> > > +			.hsw.has_fuses = true,
> > > +		},
> > > +	},
> > > +	{
> > > +		.name = "DC off",
> > > +		.domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> > > +		.ops = &gen9_dc_off_power_well_ops,
> > > +		.id = SKL_DISP_DC_OFF,
> > > +	},
> > > +	{
> > > +		.name = "power well 3",
> > > +		.domains = RKL_PW_3_POWER_DOMAINS,
> > > +		.ops = &hsw_power_well_ops,
> > > +		.id = ICL_DISP_PW_3,
> > > +		{
> > > +			.hsw.regs = &hsw_power_well_regs,
> > > +			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
> > > +			.hsw.irq_pipe_mask = BIT(PIPE_B),
> > > +			.hsw.has_vga = true,
> > > +			.hsw.has_fuses = true,
> > > +		},
> > > +	},
> > > +	{
> > > +		.name = "power well 4",
> > > +		.domains = RKL_PW_4_POWER_DOMAINS,
> > > +		.ops = &hsw_power_well_ops,
> > > +		.id = DISP_PW_ID_NONE,
> > > +		{
> > > +			.hsw.regs = &hsw_power_well_regs,
> > > +			.hsw.idx = ICL_PW_CTL_IDX_PW_4,
> > > +			.hsw.has_fuses = true,
> > > +			.hsw.irq_pipe_mask = BIT(PIPE_C),
> > > +		}
> > > +	},
> > IMHO the order of power well is differs from TGL/ICL,
> > TGL/ICL PW_4 comes after DDI and AUX IO power wells.
> > Why the order is different on RKL.
> > Thanks,
> > Anshuman Gupta.
> 
> I'm not aware of any specific reason why PW_4 was placed after the
> DDI/AUX wells on ICL, but that order seems to have been copy/pasted to
> TGL too.
> 
> It seems more natural to keep the main power wells together, so I wrote
> them in what I considered to be a more intuitive order here.  But
> ultimately the order of the power wells in the array shouldn't have any
> functional impact.

The order of two power wells in the array determines their
enabling/disabling order if they are included in the same power domain.
If there is no dependency between two power wells their order in the
array is not important.

> Matt
> 
> > > +	{
> > > +		.name = "DDI A IO",
> > > +		.domains = ICL_DDI_IO_A_POWER_DOMAINS,
> > > +		.ops = &hsw_power_well_ops,
> > > +		.id = DISP_PW_ID_NONE,
> > > +		{
> > > +			.hsw.regs = &icl_ddi_power_well_regs,
> > > +			.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> > > +		}
> > > +	},
> > > +	{
> > > +		.name = "DDI B IO",
> > > +		.domains = ICL_DDI_IO_B_POWER_DOMAINS,
> > > +		.ops = &hsw_power_well_ops,
> > > +		.id = DISP_PW_ID_NONE,
> > > +		{
> > > +			.hsw.regs = &icl_ddi_power_well_regs,
> > > +			.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> > > +		}
> > > +	},
> > > +	{
> > > +		.name = "DDI D TC1 IO",
> > > +		.domains = TGL_DDI_IO_D_TC1_POWER_DOMAINS,
> > > +		.ops = &hsw_power_well_ops,
> > > +		.id = DISP_PW_ID_NONE,
> > > +		{
> > > +			.hsw.regs = &icl_ddi_power_well_regs,
> > > +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
> > > +		},
> > > +	},
> > > +	{
> > > +		.name = "DDI E TC2 IO",
> > > +		.domains = TGL_DDI_IO_E_TC2_POWER_DOMAINS,
> > > +		.ops = &hsw_power_well_ops,
> > > +		.id = DISP_PW_ID_NONE,
> > > +		{
> > > +			.hsw.regs = &icl_ddi_power_well_regs,
> > > +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
> > > +		},
> > > +	},
> > > +	{
> > > +		.name = "AUX A",
> > > +		.domains = ICL_AUX_A_IO_POWER_DOMAINS,
> > > +		.ops = &icl_aux_power_well_ops,
> > > +		.id = DISP_PW_ID_NONE,
> > > +		{
> > > +			.hsw.regs = &icl_aux_power_well_regs,
> > > +			.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> > > +		},
> > > +	},
> > > +	{
> > > +		.name = "AUX B",
> > > +		.domains = ICL_AUX_B_IO_POWER_DOMAINS,
> > > +		.ops = &icl_aux_power_well_ops,
> > > +		.id = DISP_PW_ID_NONE,
> > > +		{
> > > +			.hsw.regs = &icl_aux_power_well_regs,
> > > +			.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> > > +		},
> > > +	},
> > > +	{
> > > +		.name = "AUX D TC1",
> > > +		.domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
> > > +		.ops = &icl_aux_power_well_ops,
> > > +		.id = DISP_PW_ID_NONE,
> > > +		{
> > > +			.hsw.regs = &icl_aux_power_well_regs,
> > > +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
> > > +		},
> > > +	},
> > > +	{
> > > +		.name = "AUX E TC2",
> > > +		.domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
> > > +		.ops = &icl_aux_power_well_ops,
> > > +		.id = DISP_PW_ID_NONE,
> > > +		{
> > > +			.hsw.regs = &icl_aux_power_well_regs,
> > > +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
> > > +		},
> > > +	},
> > > +};
> > > +
> > >  static int
> > >  sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
> > >  				   int disable_power_well)
> > > @@ -4428,7 +4609,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> > >  	 * The enabling order will be from lower to higher indexed wells,
> > >  	 * the disabling order is reversed.
> > >  	 */
> > > -	if (IS_GEN(dev_priv, 12)) {
> > > +	if (IS_ROCKETLAKE(dev_priv)) {
> > > +		err = set_power_wells(power_domains, rkl_power_wells);
> > > +	} else if (IS_GEN(dev_priv, 12)) {
> > >  		err = set_power_wells(power_domains, tgl_power_wells);
> > >  	} else if (IS_GEN(dev_priv, 11)) {
> > >  		err = set_power_wells(power_domains, icl_power_wells);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > index 95ad87d4ccb3..d145fe2bed81 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > @@ -476,13 +476,13 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> > >  	 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:
> > >  	 *
> > >  	 *  - ICL eDP/DSI transcoder
> > > -	 *  - TGL pipe A
> > > +	 *  - Gen12+ (except RKL) pipe A
> > >  	 *
> > >  	 * For any other pipe, VDSC/joining uses the power well associated with
> > >  	 * the pipe in use. Hence another reference on the pipe power domain
> > >  	 * will suffice. (Except no VDSC/joining on ICL pipe A.)
> > >  	 */
> > > -	if (INTEL_GEN(i915) >= 12 && pipe == PIPE_A)
> > > +	if (INTEL_GEN(i915) >= 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
> > >  		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
> > >  	else if (is_pipe_dsc(crtc_state))
> > >  		return POWER_DOMAIN_PIPE(pipe);
> > > -- 
> > > 2.24.1
> > > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 15/22] drm/i915/rkl: Add DDC pin mapping
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 15/22] drm/i915/rkl: Add DDC pin mapping Matt Roper
@ 2020-05-06  9:19   ` Srivatsa, Anusha
  0 siblings, 0 replies; 53+ messages in thread
From: Srivatsa, Anusha @ 2020-05-06  9:19 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx



> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt
> Roper
> Sent: Tuesday, May 5, 2020 4:22 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 15/22] drm/i915/rkl: Add DDC pin mapping
> 
> The pin mapping for the final two outputs varies according to which PCH is
> present on the platform:  with TGP the pins are remapped into the TC range,
> whereas with CMP they stay in the traditional combo output range.
> 
> Bspec: 49181
> Cc: Aditya Swarup <aditya.swarup@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_hdmi.c | 22 +++++++++++++++++++++-
>  1 file changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 010f37240710..a31a98d26882 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3082,6 +3082,24 @@ static u8 mcc_port_to_ddc_pin(struct
> drm_i915_private *dev_priv, enum port port)
>  	return ddc_pin;
>  }
> 
> +static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum
> +port port) {
> +	enum phy phy = intel_port_to_phy(dev_priv, port);
> +
> +	WARN_ON(port == PORT_C);
> +
> +	/*
> +	 * Pin mapping for RKL depends on which PCH is present.  With TGP,
> the
> +	 * final two outputs use type-c pins, even though they're actually
> +	 * combo outputs.  With CMP, the traditional DDI A-D pins are used for
> +	 * all outputs.
> +	 */
> +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
> +		return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
> +
> +	return GMBUS_PIN_1_BXT + phy;
> +}
> +
>  static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
>  			      enum port port)
>  {
> @@ -3119,7 +3137,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder
> *encoder)
>  		return ddc_pin;
>  	}
> 
> -	if (HAS_PCH_MCC(dev_priv))
> +	if (IS_ROCKETLAKE(dev_priv))
> +		ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
> +	else if (HAS_PCH_MCC(dev_priv))
>  		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
>  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>  		ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 18/22] drm/i915/rkl: Handle comp master/slave relationships for PHYs
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 18/22] drm/i915/rkl: Handle comp master/slave relationships for PHYs Matt Roper
@ 2020-05-06  9:20   ` Srivatsa, Anusha
  0 siblings, 0 replies; 53+ messages in thread
From: Srivatsa, Anusha @ 2020-05-06  9:20 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx; +Cc: De Marchi, Lucas



> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt
> Roper
> Sent: Tuesday, May 5, 2020 4:22 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH v2 18/22] drm/i915/rkl: Handle comp master/slave
> relationships for PHYs
> 
> Certain combo PHYs act as a compensation master to other PHYs and need to
> be initialized with a special irefgen bit in the PORT_COMP_DW8 register.
> Previously PHY A was the only compensation master (for PHYs B & C), but RKL
> adds a fourth PHY which is slaved to PHY C instead.
> 
> Bspec: 49291
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Aditya Swarup <aditya.swarup@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  .../gpu/drm/i915/display/intel_combo_phy.c    | 25 +++++++++++++++++--
>  1 file changed, 23 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 43d8784f6fa0..77b04bb3ec62 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -234,6 +234,27 @@ static bool ehl_vbt_ddi_d_present(struct
> drm_i915_private *i915)
>  	return false;
>  }
> 
> +static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy
> +phy) {
> +	/*
> +	 * Certain PHYs are connected to compensation resistors and act
> +	 * as masters to other PHYs.
> +	 *
> +	 * ICL,TGL:
> +	 *   A(master) -> B(slave), C(slave)
> +	 * RKL:
> +	 *   A(master) -> B(slave)
> +	 *   C(master) -> D(slave)
> +	 *
> +	 * We must set the IREFGEN bit for any PHY acting as a master
> +	 * to another PHY.
> +	 */
> +	if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C)
> +		return true;
> +
> +	return phy == PHY_A;
> +}
> +
>  static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
>  				       enum phy phy)
>  {
> @@ -245,7 +266,7 @@ static bool icl_combo_phy_verify_state(struct
> drm_i915_private *dev_priv,
> 
>  	ret = cnl_verify_procmon_ref_values(dev_priv, phy);
> 
> -	if (phy == PHY_A) {
> +	if (phy_is_master(dev_priv, phy)) {
>  		ret &= check_phy_reg(dev_priv, phy,
> ICL_PORT_COMP_DW8(phy),
>  				     IREFGEN, IREFGEN);
> 
> @@ -356,7 +377,7 @@ static void icl_combo_phys_init(struct
> drm_i915_private *dev_priv)
>  skip_phy_misc:
>  		cnl_set_procmon_ref_values(dev_priv, phy);
> 
> -		if (phy == PHY_A) {
> +		if (phy_is_master(dev_priv, phy)) {
>  			val = intel_de_read(dev_priv,
> ICL_PORT_COMP_DW8(phy));
>  			val |= IREFGEN;
>  			intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy),
> val);
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support Matt Roper
@ 2020-05-06 11:51   ` Srivatsa, Anusha
  2020-05-19 23:57     ` Lucas De Marchi
  0 siblings, 1 reply; 53+ messages in thread
From: Srivatsa, Anusha @ 2020-05-06 11:51 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx; +Cc: De Marchi, Lucas



> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt
> Roper
> Sent: Tuesday, May 5, 2020 4:22 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support
> 
> RKL re-uses the same stolen memory registers as TGL and ICL.
> 
> Bspec: 52055
> Bspec: 49589
> Bspec: 49636
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Confirmed with Spec.
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  arch/x86/kernel/early-quirks.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index 2f9ec14be3b1..a4b5af03dcc1 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -550,6 +550,7 @@ static const struct pci_device_id intel_early_ids[]
> __initconst = {
>  	INTEL_ICL_11_IDS(&gen11_early_ops),
>  	INTEL_EHL_IDS(&gen11_early_ops),
>  	INTEL_TGL_12_IDS(&gen11_early_ops),
> +	INTEL_RKL_IDS(&gen11_early_ops),
>  };
> 
>  struct resource intel_graphics_stolen_res __ro_after_init =
> DEFINE_RES_MEM(0, 0);
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 08/22] drm/i915/rkl: Add power well support
  2020-05-05 16:09       ` Imre Deak
@ 2020-05-06 12:13         ` Anshuman Gupta
  0 siblings, 0 replies; 53+ messages in thread
From: Anshuman Gupta @ 2020-05-06 12:13 UTC (permalink / raw)
  To: Imre Deak; +Cc: Lucas De Marchi, intel-gfx

On 2020-05-05 at 19:09:54 +0300, Imre Deak wrote:
> On Tue, May 05, 2020 at 07:39:04AM -0700, Matt Roper wrote:
> > On Tue, May 05, 2020 at 10:20:58AM +0530, Anshuman Gupta wrote:
> > > On 2020-05-04 at 15:52:13 -0700, Matt Roper wrote:
> > > > RKL power wells are similar to TGL power wells, but have some important
> > > > differences:
> > > > 
> > > >  * PG1 now has pipe A's VDSC (rather than sticking it in PG2)
> > > >  * PG2 no longer exists
> > > >  * DDI-C (aka TC-1) moves from PG1 -> PG3
> > > >  * PG5 no longer exists due to the lack of a fourth pipe
> > > > 
> > > > Also note that what we refer to as 'DDI-C' and 'DDI-D' need to actually
> > > > be programmed as TC-1 and TC-2 even though this platform doesn't have TC
> > > > outputs.
Looks good to me.
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > > 
> > > > Bspec: 49234
> > > > Cc: Imre Deak <imre.deak@intel.com>
> > > > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > > ---
> > > >  .../drm/i915/display/intel_display_power.c    | 185 +++++++++++++++++-
> > > >  drivers/gpu/drm/i915/display/intel_vdsc.c     |   4 +-
> > > >  2 files changed, 186 insertions(+), 3 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > index 49998906cc61..71691919d101 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > @@ -2913,6 +2913,53 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > > >  	BIT_ULL(POWER_DOMAIN_AUX_I_TBT)	|	\
> > > >  	BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
> > > >  
> > > > +#define RKL_PW_4_POWER_DOMAINS (			\
> > > > +	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
> > > > +	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
> > > > +	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
> > > > +	BIT_ULL(POWER_DOMAIN_INIT))
> > > > +
> > > > +#define RKL_PW_3_POWER_DOMAINS (			\
> > > > +	RKL_PW_4_POWER_DOMAINS |			\
> > > > +	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
> > > > +	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
> > > > +	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
> > > > +	BIT_ULL(POWER_DOMAIN_VGA) |			\
> > > > +	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
> > > > +	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |	\
> > > > +	BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |	\
> > > > +	BIT_ULL(POWER_DOMAIN_AUX_D) |			\
> > > > +	BIT_ULL(POWER_DOMAIN_AUX_E) |			\
> > > > +	BIT_ULL(POWER_DOMAIN_INIT))
> > > > +
> > > > +/*
> > > > + * There is no PW_2/PG_2 on RKL.
> > > > + *
> > > > + * RKL PW_1/PG_1 domains (under HW/DMC control):
> > > > + * - DBUF function (note: registers are in PW0)
> > > > + * - PIPE_A and its planes and VDSC/joining, except VGA
> > > > + * - transcoder A
> > > > + * - DDI_A and DDI_B
> > > > + * - FBC
> > > > + *
> > > > + * RKL PW_0/PG_0 domains (under HW/DMC control):
> > > > + * - PCI
> > > > + * - clocks except port PLL
> > > > + * - shared functions:
> > > > + *     * interrupts except pipe interrupts
> > > > + *     * MBus except PIPE_MBUS_DBOX_CTL
> > > > + *     * DBUF registers
> > > > + * - central power except FBC
> > > > + * - top-level GTC (DDI-level GTC is in the well associated with the DDI)
> > > > + */
> > > > +
> > > > +#define RKL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
> > > > +	RKL_PW_3_POWER_DOMAINS |			\
> > > > +	BIT_ULL(POWER_DOMAIN_MODESET) |			\
> > > > +	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> > > > +	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
> > > > +	BIT_ULL(POWER_DOMAIN_INIT))
> > > > +
> > > >  static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> > > >  	.sync_hw = i9xx_power_well_sync_hw_noop,
> > > >  	.enable = i9xx_always_on_power_well_noop,
> > > > @@ -4283,6 +4330,140 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > > >  	},
> > > >  };
> > > >  
> > > > +static const struct i915_power_well_desc rkl_power_wells[] = {
> > > > +	{
> > > > +		.name = "always-on",
> > > > +		.always_on = true,
> > > > +		.domains = POWER_DOMAIN_MASK,
> > > > +		.ops = &i9xx_always_on_power_well_ops,
> > > > +		.id = DISP_PW_ID_NONE,
> > > > +	},
> > > > +	{
> > > > +		.name = "power well 1",
> > > > +		/* Handled by the DMC firmware */
> > > > +		.always_on = true,
> > > > +		.domains = 0,
> > > > +		.ops = &hsw_power_well_ops,
> > > > +		.id = SKL_DISP_PW_1,
> > > > +		{
> > > > +			.hsw.regs = &hsw_power_well_regs,
> > > > +			.hsw.idx = ICL_PW_CTL_IDX_PW_1,
> > > > +			.hsw.has_fuses = true,
> > > > +		},
> > > > +	},
> > > > +	{
> > > > +		.name = "DC off",
> > > > +		.domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> > > > +		.ops = &gen9_dc_off_power_well_ops,
> > > > +		.id = SKL_DISP_DC_OFF,
> > > > +	},
> > > > +	{
> > > > +		.name = "power well 3",
> > > > +		.domains = RKL_PW_3_POWER_DOMAINS,
> > > > +		.ops = &hsw_power_well_ops,
> > > > +		.id = ICL_DISP_PW_3,
> > > > +		{
> > > > +			.hsw.regs = &hsw_power_well_regs,
> > > > +			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
> > > > +			.hsw.irq_pipe_mask = BIT(PIPE_B),
> > > > +			.hsw.has_vga = true,
> > > > +			.hsw.has_fuses = true,
> > > > +		},
> > > > +	},
> > > > +	{
> > > > +		.name = "power well 4",
> > > > +		.domains = RKL_PW_4_POWER_DOMAINS,
> > > > +		.ops = &hsw_power_well_ops,
> > > > +		.id = DISP_PW_ID_NONE,
> > > > +		{
> > > > +			.hsw.regs = &hsw_power_well_regs,
> > > > +			.hsw.idx = ICL_PW_CTL_IDX_PW_4,
> > > > +			.hsw.has_fuses = true,
> > > > +			.hsw.irq_pipe_mask = BIT(PIPE_C),
> > > > +		}
> > > > +	},
> > > IMHO the order of power well is differs from TGL/ICL,
> > > TGL/ICL PW_4 comes after DDI and AUX IO power wells.
> > > Why the order is different on RKL.
> > > Thanks,
> > > Anshuman Gupta.
> > 
> > I'm not aware of any specific reason why PW_4 was placed after the
> > DDI/AUX wells on ICL, but that order seems to have been copy/pasted to
> > TGL too.
> > 
> > It seems more natural to keep the main power wells together, so I wrote
> > them in what I considered to be a more intuitive order here.  But
> > ultimately the order of the power wells in the array shouldn't have any
> > functional impact.
> 
> The order of two power wells in the array determines their
> enabling/disabling order if they are included in the same power domain.
> If there is no dependency between two power wells their order in the
> array is not important.
> 
> > Matt
> > 
> > > > +	{
> > > > +		.name = "DDI A IO",
> > > > +		.domains = ICL_DDI_IO_A_POWER_DOMAINS,
> > > > +		.ops = &hsw_power_well_ops,
> > > > +		.id = DISP_PW_ID_NONE,
> > > > +		{
> > > > +			.hsw.regs = &icl_ddi_power_well_regs,
> > > > +			.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> > > > +		}
> > > > +	},
> > > > +	{
> > > > +		.name = "DDI B IO",
> > > > +		.domains = ICL_DDI_IO_B_POWER_DOMAINS,
> > > > +		.ops = &hsw_power_well_ops,
> > > > +		.id = DISP_PW_ID_NONE,
> > > > +		{
> > > > +			.hsw.regs = &icl_ddi_power_well_regs,
> > > > +			.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> > > > +		}
> > > > +	},
> > > > +	{
> > > > +		.name = "DDI D TC1 IO",
> > > > +		.domains = TGL_DDI_IO_D_TC1_POWER_DOMAINS,
> > > > +		.ops = &hsw_power_well_ops,
> > > > +		.id = DISP_PW_ID_NONE,
> > > > +		{
> > > > +			.hsw.regs = &icl_ddi_power_well_regs,
> > > > +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
> > > > +		},
> > > > +	},
> > > > +	{
> > > > +		.name = "DDI E TC2 IO",
> > > > +		.domains = TGL_DDI_IO_E_TC2_POWER_DOMAINS,
> > > > +		.ops = &hsw_power_well_ops,
> > > > +		.id = DISP_PW_ID_NONE,
> > > > +		{
> > > > +			.hsw.regs = &icl_ddi_power_well_regs,
> > > > +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
> > > > +		},
> > > > +	},
> > > > +	{
> > > > +		.name = "AUX A",
> > > > +		.domains = ICL_AUX_A_IO_POWER_DOMAINS,
> > > > +		.ops = &icl_aux_power_well_ops,
> > > > +		.id = DISP_PW_ID_NONE,
> > > > +		{
> > > > +			.hsw.regs = &icl_aux_power_well_regs,
> > > > +			.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> > > > +		},
> > > > +	},
> > > > +	{
> > > > +		.name = "AUX B",
> > > > +		.domains = ICL_AUX_B_IO_POWER_DOMAINS,
> > > > +		.ops = &icl_aux_power_well_ops,
> > > > +		.id = DISP_PW_ID_NONE,
> > > > +		{
> > > > +			.hsw.regs = &icl_aux_power_well_regs,
> > > > +			.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> > > > +		},
> > > > +	},
> > > > +	{
> > > > +		.name = "AUX D TC1",
> > > > +		.domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
> > > > +		.ops = &icl_aux_power_well_ops,
> > > > +		.id = DISP_PW_ID_NONE,
> > > > +		{
> > > > +			.hsw.regs = &icl_aux_power_well_regs,
> > > > +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
> > > > +		},
> > > > +	},
> > > > +	{
> > > > +		.name = "AUX E TC2",
> > > > +		.domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
> > > > +		.ops = &icl_aux_power_well_ops,
> > > > +		.id = DISP_PW_ID_NONE,
> > > > +		{
> > > > +			.hsw.regs = &icl_aux_power_well_regs,
> > > > +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
> > > > +		},
> > > > +	},
> > > > +};
> > > > +
> > > >  static int
> > > >  sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
> > > >  				   int disable_power_well)
> > > > @@ -4428,7 +4609,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> > > >  	 * The enabling order will be from lower to higher indexed wells,
> > > >  	 * the disabling order is reversed.
> > > >  	 */
> > > > -	if (IS_GEN(dev_priv, 12)) {
> > > > +	if (IS_ROCKETLAKE(dev_priv)) {
> > > > +		err = set_power_wells(power_domains, rkl_power_wells);
> > > > +	} else if (IS_GEN(dev_priv, 12)) {
> > > >  		err = set_power_wells(power_domains, tgl_power_wells);
> > > >  	} else if (IS_GEN(dev_priv, 11)) {
> > > >  		err = set_power_wells(power_domains, icl_power_wells);
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > > index 95ad87d4ccb3..d145fe2bed81 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > > @@ -476,13 +476,13 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> > > >  	 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:
> > > >  	 *
> > > >  	 *  - ICL eDP/DSI transcoder
> > > > -	 *  - TGL pipe A
> > > > +	 *  - Gen12+ (except RKL) pipe A
> > > >  	 *
> > > >  	 * For any other pipe, VDSC/joining uses the power well associated with
> > > >  	 * the pipe in use. Hence another reference on the pipe power domain
> > > >  	 * will suffice. (Except no VDSC/joining on ICL pipe A.)
> > > >  	 */
> > > > -	if (INTEL_GEN(i915) >= 12 && pipe == PIPE_A)
> > > > +	if (INTEL_GEN(i915) >= 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
> > > >  		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
> > > >  	else if (is_pipe_dsc(crtc_state))
> > > >  		return POWER_DOMAIN_PIPE(pipe);
> > > > -- 
> > > > 2.24.1
> > > > 
> > 
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > VTT-OSGC Platform Enablement
> > Intel Corporation
> > (916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B Matt Roper
@ 2020-05-06 13:49   ` Srivatsa, Anusha
  2020-05-06 16:49     ` Matt Roper
  0 siblings, 1 reply; 53+ messages in thread
From: Srivatsa, Anusha @ 2020-05-06 13:49 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx



> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt
> Roper
> Sent: Tuesday, May 5, 2020 4:22 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC for
> PHY's A and B
> 
> Since the number of platforms with this restriction are growing, let's separate
> out the platform logic into a has_phy_misc() function.
> 
> Bspec: 50107
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_combo_phy.c    | 30 +++++++++++--------
>  1 file changed, 17 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 9ff05ec12115..43d8784f6fa0 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -181,11 +181,25 @@ static void cnl_combo_phys_uninit(struct
> drm_i915_private *dev_priv)
>  	intel_de_write(dev_priv, CHICKEN_MISC_2, val);  }
> 
> +static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) {
> +	/*
> +	 * Some platforms only expect PHY_MISC to be programmed for PHY-A
> and
> +	 * PHY-B and may not even have instances of the register for the
> +	 * other combo PHY's.
> +	 */
> +	if (IS_ELKHARTLAKE(i915) ||
> +	    IS_ROCKETLAKE(i915))
> +		return phy < PHY_C;
According BSpec 50107, there is an instance of this for combo PHY C as well. 

Anusha
> +
> +	return true;
> +}
> +
>  static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
>  				  enum phy phy)
>  {
>  	/* The PHY C added by EHL has no PHY_MISC register */
> -	if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
> +	if (!has_phy_misc(dev_priv, phy))
>  		return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy))
> & COMP_INIT;
>  	else
>  		return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & @@ -
> 317,12 +331,7 @@ static void icl_combo_phys_init(struct drm_i915_private
> *dev_priv)
>  			continue;
>  		}
> 
> -		/*
> -		 * Although EHL adds a combo PHY C, there's no PHY_MISC
> -		 * register for it and no need to program the
> -		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
> -		 */
> -		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
> +		if (!has_phy_misc(dev_priv, phy))
>  			goto skip_phy_misc;
> 
>  		/*
> @@ -376,12 +385,7 @@ static void icl_combo_phys_uninit(struct
> drm_i915_private *dev_priv)
>  				 "Combo PHY %c HW state changed
> unexpectedly\n",
>  				 phy_name(phy));
> 
> -		/*
> -		 * Although EHL adds a combo PHY C, there's no PHY_MISC
> -		 * register for it and no need to program the
> -		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
> -		 */
> -		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
> +		if (!has_phy_misc(dev_priv, phy))
>  			goto skip_phy_misc;
> 
>  		val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B
  2020-05-06 13:49   ` Srivatsa, Anusha
@ 2020-05-06 16:49     ` Matt Roper
  2020-05-07 11:22       ` Srivatsa, Anusha
  0 siblings, 1 reply; 53+ messages in thread
From: Matt Roper @ 2020-05-06 16:49 UTC (permalink / raw)
  To: Srivatsa, Anusha; +Cc: intel-gfx

On Wed, May 06, 2020 at 06:49:06AM -0700, Srivatsa, Anusha wrote:
> 
> 
> > -----Original Message----- From: Intel-gfx
> > <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt Roper
> > Sent: Tuesday, May 5, 2020 4:22 AM To:
> > intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v2
> > 10/22] drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B
> > 
> > Since the number of platforms with this restriction are growing,
> > let's separate out the platform logic into a has_phy_misc()
> > function.
> > 
> > Bspec: 50107 Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > --- .../gpu/drm/i915/display/intel_combo_phy.c    | 30
> > +++++++++++-------- 1 file changed, 17 insertions(+), 13
> > deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> > b/drivers/gpu/drm/i915/display/intel_combo_phy.c index
> > 9ff05ec12115..43d8784f6fa0 100644 ---
> > a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++
> > b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -181,11 +181,25
> > @@ static void cnl_combo_phys_uninit(struct drm_i915_private
> > *dev_priv) intel_de_write(dev_priv, CHICKEN_MISC_2, val);  }
> > 
> > +static bool has_phy_misc(struct drm_i915_private *i915, enum phy
> > phy) { +	/* +	 * Some platforms only expect PHY_MISC to be
> > programmed for PHY-A and +	 * PHY-B and may not even have instances
> > of the register for the +	 * other combo PHY's.  +	 */ + if
> > (IS_ELKHARTLAKE(i915) || +	    IS_ROCKETLAKE(i915)) + return phy <
> > PHY_C;
> According BSpec 50107, there is an instance of this for combo PHY C as
> well. 
> 
Yeah, there's technically an instance of the register, but the only
field in it that our driver programs has a RKL programming note that
says "This register field need only be programmed for port A and B."


Matt

> Anusha
> > +
> > +	return true;
> > +}
> > +
> >  static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
> >  				  enum phy phy)
> >  {
> >  	/* The PHY C added by EHL has no PHY_MISC register */
> > -	if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
> > +	if (!has_phy_misc(dev_priv, phy))
> >  		return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy))
> > & COMP_INIT;
> >  	else
> >  		return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & @@ -
> > 317,12 +331,7 @@ static void icl_combo_phys_init(struct drm_i915_private
> > *dev_priv)
> >  			continue;
> >  		}
> > 
> > -		/*
> > -		 * Although EHL adds a combo PHY C, there's no PHY_MISC
> > -		 * register for it and no need to program the
> > -		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
> > -		 */
> > -		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
> > +		if (!has_phy_misc(dev_priv, phy))
> >  			goto skip_phy_misc;
> > 
> >  		/*
> > @@ -376,12 +385,7 @@ static void icl_combo_phys_uninit(struct
> > drm_i915_private *dev_priv)
> >  				 "Combo PHY %c HW state changed
> > unexpectedly\n",
> >  				 phy_name(phy));
> > 
> > -		/*
> > -		 * Although EHL adds a combo PHY C, there's no PHY_MISC
> > -		 * register for it and no need to program the
> > -		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
> > -		 */
> > -		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
> > +		if (!has_phy_misc(dev_priv, phy))
> >  			goto skip_phy_misc;
> > 
> >  		val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
> > --
> > 2.24.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 16/22] drm/i915/rkl: Don't try to access transcoder D
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 16/22] drm/i915/rkl: Don't try to access transcoder D Matt Roper
@ 2020-05-06 20:34   ` Matt Roper
  2020-05-06 21:21   ` [Intel-gfx] [PATCH v3 " Matt Roper
  1 sibling, 0 replies; 53+ messages in thread
From: Matt Roper @ 2020-05-06 20:34 UTC (permalink / raw)
  To: intel-gfx

On Mon, May 04, 2020 at 03:52:21PM -0700, Matt Roper wrote:
> There are a couple places in our driver that loop over transcoders A..D
> for gen11+; since RKL only has three pipes/transcoders, this can lead to
> unclaimed register reads/writes.  We should add checks for transcoder
> existence where appropriate.
> 
> Cc: Aditya Swarup <aditya.swarup@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 3 +++
>  drivers/gpu/drm/i915/i915_irq.c              | 6 ++++++
>  2 files changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index fcfc3812ef28..2eeafda82188 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11007,6 +11007,9 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
>  		else
>  			cpu_transcoder = TRANSCODER_DSI_C;
>  
> +		if (!HAS_TRANSCODER(dev_priv, cpu_transcoder))
> +			continue;
> +

It looks like this hunk wound up in the wrong function after a conflict
resolution.  It was supposed to be in icl_get_trans_port_sync_config()
instead (this BXT function doesn't execute on gen >= 11).


Matt

>  		power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
>  		drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
>  
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 622986759ec6..1381cb530c2f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2849,6 +2849,9 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
>  		for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
>  			enum intel_display_power_domain domain;
>  
> +			if (!HAS_TRANSCODER(dev_priv, trans))
> +				continue;
> +
>  			domain = POWER_DOMAIN_TRANSCODER(trans);
>  			if (!intel_display_power_is_enabled(dev_priv, domain))
>  				continue;
> @@ -3399,6 +3402,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  		for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
>  			enum intel_display_power_domain domain;
>  
> +			if (!HAS_TRANSCODER(dev_priv, trans))
> +				continue;
> +
>  			domain = POWER_DOMAIN_TRANSCODER(trans);
>  			if (!intel_display_power_is_enabled(dev_priv, domain))
>  				continue;
> -- 
> 2.24.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] [PATCH v3 16/22] drm/i915/rkl: Don't try to access transcoder D
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 16/22] drm/i915/rkl: Don't try to access transcoder D Matt Roper
  2020-05-06 20:34   ` Matt Roper
@ 2020-05-06 21:21   ` Matt Roper
  1 sibling, 0 replies; 53+ messages in thread
From: Matt Roper @ 2020-05-06 21:21 UTC (permalink / raw)
  To: intel-gfx

There are a couple places in our driver that loop over transcoders A..D
for gen11+; since RKL only has three pipes/transcoders, this can lead to
unclaimed register reads/writes.  We should add checks for transcoder
existence where appropriate.

v2: Move one transcoder check that wound up in the wrong function after
    conflict resolution.  It belongs in bdw_get_trans_port_sync_config
    rather than bxt_get_dsi_transcoder_state.

Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++
 drivers/gpu/drm/i915/i915_irq.c          | 6 ++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 0ab03282c397..f93bc0661d00 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4131,6 +4131,9 @@ static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
 		enum intel_display_power_domain power_domain;
 		intel_wakeref_t trans_wakeref;
 
+		if (!HAS_TRANSCODER(dev_priv, cpu_transcoder))
+			continue;
+
 		power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 		trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
 								   power_domain);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3c3fb9d9df62..297d4cacfb6a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2849,6 +2849,9 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
 		for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
 			enum intel_display_power_domain domain;
 
+			if (!HAS_TRANSCODER(dev_priv, trans))
+				continue;
+
 			domain = POWER_DOMAIN_TRANSCODER(trans);
 			if (!intel_display_power_is_enabled(dev_priv, domain))
 				continue;
@@ -3397,6 +3400,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 		for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
 			enum intel_display_power_domain domain;
 
+			if (!HAS_TRANSCODER(dev_priv, trans))
+				continue;
+
 			domain = POWER_DOMAIN_TRANSCODER(trans);
 			if (!intel_display_power_is_enabled(dev_priv, domain))
 				continue;
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Rocket Lake (rev5)
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (24 preceding siblings ...)
  2020-05-05 13:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-05-06 22:31 ` Patchwork
  2020-05-06 22:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
  2020-05-07  2:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  27 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2020-05-06 22:31 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

== Series Details ==

Series: Introduce Rocket Lake (rev5)
URL   : https://patchwork.freedesktop.org/series/76826/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
992fe0e5bf6f drm/i915/rkl: Add RKL platform info and PCI ids
-:35: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#35: FILE: drivers/gpu/drm/i915/i915_drv.h:1522:
+#define IS_RKL_REVID(p, since, until) \
+	(IS_ROCKETLAKE(p) && IS_REVID(p, since, until))

-:102: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#102: FILE: include/drm/i915_pciids.h:609:
+#define INTEL_RKL_IDS(info) \
+	INTEL_VGA_DEVICE(0x4C80, info), \
+	INTEL_VGA_DEVICE(0x4C8A, info), \
+	INTEL_VGA_DEVICE(0x4C8B, info), \
+	INTEL_VGA_DEVICE(0x4C8C, info), \
+	INTEL_VGA_DEVICE(0x4C90, info), \
+	INTEL_VGA_DEVICE(0x4C9A, info)

-:102: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#102: FILE: include/drm/i915_pciids.h:609:
+#define INTEL_RKL_IDS(info) \
+	INTEL_VGA_DEVICE(0x4C80, info), \
+	INTEL_VGA_DEVICE(0x4C8A, info), \
+	INTEL_VGA_DEVICE(0x4C8B, info), \
+	INTEL_VGA_DEVICE(0x4C8C, info), \
+	INTEL_VGA_DEVICE(0x4C90, info), \
+	INTEL_VGA_DEVICE(0x4C9A, info)

total: 1 errors, 0 warnings, 2 checks, 69 lines checked
15e40d80e929 x86/gpu: add RKL stolen memory support
294ed2fa7047 drm/i915/rkl: Re-use TGL GuC/HuC firmware
5077d28b310e drm/i915/rkl: Load DMC firmware for Rocket Lake
a828a46df1e1 drm/i915/rkl: Add PCH support
79d1afd4876a drm/i915/rkl: Update memory bandwidth parameters
baec83a0ef12 drm/i915/rkl: Limit number of universal planes to 5
d2f8442de5ae drm/i915/rkl: Add power well support
58ad52c714dd drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2
-:36: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#36: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:5261:
+		min_buddy = max_buddy = 0;

total: 0 errors, 0 warnings, 1 checks, 84 lines checked
c601db6a20fd drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B
cbc732494a17 drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
ffcedfb908db drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs
aa69de72e7ad drm/i915/rkl: Setup ports/phys
c3f23b36db92 drm/i915/rkl: provide port/phy mapping for vbt
-:17: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#17: 
[drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:275:DDI A]

total: 0 errors, 1 warnings, 0 checks, 104 lines checked
06afd0a313fb drm/i915/rkl: Add DDC pin mapping
907417b5599f drm/i915/rkl: Don't try to access transcoder D
01eeaee24e99 drm/i915/rkl: Don't try to read out DSI transcoders
f53b5ed86243 drm/i915/rkl: Handle comp master/slave relationships for PHYs
0728f1c7d53c drm/i915/rkl: Add DPLL4 support
a31143c0e350 drm/i915/rkl: Handle HTI
-:92: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#92: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:274:
+{
+

-:154: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#154: FILE: drivers/gpu/drm/i915/i915_reg.h:2903:
+#define   HDPORT_PHY_USED_DP(phy)	REG_BIT(2*phy + 2)
                                  	         ^

-:154: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'phy' may be better as '(phy)' to avoid precedence issues
#154: FILE: drivers/gpu/drm/i915/i915_reg.h:2903:
+#define   HDPORT_PHY_USED_DP(phy)	REG_BIT(2*phy + 2)

-:155: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#155: FILE: drivers/gpu/drm/i915/i915_reg.h:2904:
+#define   HDPORT_PHY_USED_HDMI(phy)	REG_BIT(2*phy + 1)
                                    	         ^

-:155: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'phy' may be better as '(phy)' to avoid precedence issues
#155: FILE: drivers/gpu/drm/i915/i915_reg.h:2904:
+#define   HDPORT_PHY_USED_HDMI(phy)	REG_BIT(2*phy + 1)

total: 0 errors, 0 warnings, 5 checks, 116 lines checked
b71b6be89206 drm/i915/rkl: Disable PSR2
a956d64b8996 drm/i915/rkl: Add initial workarounds

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for Introduce Rocket Lake (rev5)
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (25 preceding siblings ...)
  2020-05-06 22:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Rocket Lake (rev5) Patchwork
@ 2020-05-06 22:55 ` Patchwork
  2020-05-07  2:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  27 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2020-05-06 22:55 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

== Series Details ==

Series: Introduce Rocket Lake (rev5)
URL   : https://patchwork.freedesktop.org/series/76826/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8438 -> Patchwork_17595
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/index.html

Known issues
------------

  Here are the changes found in Patchwork_17595 that come from known issues:

### IGT changes ###

#### Warnings ####

  * igt@i915_pm_rpm@basic-rte:
    - fi-kbl-guc:         [SKIP][1] ([fdo#109271]) -> [FAIL][2] ([i915#579])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579


Participating hosts (51 -> 44)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8438 -> Patchwork_17595

  CI-20190529: 20190529
  CI_DRM_8438: 9463611ee93f4b254044b8b2467a1e81f942ad01 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5635: e83abfca61d407d12eee4d25bb0e8686337a7791 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17595: a956d64b89965d60f21052c98e2383108c95d17f @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

a956d64b8996 drm/i915/rkl: Add initial workarounds
b71b6be89206 drm/i915/rkl: Disable PSR2
a31143c0e350 drm/i915/rkl: Handle HTI
0728f1c7d53c drm/i915/rkl: Add DPLL4 support
f53b5ed86243 drm/i915/rkl: Handle comp master/slave relationships for PHYs
01eeaee24e99 drm/i915/rkl: Don't try to read out DSI transcoders
907417b5599f drm/i915/rkl: Don't try to access transcoder D
06afd0a313fb drm/i915/rkl: Add DDC pin mapping
c3f23b36db92 drm/i915/rkl: provide port/phy mapping for vbt
aa69de72e7ad drm/i915/rkl: Setup ports/phys
ffcedfb908db drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs
cbc732494a17 drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
c601db6a20fd drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B
58ad52c714dd drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2
d2f8442de5ae drm/i915/rkl: Add power well support
baec83a0ef12 drm/i915/rkl: Limit number of universal planes to 5
79d1afd4876a drm/i915/rkl: Update memory bandwidth parameters
a828a46df1e1 drm/i915/rkl: Add PCH support
5077d28b310e drm/i915/rkl: Load DMC firmware for Rocket Lake
294ed2fa7047 drm/i915/rkl: Re-use TGL GuC/HuC firmware
15e40d80e929 x86/gpu: add RKL stolen memory support
992fe0e5bf6f drm/i915/rkl: Add RKL platform info and PCI ids

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* [Intel-gfx] ✓ Fi.CI.IGT: success for Introduce Rocket Lake (rev5)
  2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
                   ` (26 preceding siblings ...)
  2020-05-06 22:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-05-07  2:12 ` Patchwork
  27 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2020-05-07  2:12 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

== Series Details ==

Series: Introduce Rocket Lake (rev5)
URL   : https://patchwork.freedesktop.org/series/76826/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8438_full -> Patchwork_17595_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_17595_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-kbl:          [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-kbl3/igt@gem_workarounds@suspend-resume-fd.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-kbl:          [PASS][3] -> [DMESG-WARN][4] ([i915#1436] / [i915#716])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-kbl4/igt@gen9_exec_parse@allowed-all.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-kbl4/igt@gen9_exec_parse@allowed-all.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
    - shard-skl:          [PASS][5] -> [INCOMPLETE][6] ([i915#300])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-skl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [PASS][7] -> [DMESG-WARN][8] ([i915#180])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge:
    - shard-kbl:          [PASS][9] -> [FAIL][10] ([i915#70] / [i915#93] / [i915#95])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-kbl3/igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-kbl1/igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge.html

  * igt@kms_cursor_legacy@cursor-vs-flip-toggle:
    - shard-hsw:          [PASS][11] -> [FAIL][12] ([i915#57])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-hsw2/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-kbl:          [PASS][13] -> [DMESG-WARN][14] ([i915#180] / [i915#93] / [i915#95]) +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-skl:          [PASS][15] -> [FAIL][16] ([i915#1188])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [PASS][19] -> [SKIP][20] ([fdo#109642] / [fdo#111068])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-iclb3/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         [PASS][21] -> [SKIP][22] ([fdo#109441]) +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html

  
#### Possible fixes ####

  * igt@kms_cursor_legacy@pipe-c-torture-move:
    - shard-hsw:          [DMESG-WARN][23] ([i915#128]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-hsw1/igt@kms_cursor_legacy@pipe-c-torture-move.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-hsw7/igt@kms_cursor_legacy@pipe-c-torture-move.html

  * {igt@kms_flip@flip-vs-suspend@b-hdmi-a1}:
    - shard-hsw:          [INCOMPLETE][25] ([i915#61]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-hsw4/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-hsw2/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html

  * {igt@kms_flip@flip-vs-suspend@c-dp1}:
    - shard-apl:          [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-apl2/igt@kms_flip@flip-vs-suspend@c-dp1.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-apl3/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * {igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1}:
    - shard-skl:          [FAIL][29] ([i915#34]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-skl5/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-kbl:          [DMESG-WARN][31] ([i915#180] / [i915#93] / [i915#95]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-kbl:          [DMESG-WARN][33] ([i915#180]) -> [PASS][34] +2 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [FAIL][35] ([fdo#108145] / [i915#265]) -> [PASS][36] +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [SKIP][37] ([fdo#109441]) -> [PASS][38] +3 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-iclb1/igt@kms_psr@psr2_cursor_render.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-iclb2/igt@kms_psr@psr2_cursor_render.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc6-psr:
    - shard-tglb:         [SKIP][39] ([i915#468]) -> [FAIL][40] ([i915#454]) +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-tglb8/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_content_protection@srm:
    - shard-apl:          [FAIL][41] ([fdo#110321]) -> [TIMEOUT][42] ([i915#1319])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8438/shard-apl3/igt@kms_content_protection@srm.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/shard-apl2/igt@kms_content_protection@srm.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300
  [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
  [i915#57]: https://gitlab.freedesktop.org/drm/intel/issues/57
  [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
  [i915#70]: https://gitlab.freedesktop.org/drm/intel/issues/70
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8438 -> Patchwork_17595

  CI-20190529: 20190529
  CI_DRM_8438: 9463611ee93f4b254044b8b2467a1e81f942ad01 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5635: e83abfca61d407d12eee4d25bb0e8686337a7791 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17595: a956d64b89965d60f21052c98e2383108c95d17f @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17595/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 01/22] drm/i915/rkl: Add RKL platform info and PCI ids
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 01/22] drm/i915/rkl: Add RKL platform info and PCI ids Matt Roper
@ 2020-05-07 11:18   ` Srivatsa, Anusha
  0 siblings, 0 replies; 53+ messages in thread
From: Srivatsa, Anusha @ 2020-05-07 11:18 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx; +Cc: De Marchi, Lucas



> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt
> Roper
> Sent: Tuesday, May 5, 2020 4:22 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH v2 01/22] drm/i915/rkl: Add RKL platform info and
> PCI ids
> 
> Introduce the basic platform definition, macros, and PCI IDs.
> 
> Bspec: 44501
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Caz Yokoyama <caz.yokoyama@intel.com>
> Cc: Aditya Swarup <aditya.swarup@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Acked-by: Caz Yokoyama <caz.yokoyama@intel.com>

Confirmed the info with the BSpec.
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h          |  8 ++++++++
>  drivers/gpu/drm/i915/i915_pci.c          | 10 ++++++++++
>  drivers/gpu/drm/i915/intel_device_info.c |  1 +
> drivers/gpu/drm/i915/intel_device_info.h |  1 +
>  include/drm/i915_pciids.h                |  9 +++++++++
>  5 files changed, 29 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index 6af69555733e..1ba77283123d
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1406,6 +1406,7 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
>  #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
>  #define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv,
> INTEL_ELKHARTLAKE)
>  #define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv,
> INTEL_TIGERLAKE)
> +#define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv,
> INTEL_ROCKETLAKE)
>  #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>  				    (INTEL_DEVID(dev_priv) & 0xFF00) ==
> 0x0C00)  #define IS_BDW_ULT(dev_priv) \ @@ -1514,6 +1515,13 @@
> IS_SUBPLATFORM(const struct drm_i915_private *i915,  #define
> IS_TGL_REVID(p, since, until) \
>  	(IS_TIGERLAKE(p) && IS_REVID(p, since, until))
> 
> +#define RKL_REVID_A0		0x0
> +#define RKL_REVID_B0		0x1
> +#define RKL_REVID_C0		0x4
> +
> +#define IS_RKL_REVID(p, since, until) \
> +	(IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
> +
>  #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
>  #define IS_GEN9_LP(dev_priv)	(IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
>  #define IS_GEN9_BC(dev_priv)	(IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 1faf9d6ec0a4..5a470bab2214 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -863,6 +863,15 @@ static const struct intel_device_info tgl_info = {
>  		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),  };
> 
> +static const struct intel_device_info rkl_info = {
> +	GEN12_FEATURES,
> +	PLATFORM(INTEL_ROCKETLAKE),
> +	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> +	.require_force_probe = 1,
> +	.engine_mask =
> +		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), };
> +
>  #define GEN12_DGFX_FEATURES \
>  	GEN12_FEATURES, \
>  	.is_dgfx = 1
> @@ -941,6 +950,7 @@ static const struct pci_device_id pciidlist[] = {
>  	INTEL_ICL_11_IDS(&icl_info),
>  	INTEL_EHL_IDS(&ehl_info),
>  	INTEL_TGL_12_IDS(&tgl_info),
> +	INTEL_RKL_IDS(&rkl_info),
>  	{0, 0, 0}
>  };
>  MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 91bb7891c70c..9862c1185059 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -61,6 +61,7 @@ static const char * const platform_names[] = {
>  	PLATFORM_NAME(ICELAKE),
>  	PLATFORM_NAME(ELKHARTLAKE),
>  	PLATFORM_NAME(TIGERLAKE),
> +	PLATFORM_NAME(ROCKETLAKE),
>  };
>  #undef PLATFORM_NAME
> 
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 69c9257c6c6a..a126984cef7f 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -80,6 +80,7 @@ enum intel_platform {
>  	INTEL_ELKHARTLAKE,
>  	/* gen12 */
>  	INTEL_TIGERLAKE,
> +	INTEL_ROCKETLAKE,
>  	INTEL_MAX_PLATFORMS
>  };
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> 662d8351c87a..bc989de2aac2 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -605,4 +605,13 @@
>  	INTEL_VGA_DEVICE(0x9AD9, info), \
>  	INTEL_VGA_DEVICE(0x9AF8, info)
> 
> +/* RKL */
> +#define INTEL_RKL_IDS(info) \
> +	INTEL_VGA_DEVICE(0x4C80, info), \
> +	INTEL_VGA_DEVICE(0x4C8A, info), \
> +	INTEL_VGA_DEVICE(0x4C8B, info), \
> +	INTEL_VGA_DEVICE(0x4C8C, info), \
> +	INTEL_VGA_DEVICE(0x4C90, info), \
> +	INTEL_VGA_DEVICE(0x4C9A, info)
> +
>  #endif /* _I915_PCIIDS_H */
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B
  2020-05-06 16:49     ` Matt Roper
@ 2020-05-07 11:22       ` Srivatsa, Anusha
  0 siblings, 0 replies; 53+ messages in thread
From: Srivatsa, Anusha @ 2020-05-07 11:22 UTC (permalink / raw)
  To: Roper, Matthew D; +Cc: intel-gfx



> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Wednesday, May 6, 2020 10:20 PM
> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC
> for PHY's A and B
> 
> On Wed, May 06, 2020 at 06:49:06AM -0700, Srivatsa, Anusha wrote:
> >
> >
> > > -----Original Message----- From: Intel-gfx
> > > <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt Roper
> > > Sent: Tuesday, May 5, 2020 4:22 AM To:
> > > intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v2
> > > 10/22] drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B
> > >
> > > Since the number of platforms with this restriction are growing,
> > > let's separate out the platform logic into a has_phy_misc()
> > > function.
> > >
> > > Bspec: 50107 Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > --- .../gpu/drm/i915/display/intel_combo_phy.c    | 30
> > > +++++++++++-------- 1 file changed, 17 insertions(+), 13
> > > deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> > > b/drivers/gpu/drm/i915/display/intel_combo_phy.c index
> > > 9ff05ec12115..43d8784f6fa0 100644 ---
> > > a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++
> > > b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -181,11 +181,25
> > > @@ static void cnl_combo_phys_uninit(struct drm_i915_private
> > > *dev_priv) intel_de_write(dev_priv, CHICKEN_MISC_2, val);  }
> > >
> > > +static bool has_phy_misc(struct drm_i915_private *i915, enum phy
> > > phy) { +	/* +	 * Some platforms only expect PHY_MISC to be
> > > programmed for PHY-A and +	 * PHY-B and may not even have
> instances
> > > of the register for the +	 * other combo PHY's.  +	 */ + if
> > > (IS_ELKHARTLAKE(i915) || +	    IS_ROCKETLAKE(i915)) + return phy <
> > > PHY_C;
> > According BSpec 50107, there is an instance of this for combo PHY C as
> > well.
> >
> Yeah, there's technically an instance of the register, but the only field in it that
> our driver programs has a RKL programming note that says "This register field
> need only be programmed for port A and B."

Ok. Thanks for pointing it out.

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> 
> Matt
> 
> > Anusha
> > > +
> > > +	return true;
> > > +}
> > > +
> > >  static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
> > >  				  enum phy phy)
> > >  {
> > >  	/* The PHY C added by EHL has no PHY_MISC register */
> > > -	if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
> > > +	if (!has_phy_misc(dev_priv, phy))
> > >  		return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy))
> &
> > > COMP_INIT;
> > >  	else
> > >  		return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & @@ -
> > > 317,12 +331,7 @@ static void icl_combo_phys_init(struct
> > > drm_i915_private
> > > *dev_priv)
> > >  			continue;
> > >  		}
> > >
> > > -		/*
> > > -		 * Although EHL adds a combo PHY C, there's no PHY_MISC
> > > -		 * register for it and no need to program the
> > > -		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
> > > -		 */
> > > -		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
> > > +		if (!has_phy_misc(dev_priv, phy))
> > >  			goto skip_phy_misc;
> > >
> > >  		/*
> > > @@ -376,12 +385,7 @@ static void icl_combo_phys_uninit(struct
> > > drm_i915_private *dev_priv)
> > >  				 "Combo PHY %c HW state changed
> unexpectedly\n",
> > >  				 phy_name(phy));
> > >
> > > -		/*
> > > -		 * Although EHL adds a combo PHY C, there's no PHY_MISC
> > > -		 * register for it and no need to program the
> > > -		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
> > > -		 */
> > > -		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
> > > +		if (!has_phy_misc(dev_priv, phy))
> > >  			goto skip_phy_misc;
> > >
> > >  		val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
> > > --
> > > 2.24.1
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs Matt Roper
@ 2020-05-07 11:38   ` Srivatsa, Anusha
  2020-05-07 11:59   ` Ville Syrjälä
  1 sibling, 0 replies; 53+ messages in thread
From: Srivatsa, Anusha @ 2020-05-07 11:38 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx; +Cc: De Marchi, Lucas



> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt
> Roper
> Sent: Tuesday, May 5, 2020 4:22 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for
> TC1 and TC2 outputs
> 
> When Rocket Lake is paired with a TGP PCH, the last two outputs utilize the
> TC1 and TC2 hpd pins, even though these are combo outputs.
> 
> Bspec: 49181
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Looks good.

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 6952b0295096..d32bbcd99b8a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6172,8 +6172,12 @@ static bool bxt_digital_port_connected(struct
> intel_encoder *encoder)  static bool intel_combo_phy_connected(struct
> drm_i915_private *dev_priv,
>  				      enum phy phy)
>  {
> -	if (HAS_PCH_MCC(dev_priv) && phy == PHY_C)
> -		return intel_de_read(dev_priv, SDEISR) &
> SDE_TC_HOTPLUG_ICP(PORT_TC1);
> +	if (IS_ROCKETLAKE(dev_priv) && phy >= PHY_C)
> +		return intel_de_read(dev_priv, SDEISR) &
> +			SDE_TC_HOTPLUG_ICP(phy - PHY_C);
> +	else if (HAS_PCH_MCC(dev_priv) && phy == PHY_C)
> +		return intel_de_read(dev_priv, SDEISR) &
> +			SDE_TC_HOTPLUG_ICP(PORT_TC1);
> 
>  	return intel_de_read(dev_priv, SDEISR) &
> SDE_DDI_HOTPLUG_ICP(phy);  }
> --
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 17/22] drm/i915/rkl: Don't try to read out DSI transcoders
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 17/22] drm/i915/rkl: Don't try to read out DSI transcoders Matt Roper
@ 2020-05-07 11:58   ` Ville Syrjälä
  0 siblings, 0 replies; 53+ messages in thread
From: Ville Syrjälä @ 2020-05-07 11:58 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Mon, May 04, 2020 at 03:52:22PM -0700, Matt Roper wrote:
> From: Aditya Swarup <aditya.swarup@intel.com>
> 
> RKL doesn't have DSI outputs, so we shouldn't try to read out the DSI
> transcoder registers.
> 
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 2eeafda82188..e63221b8a9a6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10901,7 +10901,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
>  	intel_wakeref_t wf;
>  	u32 tmp;
>  
> -	if (INTEL_GEN(dev_priv) >= 11)
> +	if (!IS_ROCKETLAKE(dev_priv) && INTEL_GEN(dev_priv) >= 11)
>  		panel_transcoder_mask |=
>  			BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);

I suspect we want
1) fix the deivice info transcoder mask (if not already done)
2) use for_each_transcoder_masked() here

>  
> -- 
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs Matt Roper
  2020-05-07 11:38   ` Srivatsa, Anusha
@ 2020-05-07 11:59   ` Ville Syrjälä
  1 sibling, 0 replies; 53+ messages in thread
From: Ville Syrjälä @ 2020-05-07 11:59 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx, Lucas De Marchi

On Mon, May 04, 2020 at 03:52:17PM -0700, Matt Roper wrote:
> When Rocket Lake is paired with a TGP PCH, the last two outputs utilize
> the TC1 and TC2 hpd pins, even though these are combo outputs.
> 
> Bspec: 49181
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 6952b0295096..d32bbcd99b8a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6172,8 +6172,12 @@ static bool bxt_digital_port_connected(struct intel_encoder *encoder)
>  static bool intel_combo_phy_connected(struct drm_i915_private *dev_priv,
>  				      enum phy phy)
>  {
> -	if (HAS_PCH_MCC(dev_priv) && phy == PHY_C)
> -		return intel_de_read(dev_priv, SDEISR) & SDE_TC_HOTPLUG_ICP(PORT_TC1);
> +	if (IS_ROCKETLAKE(dev_priv) && phy >= PHY_C)
> +		return intel_de_read(dev_priv, SDEISR) &
> +			SDE_TC_HOTPLUG_ICP(phy - PHY_C);
> +	else if (HAS_PCH_MCC(dev_priv) && phy == PHY_C)
> +		return intel_de_read(dev_priv, SDEISR) &
> +			SDE_TC_HOTPLUG_ICP(PORT_TC1);

Most of this mess is going to disappear as soon as I can land
https://patchwork.freedesktop.org/series/72348/

So assuming the hpd[] thing gets correctly populated we no longer
need any hack like these.

>  
>  	return intel_de_read(dev_priv, SDEISR) & SDE_DDI_HOTPLUG_ICP(phy);
>  }
> -- 
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 14/22] drm/i915/rkl: provide port/phy mapping for vbt
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 14/22] drm/i915/rkl: provide port/phy mapping for vbt Matt Roper
@ 2020-05-07 12:04   ` Ville Syrjälä
  2020-05-07 18:05     ` Matt Roper
  0 siblings, 1 reply; 53+ messages in thread
From: Ville Syrjälä @ 2020-05-07 12:04 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx, Lucas De Marchi

On Mon, May 04, 2020 at 03:52:19PM -0700, Matt Roper wrote:
> From: Lucas De Marchi <lucas.demarchi@intel.com>
> 
> RKL uses the DDI A, DDI B, DDI USBC1, DDI USBC2 from the DE point of
> view, so all DDI/pipe/transcoder register use these indexes to refer to
> them. Combo phy and IO functions follow another namespace that we keep
> as "enum phy". The VBT in theory would use the DE point of view, but
> that does not happen in practice.
> 
> Provide a table to convert the child devices to the "correct" port
> numbering we use. Now this is the output we get while reading the VBT:
> 
> DDIA:
> [drm:intel_bios_port_aux_ch [i915]] using AUX A for port A (VBT)
> [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:275:DDI A]
> [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:275:DDI A]
> [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x1 for port A (VBT)
> 
> DDIB:
> [drm:intel_bios_port_aux_ch [i915]] using AUX B for port B (platform default)
> [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:291:DDI B]
> [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x2 for port B (VBT)
> 
> DDI USBC1:
> [drm:intel_bios_port_aux_ch [i915]] using AUX D for port D (VBT)
> [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:295:DDI D]
> [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:295:DDI D]
> [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x3 for port D (VBT)
> 
> DDI USBC2:
> [drm:intel_bios_port_aux_ch [i915]] using AUX E for port E (VBT)
> [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:306:DDI E]
> [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:306:DDI E]
> [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x9 for port E (VBT)
> 
> Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Cc: Aditya Swarup <aditya.swarup@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 72 ++++++++++++++++-------
>  1 file changed, 51 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 839124647202..4f1a72a90b8f 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1619,30 +1619,18 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
>  	return 0;
>  }
>  
> -static enum port dvo_port_to_port(u8 dvo_port)
> +static enum port __dvo_port_to_port(int n_ports, int n_dvo,
> +				    const int port_mapping[][3], u8 dvo_port)
>  {
> -	/*
> -	 * Each DDI port can have more than one value on the "DVO Port" field,
> -	 * so look for all the possible values for each port.
> -	 */
> -	static const int dvo_ports[][3] = {
> -		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1},
> -		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1},
> -		[PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1},
> -		[PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1},
> -		[PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
> -		[PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1},
> -		[PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1},
> -	};
>  	enum port port;
>  	int i;
>  
> -	for (port = PORT_A; port < ARRAY_SIZE(dvo_ports); port++) {
> -		for (i = 0; i < ARRAY_SIZE(dvo_ports[port]); i++) {
> -			if (dvo_ports[port][i] == -1)
> +	for (port = PORT_A; port < n_ports; port++) {
> +		for (i = 0; i < n_dvo; i++) {
> +			if (port_mapping[port][i] == -1)
>  				break;
>  
> -			if (dvo_port == dvo_ports[port][i])
> +			if (dvo_port == port_mapping[port][i])
>  				return port;
>  		}
>  	}
> @@ -1650,6 +1638,48 @@ static enum port dvo_port_to_port(u8 dvo_port)
>  	return PORT_NONE;
>  }
>  
> +static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
> +				  u8 dvo_port)
> +{
> +	/*
> +	 * Each DDI port can have more than one value on the "DVO Port" field,
> +	 * so look for all the possible values for each port.
> +	 */
> +	static const int port_mapping[][3] = {
> +		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
> +		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
> +		[PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
> +		[PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
> +		[PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, -1 },
> +		[PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },
> +		[PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },
> +	};
> +	/*
> +	 * Bspec lists the ports as A, B, C, D - however internally in our
> +	 * driver we keep them as PORT_A, PORT_B, PORT_D and PORT_E so the
> +	 * registers in Display Engine match the right offsets. Apply the
> +	 * mapping here to translate from VBT to internal convention.
> +	 */
> +	static const int rkl_port_mapping[][3] = {
> +		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
> +		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
> +		[PORT_C] = { -1 },
> +		[PORT_D] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
> +		[PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
> +	};
> +
> +	if (IS_ROCKETLAKE(dev_priv))
> +		return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
> +					  ARRAY_SIZE(rkl_port_mapping[0]),
> +					  rkl_port_mapping,
> +					  dvo_port);
> +	else
> +		return __dvo_port_to_port(ARRAY_SIZE(port_mapping),
> +					  ARRAY_SIZE(port_mapping[0]),
> +					  port_mapping,
> +					  dvo_port);
> +}

What a horror show. To me it looks like we should just use the
phy here. Or would that break something else?

> +
>  static void parse_ddi_port(struct drm_i915_private *dev_priv,
>  			   struct display_device_data *devdata,
>  			   u8 bdb_version)
> @@ -1659,7 +1689,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv,
>  	bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
>  	enum port port;
>  
> -	port = dvo_port_to_port(child->dvo_port);
> +	port = dvo_port_to_port(dev_priv, child->dvo_port);
>  	if (port == PORT_NONE)
>  		return;
>  
> @@ -2603,10 +2633,10 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
>  		aux_ch = AUX_CH_B;
>  		break;
>  	case DP_AUX_C:
> -		aux_ch = AUX_CH_C;
> +		aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C;
>  		break;
>  	case DP_AUX_D:
> -		aux_ch = AUX_CH_D;
> +		aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D;
>  		break;
>  	case DP_AUX_E:
>  		aux_ch = AUX_CH_E;
> -- 
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 07/22] drm/i915/rkl: Limit number of universal planes to 5
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 07/22] drm/i915/rkl: Limit number of universal planes to 5 Matt Roper
@ 2020-05-07 12:10   ` Ville Syrjälä
  0 siblings, 0 replies; 53+ messages in thread
From: Ville Syrjälä @ 2020-05-07 12:10 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Mon, May 04, 2020 at 03:52:12PM -0700, Matt Roper wrote:
> RKL only has five universal planes, plus a cursor.  Since the
> bottom-most universal plane is considered the primary plane, set the
> number of sprites available on this platform to 4.
> 
> In general, the plane capabilities of the remaining planes stay the same
> as TGL.  However the NV12 Y-plane support moves down to the new top two
> planes and now only the bottom three planes can be used for NV12 UV.
> 
> Bspec: 49181
> Bspec: 49251
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  6 +++++-
>  drivers/gpu/drm/i915/display/intel_sprite.c  | 17 ++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_sprite.h  | 11 ++---------
>  drivers/gpu/drm/i915/i915_irq.c              |  4 +++-
>  drivers/gpu/drm/i915/i915_reg.h              |  5 +++++
>  drivers/gpu/drm/i915/intel_device_info.c     |  5 ++++-
>  6 files changed, 35 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index fd6d63b03489..7d7a5b66f2cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12500,7 +12500,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
>  			continue;
>  
>  		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
> -			if (!icl_is_nv12_y_plane(linked->id))
> +			if (!icl_is_nv12_y_plane(dev_priv, linked->id))
>  				continue;
>  
>  			if (crtc_state->active_planes & BIT(linked->id))
> @@ -12546,6 +12546,10 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
>  				plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
>  			else if (linked->id == PLANE_SPRITE4)
>  				plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
> +			else if (linked->id == PLANE_SPRITE3)
> +				plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
> +			else if (linked->id == PLANE_SPRITE2)
> +				plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
>  			else
>  				MISSING_CASE(linked->id);
>  		}
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 0000ec7055f7..571c36f929bd 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -333,6 +333,21 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
>  	return 0;
>  }
>  
> +static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
> +{
> +	if (IS_ROCKETLAKE(i915))
> +		return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
> +	else

I'd probably move the gen11+ check here too.

Starting to wonder if we shouldn't just stuff a few plane
masks into the device info (and replace all num_sprites
stuff with those).

Anyways, looks reasonable:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Also wondering what happened to some of the stuff I did to these
functions... Oh right, it was all part of some colorkey stuff
which by now needs to rebased.

> +		return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
> +}
> +
> +bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
> +			 enum plane_id plane_id)
> +{
> +	return INTEL_GEN(dev_priv) >= 11 &&
> +		icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id);
> +}
> +
>  bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id)
>  {
>  	return INTEL_GEN(dev_priv) >= 11 &&
> @@ -3003,7 +3018,7 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
>  	if (icl_is_hdr_plane(dev_priv, plane_id)) {
>  		*num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
>  		return icl_hdr_plane_formats;
> -	} else if (icl_is_nv12_y_plane(plane_id)) {
> +	} else if (icl_is_nv12_y_plane(dev_priv, plane_id)) {
>  		*num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats);
>  		return icl_sdr_y_plane_formats;
>  	} else {
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.h b/drivers/gpu/drm/i915/display/intel_sprite.h
> index 5eeaa92420d1..cd2104ba1ca1 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.h
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.h
> @@ -32,21 +32,14 @@ struct intel_plane *
>  skl_universal_plane_create(struct drm_i915_private *dev_priv,
>  			   enum pipe pipe, enum plane_id plane_id);
>  
> -static inline bool icl_is_nv12_y_plane(enum plane_id id)
> -{
> -	/* Don't need to do a gen check, these planes are only available on gen11 */
> -	if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
> -		return true;
> -
> -	return false;
> -}
> -
>  static inline u8 icl_hdr_plane_mask(void)
>  {
>  	return BIT(PLANE_PRIMARY) |
>  		BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
>  }
>  
> +bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
> +			 enum plane_id plane_id);
>  bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
>  
>  int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index bd722d0650c8..622986759ec6 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2221,7 +2221,9 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
>  
>  static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
>  {
> -	if (INTEL_GEN(dev_priv) >= 11)
> +	if (IS_ROCKETLAKE(dev_priv))
> +		return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
> +	else if (INTEL_GEN(dev_priv) >= 11)
>  		return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
>  	else if (INTEL_GEN(dev_priv) >= 9)
>  		return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fd9f2904d93c..59c1d527cf13 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6907,6 +6907,8 @@ enum {
>  #define _PLANE_CUS_CTL_1_A			0x701c8
>  #define _PLANE_CUS_CTL_2_A			0x702c8
>  #define  PLANE_CUS_ENABLE			(1 << 31)
> +#define  PLANE_CUS_PLANE_4_RKL			(0 << 30)
> +#define  PLANE_CUS_PLANE_5_RKL			(1 << 30)
>  #define  PLANE_CUS_PLANE_6			(0 << 30)
>  #define  PLANE_CUS_PLANE_7			(1 << 30)
>  #define  PLANE_CUS_HPHASE_SIGN_NEGATIVE		(1 << 19)
> @@ -7573,6 +7575,9 @@ enum {
>  	 GEN11_PIPE_PLANE7_FAULT | \
>  	 GEN11_PIPE_PLANE6_FAULT | \
>  	 GEN11_PIPE_PLANE5_FAULT)
> +#define RKL_DE_PIPE_IRQ_FAULT_ERRORS \
> +	(GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
> +	 GEN11_PIPE_PLANE5_FAULT)
>  
>  #define GEN8_DE_PORT_ISR _MMIO(0x44440)
>  #define GEN8_DE_PORT_IMR _MMIO(0x44444)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 9862c1185059..a5a92c2728db 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -934,7 +934,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  
>  	BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
>  
> -	if (INTEL_GEN(dev_priv) >= 11)
> +	if (IS_ROCKETLAKE(dev_priv))
> +		for_each_pipe(dev_priv, pipe)
> +			runtime->num_sprites[pipe] = 4;
> +	else if (INTEL_GEN(dev_priv) >= 11)
>  		for_each_pipe(dev_priv, pipe)
>  			runtime->num_sprites[pipe] = 6;
>  	else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
> -- 
> 2.24.1

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 06/22] drm/i915/rkl: Update memory bandwidth parameters
  2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 06/22] drm/i915/rkl: Update memory bandwidth parameters Matt Roper
@ 2020-05-07 12:24   ` Ville Syrjälä
  0 siblings, 0 replies; 53+ messages in thread
From: Ville Syrjälä @ 2020-05-07 12:24 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Mon, May 04, 2020 at 03:52:11PM -0700, Matt Roper wrote:
> The RKL platform has different memory characteristics from past
> platforms.  Update the values used by our memory bandwidth calculations
> accordingly.
> 
> Bspec: 53998
> Cc: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 6e7cc3a4f1aa..d435cc6019e4 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -176,6 +176,12 @@ static const struct intel_sa_info tgl_sa_info = {
>  	.displayrtids = 256,
>  };
>  
> +static const struct intel_sa_info rkl_sa_info = {
> +	.deburst = 16,
> +	.deprogbwlimit = 20, /* GB/s */
> +	.displayrtids = 128,
> +};

Numbers appear to match the spec.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +
>  static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
>  {
>  	struct intel_qgv_info qi = {};
> @@ -271,7 +277,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
>  	if (!HAS_DISPLAY(dev_priv))
>  		return;
>  
> -	if (IS_GEN(dev_priv, 12))
> +	if (IS_ROCKETLAKE(dev_priv))
> +		icl_get_bw_info(dev_priv, &rkl_sa_info);
> +	else if (IS_GEN(dev_priv, 12))
>  		icl_get_bw_info(dev_priv, &tgl_sa_info);
>  	else if (IS_GEN(dev_priv, 11))
>  		icl_get_bw_info(dev_priv, &icl_sa_info);
> -- 
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 14/22] drm/i915/rkl: provide port/phy mapping for vbt
  2020-05-07 12:04   ` Ville Syrjälä
@ 2020-05-07 18:05     ` Matt Roper
  2020-05-08  9:44       ` Ville Syrjälä
  0 siblings, 1 reply; 53+ messages in thread
From: Matt Roper @ 2020-05-07 18:05 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx, Lucas De Marchi

On Thu, May 07, 2020 at 03:04:30PM +0300, Ville Syrjälä wrote:
> On Mon, May 04, 2020 at 03:52:19PM -0700, Matt Roper wrote:
> > From: Lucas De Marchi <lucas.demarchi@intel.com>
> > 
> > RKL uses the DDI A, DDI B, DDI USBC1, DDI USBC2 from the DE point of
> > view, so all DDI/pipe/transcoder register use these indexes to refer to
> > them. Combo phy and IO functions follow another namespace that we keep
> > as "enum phy". The VBT in theory would use the DE point of view, but
> > that does not happen in practice.
> > 
> > Provide a table to convert the child devices to the "correct" port
> > numbering we use. Now this is the output we get while reading the VBT:
> > 
> > DDIA:
> > [drm:intel_bios_port_aux_ch [i915]] using AUX A for port A (VBT)
> > [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:275:DDI A]
> > [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:275:DDI A]
> > [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x1 for port A (VBT)
> > 
> > DDIB:
> > [drm:intel_bios_port_aux_ch [i915]] using AUX B for port B (platform default)
> > [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:291:DDI B]
> > [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x2 for port B (VBT)
> > 
> > DDI USBC1:
> > [drm:intel_bios_port_aux_ch [i915]] using AUX D for port D (VBT)
> > [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:295:DDI D]
> > [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:295:DDI D]
> > [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x3 for port D (VBT)
> > 
> > DDI USBC2:
> > [drm:intel_bios_port_aux_ch [i915]] using AUX E for port E (VBT)
> > [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:306:DDI E]
> > [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:306:DDI E]
> > [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x9 for port E (VBT)
> > 
> > Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
> > Cc: Aditya Swarup <aditya.swarup@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_bios.c | 72 ++++++++++++++++-------
> >  1 file changed, 51 insertions(+), 21 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> > index 839124647202..4f1a72a90b8f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -1619,30 +1619,18 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
> >  	return 0;
> >  }
> >  
> > -static enum port dvo_port_to_port(u8 dvo_port)
> > +static enum port __dvo_port_to_port(int n_ports, int n_dvo,
> > +				    const int port_mapping[][3], u8 dvo_port)
> >  {
> > -	/*
> > -	 * Each DDI port can have more than one value on the "DVO Port" field,
> > -	 * so look for all the possible values for each port.
> > -	 */
> > -	static const int dvo_ports[][3] = {
> > -		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1},
> > -		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1},
> > -		[PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1},
> > -		[PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1},
> > -		[PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
> > -		[PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1},
> > -		[PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1},
> > -	};
> >  	enum port port;
> >  	int i;
> >  
> > -	for (port = PORT_A; port < ARRAY_SIZE(dvo_ports); port++) {
> > -		for (i = 0; i < ARRAY_SIZE(dvo_ports[port]); i++) {
> > -			if (dvo_ports[port][i] == -1)
> > +	for (port = PORT_A; port < n_ports; port++) {
> > +		for (i = 0; i < n_dvo; i++) {
> > +			if (port_mapping[port][i] == -1)
> >  				break;
> >  
> > -			if (dvo_port == dvo_ports[port][i])
> > +			if (dvo_port == port_mapping[port][i])
> >  				return port;
> >  		}
> >  	}
> > @@ -1650,6 +1638,48 @@ static enum port dvo_port_to_port(u8 dvo_port)
> >  	return PORT_NONE;
> >  }
> >  
> > +static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
> > +				  u8 dvo_port)
> > +{
> > +	/*
> > +	 * Each DDI port can have more than one value on the "DVO Port" field,
> > +	 * so look for all the possible values for each port.
> > +	 */
> > +	static const int port_mapping[][3] = {
> > +		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
> > +		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
> > +		[PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
> > +		[PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
> > +		[PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, -1 },
> > +		[PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },
> > +		[PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },
> > +	};
> > +	/*
> > +	 * Bspec lists the ports as A, B, C, D - however internally in our
> > +	 * driver we keep them as PORT_A, PORT_B, PORT_D and PORT_E so the
> > +	 * registers in Display Engine match the right offsets. Apply the
> > +	 * mapping here to translate from VBT to internal convention.
> > +	 */
> > +	static const int rkl_port_mapping[][3] = {
> > +		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
> > +		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
> > +		[PORT_C] = { -1 },
> > +		[PORT_D] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
> > +		[PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
> > +	};
> > +
> > +	if (IS_ROCKETLAKE(dev_priv))
> > +		return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
> > +					  ARRAY_SIZE(rkl_port_mapping[0]),
> > +					  rkl_port_mapping,
> > +					  dvo_port);
> > +	else
> > +		return __dvo_port_to_port(ARRAY_SIZE(port_mapping),
> > +					  ARRAY_SIZE(port_mapping[0]),
> > +					  port_mapping,
> > +					  dvo_port);
> > +}
> 
> What a horror show. To me it looks like we should just use the
> phy here. Or would that break something else?

That would break EHL since its VBT uses the DDI ("D") rather than the
PHY.

So today we have two platforms (EHL and RKL) that have DDI != PHY, but
the VBT handling of them isn't consistent.  :-(


Matt

> 
> > +
> >  static void parse_ddi_port(struct drm_i915_private *dev_priv,
> >  			   struct display_device_data *devdata,
> >  			   u8 bdb_version)
> > @@ -1659,7 +1689,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv,
> >  	bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
> >  	enum port port;
> >  
> > -	port = dvo_port_to_port(child->dvo_port);
> > +	port = dvo_port_to_port(dev_priv, child->dvo_port);
> >  	if (port == PORT_NONE)
> >  		return;
> >  
> > @@ -2603,10 +2633,10 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
> >  		aux_ch = AUX_CH_B;
> >  		break;
> >  	case DP_AUX_C:
> > -		aux_ch = AUX_CH_C;
> > +		aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C;
> >  		break;
> >  	case DP_AUX_D:
> > -		aux_ch = AUX_CH_D;
> > +		aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D;
> >  		break;
> >  	case DP_AUX_E:
> >  		aux_ch = AUX_CH_E;
> > -- 
> > 2.24.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 14/22] drm/i915/rkl: provide port/phy mapping for vbt
  2020-05-07 18:05     ` Matt Roper
@ 2020-05-08  9:44       ` Ville Syrjälä
  0 siblings, 0 replies; 53+ messages in thread
From: Ville Syrjälä @ 2020-05-08  9:44 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx, Lucas De Marchi

On Thu, May 07, 2020 at 11:05:33AM -0700, Matt Roper wrote:
> On Thu, May 07, 2020 at 03:04:30PM +0300, Ville Syrjälä wrote:
> > On Mon, May 04, 2020 at 03:52:19PM -0700, Matt Roper wrote:
> > > From: Lucas De Marchi <lucas.demarchi@intel.com>
> > > 
> > > RKL uses the DDI A, DDI B, DDI USBC1, DDI USBC2 from the DE point of
> > > view, so all DDI/pipe/transcoder register use these indexes to refer to
> > > them. Combo phy and IO functions follow another namespace that we keep
> > > as "enum phy". The VBT in theory would use the DE point of view, but
> > > that does not happen in practice.
> > > 
> > > Provide a table to convert the child devices to the "correct" port
> > > numbering we use. Now this is the output we get while reading the VBT:
> > > 
> > > DDIA:
> > > [drm:intel_bios_port_aux_ch [i915]] using AUX A for port A (VBT)
> > > [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:275:DDI A]
> > > [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:275:DDI A]
> > > [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x1 for port A (VBT)
> > > 
> > > DDIB:
> > > [drm:intel_bios_port_aux_ch [i915]] using AUX B for port B (platform default)
> > > [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:291:DDI B]
> > > [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x2 for port B (VBT)
> > > 
> > > DDI USBC1:
> > > [drm:intel_bios_port_aux_ch [i915]] using AUX D for port D (VBT)
> > > [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:295:DDI D]
> > > [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:295:DDI D]
> > > [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x3 for port D (VBT)
> > > 
> > > DDI USBC2:
> > > [drm:intel_bios_port_aux_ch [i915]] using AUX E for port E (VBT)
> > > [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:306:DDI E]
> > > [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:306:DDI E]
> > > [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x9 for port E (VBT)
> > > 
> > > Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
> > > Cc: Aditya Swarup <aditya.swarup@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_bios.c | 72 ++++++++++++++++-------
> > >  1 file changed, 51 insertions(+), 21 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> > > index 839124647202..4f1a72a90b8f 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > > @@ -1619,30 +1619,18 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
> > >  	return 0;
> > >  }
> > >  
> > > -static enum port dvo_port_to_port(u8 dvo_port)
> > > +static enum port __dvo_port_to_port(int n_ports, int n_dvo,
> > > +				    const int port_mapping[][3], u8 dvo_port)
> > >  {
> > > -	/*
> > > -	 * Each DDI port can have more than one value on the "DVO Port" field,
> > > -	 * so look for all the possible values for each port.
> > > -	 */
> > > -	static const int dvo_ports[][3] = {
> > > -		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1},
> > > -		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1},
> > > -		[PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1},
> > > -		[PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1},
> > > -		[PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
> > > -		[PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1},
> > > -		[PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1},
> > > -	};
> > >  	enum port port;
> > >  	int i;
> > >  
> > > -	for (port = PORT_A; port < ARRAY_SIZE(dvo_ports); port++) {
> > > -		for (i = 0; i < ARRAY_SIZE(dvo_ports[port]); i++) {
> > > -			if (dvo_ports[port][i] == -1)
> > > +	for (port = PORT_A; port < n_ports; port++) {
> > > +		for (i = 0; i < n_dvo; i++) {
> > > +			if (port_mapping[port][i] == -1)
> > >  				break;
> > >  
> > > -			if (dvo_port == dvo_ports[port][i])
> > > +			if (dvo_port == port_mapping[port][i])
> > >  				return port;
> > >  		}
> > >  	}
> > > @@ -1650,6 +1638,48 @@ static enum port dvo_port_to_port(u8 dvo_port)
> > >  	return PORT_NONE;
> > >  }
> > >  
> > > +static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
> > > +				  u8 dvo_port)
> > > +{
> > > +	/*
> > > +	 * Each DDI port can have more than one value on the "DVO Port" field,
> > > +	 * so look for all the possible values for each port.
> > > +	 */
> > > +	static const int port_mapping[][3] = {
> > > +		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
> > > +		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
> > > +		[PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
> > > +		[PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
> > > +		[PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, -1 },
> > > +		[PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },
> > > +		[PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },
> > > +	};
> > > +	/*
> > > +	 * Bspec lists the ports as A, B, C, D - however internally in our
> > > +	 * driver we keep them as PORT_A, PORT_B, PORT_D and PORT_E so the
> > > +	 * registers in Display Engine match the right offsets. Apply the
> > > +	 * mapping here to translate from VBT to internal convention.
> > > +	 */
> > > +	static const int rkl_port_mapping[][3] = {
> > > +		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
> > > +		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
> > > +		[PORT_C] = { -1 },
> > > +		[PORT_D] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
> > > +		[PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
> > > +	};
> > > +
> > > +	if (IS_ROCKETLAKE(dev_priv))
> > > +		return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
> > > +					  ARRAY_SIZE(rkl_port_mapping[0]),
> > > +					  rkl_port_mapping,
> > > +					  dvo_port);
> > > +	else
> > > +		return __dvo_port_to_port(ARRAY_SIZE(port_mapping),
> > > +					  ARRAY_SIZE(port_mapping[0]),
> > > +					  port_mapping,
> > > +					  dvo_port);
> > > +}
> > 
> > What a horror show. To me it looks like we should just use the
> > phy here. Or would that break something else?
> 
> That would break EHL since its VBT uses the DDI ("D") rather than the
> PHY.
> 
> So today we have two platforms (EHL and RKL) that have DDI != PHY, but
> the VBT handling of them isn't consistent.  :-(

Sigh.

I wonder if we should just add encoder->vbt_port or something along
those lines. Unfortunately even that still needs some mapping tricks
due to the HDMI vs. DP dvo_port difference.

In the mantime I guess this is hidden well wnough that it won't bother
too many people until the next platform that needs these hacks comes
along.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> 
> 
> Matt
> 
> > 
> > > +
> > >  static void parse_ddi_port(struct drm_i915_private *dev_priv,
> > >  			   struct display_device_data *devdata,
> > >  			   u8 bdb_version)
> > > @@ -1659,7 +1689,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv,
> > >  	bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
> > >  	enum port port;
> > >  
> > > -	port = dvo_port_to_port(child->dvo_port);
> > > +	port = dvo_port_to_port(dev_priv, child->dvo_port);
> > >  	if (port == PORT_NONE)
> > >  		return;
> > >  
> > > @@ -2603,10 +2633,10 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
> > >  		aux_ch = AUX_CH_B;
> > >  		break;
> > >  	case DP_AUX_C:
> > > -		aux_ch = AUX_CH_C;
> > > +		aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C;
> > >  		break;
> > >  	case DP_AUX_D:
> > > -		aux_ch = AUX_CH_D;
> > > +		aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D;
> > >  		break;
> > >  	case DP_AUX_E:
> > >  		aux_ch = AUX_CH_E;
> > > -- 
> > > 2.24.1
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Ville Syrjälä
> > Intel
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support
  2020-05-06 11:51   ` Srivatsa, Anusha
@ 2020-05-19 23:57     ` Lucas De Marchi
  2020-05-20  9:30       ` Borislav Petkov
  0 siblings, 1 reply; 53+ messages in thread
From: Lucas De Marchi @ 2020-05-19 23:57 UTC (permalink / raw)
  To: Srivatsa, Anusha
  Cc: intel-gfx, x86, De Marchi, Lucas, Ingo Molnar, Thomas Gleixner,
	Borislav Petkov

Cc'ing x86@kernel.org and maintainers

On Wed, May 6, 2020 at 4:52 AM Srivatsa, Anusha
<anusha.srivatsa@intel.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt
> > Roper
> > Sent: Tuesday, May 5, 2020 4:22 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> > Subject: [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support
> >
> > RKL re-uses the same stolen memory registers as TGL and ICL.
> >
> > Bspec: 52055
> > Bspec: 49589
> > Bspec: 49636
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>
> Confirmed with Spec.
> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> > ---
> >  arch/x86/kernel/early-quirks.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> > index 2f9ec14be3b1..a4b5af03dcc1 100644
> > --- a/arch/x86/kernel/early-quirks.c
> > +++ b/arch/x86/kernel/early-quirks.c
> > @@ -550,6 +550,7 @@ static const struct pci_device_id intel_early_ids[]
> > __initconst = {
> >       INTEL_ICL_11_IDS(&gen11_early_ops),
> >       INTEL_EHL_IDS(&gen11_early_ops),
> >       INTEL_TGL_12_IDS(&gen11_early_ops),
> > +     INTEL_RKL_IDS(&gen11_early_ops),

Trying to apply to drm-intel-next-queued checkpatch rightfully complain:

35aad4f58736 (HEAD -> drm-intel-next-queued) x86/gpu: add RKL stolen
memory support
The following files are outside of i915 maintenance scope:
arch/x86/kernel/early-quirks.c

Can we get an ack?  Going forward, for simple changes like this, do
you prefer to still ack on it
or should we just apply to our tree?

thanks
Lucas De Marchi

> >  };
> >
> >  struct resource intel_graphics_stolen_res __ro_after_init =
> > DEFINE_RES_MEM(0, 0);
> > --
> > 2.24.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support
  2020-05-19 23:57     ` Lucas De Marchi
@ 2020-05-20  9:30       ` Borislav Petkov
  2020-05-20 17:49         ` Lucas De Marchi
  0 siblings, 1 reply; 53+ messages in thread
From: Borislav Petkov @ 2020-05-20  9:30 UTC (permalink / raw)
  To: Lucas De Marchi
  Cc: intel-gfx, x86, De Marchi, Lucas, Ingo Molnar, Thomas Gleixner,
	Borislav Petkov

On Tue, May 19, 2020 at 04:57:27PM -0700, Lucas De Marchi wrote:
> The following files are outside of i915 maintenance scope:
> arch/x86/kernel/early-quirks.c
> 
> Can we get an ack?

Acked-by: Borislav Petkov <bp@suse.de>

> Going forward, for simple changes like this, do you prefer to still
> ack on it or should we just apply to our tree?

Well, we are very quickly to give an ACK for trivial stuff like that
if we get CCed upfront on the patch. It keeps us aware of what's being
changed outside of tip.

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

* Re: [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support
  2020-05-20  9:30       ` Borislav Petkov
@ 2020-05-20 17:49         ` Lucas De Marchi
  0 siblings, 0 replies; 53+ messages in thread
From: Lucas De Marchi @ 2020-05-20 17:49 UTC (permalink / raw)
  To: Borislav Petkov
  Cc: intel-gfx, x86, Ingo Molnar, Thomas Gleixner, Borislav Petkov

On Wed, May 20, 2020 at 11:30:25AM +0200, Borislav Petkov wrote:
>On Tue, May 19, 2020 at 04:57:27PM -0700, Lucas De Marchi wrote:
>> The following files are outside of i915 maintenance scope:
>> arch/x86/kernel/early-quirks.c
>>
>> Can we get an ack?
>
>Acked-by: Borislav Petkov <bp@suse.de>
>
>> Going forward, for simple changes like this, do you prefer to still
>> ack on it or should we just apply to our tree?
>
>Well, we are very quickly to give an ACK for trivial stuff like that
>if we get CCed upfront on the patch. It keeps us aware of what's being
>changed outside of tip.

that works, thanks for quick reply and ack.

Lucas De Marchi

>
>Thx.
>
>-- 
>Regards/Gruss,
>    Boris.
>
>https://people.kernel.org/tglx/notes-about-netiquette
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 53+ messages in thread

end of thread, back to index

Thread overview: 53+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 01/22] drm/i915/rkl: Add RKL platform info and PCI ids Matt Roper
2020-05-07 11:18   ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support Matt Roper
2020-05-06 11:51   ` Srivatsa, Anusha
2020-05-19 23:57     ` Lucas De Marchi
2020-05-20  9:30       ` Borislav Petkov
2020-05-20 17:49         ` Lucas De Marchi
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 03/22] drm/i915/rkl: Re-use TGL GuC/HuC firmware Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 04/22] drm/i915/rkl: Load DMC firmware for Rocket Lake Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 05/22] drm/i915/rkl: Add PCH support Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 06/22] drm/i915/rkl: Update memory bandwidth parameters Matt Roper
2020-05-07 12:24   ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 07/22] drm/i915/rkl: Limit number of universal planes to 5 Matt Roper
2020-05-07 12:10   ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 08/22] drm/i915/rkl: Add power well support Matt Roper
2020-05-05  4:50   ` Anshuman Gupta
2020-05-05 14:39     ` Matt Roper
2020-05-05 16:09       ` Imre Deak
2020-05-06 12:13         ` Anshuman Gupta
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 09/22] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B Matt Roper
2020-05-06 13:49   ` Srivatsa, Anusha
2020-05-06 16:49     ` Matt Roper
2020-05-07 11:22       ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 11/22] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs Matt Roper
2020-05-07 11:38   ` Srivatsa, Anusha
2020-05-07 11:59   ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 13/22] drm/i915/rkl: Setup ports/phys Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 14/22] drm/i915/rkl: provide port/phy mapping for vbt Matt Roper
2020-05-07 12:04   ` Ville Syrjälä
2020-05-07 18:05     ` Matt Roper
2020-05-08  9:44       ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 15/22] drm/i915/rkl: Add DDC pin mapping Matt Roper
2020-05-06  9:19   ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 16/22] drm/i915/rkl: Don't try to access transcoder D Matt Roper
2020-05-06 20:34   ` Matt Roper
2020-05-06 21:21   ` [Intel-gfx] [PATCH v3 " Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 17/22] drm/i915/rkl: Don't try to read out DSI transcoders Matt Roper
2020-05-07 11:58   ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 18/22] drm/i915/rkl: Handle comp master/slave relationships for PHYs Matt Roper
2020-05-06  9:20   ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 19/22] drm/i915/rkl: Add DPLL4 support Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 20/22] drm/i915/rkl: Handle HTI Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 21/22] drm/i915/rkl: Disable PSR2 Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 22/22] drm/i915/rkl: Add initial workarounds Matt Roper
2020-05-04 23:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Rocket Lake (rev4) Patchwork
2020-05-04 23:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-05 13:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-05-06 22:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Rocket Lake (rev5) Patchwork
2020-05-06 22:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-07  2:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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