From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 4/4] drm/i915/display: Enable HOBL regardless the VBT value
Date: Thu, 28 May 2020 13:03:56 -0700 [thread overview]
Message-ID: <20200528200356.36756-4-jose.souza@intel.com> (raw)
In-Reply-To: <20200528200356.36756-1-jose.souza@intel.com>
HOBL worked in my TGL RVP even without the necessary HW support, also
it worked in more than half of the TGL machines in CI so it is worthy
to enable it by default.
Even if link training fails with this new vswing table it will only
cause one additional link training, that is worthy the try to get the
additional power-savings.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index db078780542f..86de1187d363 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -108,7 +108,7 @@ intel_dp_reset_link_train(struct intel_dp *intel_dp, u8 dp_train_pat)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.hobl)
+ if (HAS_HOBL(dev_priv) && intel_dp_is_edp(intel_dp))
intel_dp->try_hobl = true;
memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
--
2.26.2
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next prev parent reply other threads:[~2020-05-28 20:03 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-28 20:03 [Intel-gfx] [PATCH 1/4] drm/i915/display/hsw+: Do not program the same vswing entry twice José Roberto de Souza
2020-05-28 20:03 ` [Intel-gfx] [PATCH 2/4] drm/i915/bios: Parse HOBL parameter José Roberto de Souza
2020-05-28 20:03 ` [Intel-gfx] [PATCH 3/4] drm/i915/display: Implement HOBL José Roberto de Souza
2020-05-29 7:00 ` Ville Syrjälä
2020-05-29 17:17 ` Souza, Jose
2020-05-28 20:03 ` José Roberto de Souza [this message]
2020-05-28 20:12 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915/display/hsw+: Do not program the same vswing entry twice Patchwork
2020-05-28 20:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-28 22:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-05-29 6:51 ` [Intel-gfx] [PATCH 1/4] " Ville Syrjälä
2020-05-29 20:52 ` Souza, Jose
2020-06-03 12:42 ` Ville Syrjälä
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