From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Subject: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Set timeslicing priority from queue
Date: Mon, 1 Jun 2020 21:35:49 +0100 [thread overview]
Message-ID: <20200601203550.19192-2-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <20200601203550.19192-1-chris@chris-wilson.co.uk>
If we only submit the first port, leaving the second empty yet have
ready requests pending in the queue, use that to set the timeslicing
priority (i.e. the priority at which we will decided to enabling
timeslicing and evict the currently active context if the queue is of
equal priority after its quantum expired).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 6fc0966b75ff..7a3c55e3ad9d 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1962,7 +1962,7 @@ static int
switch_prio(struct intel_engine_cs *engine, const struct i915_request *rq)
{
if (list_is_last(&rq->sched.link, &engine->active.requests))
- return INT_MIN;
+ return engine->execlists.queue_priority_hint;
return rq_prio(list_next_entry(rq, sched.link));
}
--
2.20.1
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next prev parent reply other threads:[~2020-06-01 20:36 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-01 20:35 [Intel-gfx] [PATCH 1/3] drm/i915: Trim set_timer_ms() intervals Chris Wilson
2020-06-01 20:35 ` Chris Wilson [this message]
2020-06-01 20:35 ` [Intel-gfx] [PATCH 3/3] drm/i915/gt: Always check to enable timeslicing if not submitting Chris Wilson
2020-06-01 21:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Trim set_timer_ms() intervals Patchwork
2020-06-02 4:48 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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