Intel-GFX Archive on lore.kernel.org
 help / color / Atom feed
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Hans de Goede <hdegoede@redhat.com>
Cc: linux-pwm@vger.kernel.org,
	intel-gfx <intel-gfx@lists.freedesktop.org>,
	"Rafael J . Wysocki" <rjw@rjwysocki.net>,
	linux-acpi@vger.kernel.org, dri-devel@lists.freedesktop.org,
	"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
	"Mika Westerberg" <mika.westerberg@linux.intel.com>,
	"Len Brown" <lenb@kernel.org>
Subject: Re: [Intel-gfx] [PATCH v5 06/16] pwm: lpss: Use pwm_lpss_apply() when restoring state on resume
Date: Tue, 28 Jul 2020 21:57:03 +0300
Message-ID: <20200728185703.GA3703480@smile.fi.intel.com> (raw)
In-Reply-To: <20200717133753.127282-7-hdegoede@redhat.com>

On Fri, Jul 17, 2020 at 03:37:43PM +0200, Hans de Goede wrote:
> Before this commit a suspend + resume of the LPSS PWM controller
> would result in the controller being reset to its defaults of
> output-freq = clock/256, duty-cycle=100%, until someone changes
> to the output-freq and/or duty-cycle are made.
> 
> This problem has been masked so far because the main consumer
> (the i915 driver) was always making duty-cycle changes on resume.
> With the conversion of the i915 driver to the atomic PWM API the
> driver now only disables/enables the PWM on suspend/resume leaving
> the output-freq and duty as is, triggering this problem.
> 
> The LPSS PWM controller has a mechanism where the ctrl register value
> and the actual base-unit and on-time-div values used are latched. When
> software sets the SW_UPDATE bit then at the end of the current PWM cycle,
> the new values from the ctrl-register will be latched into the actual
> registers, and the SW_UPDATE bit will be cleared.
> 
> The problem is that before this commit our suspend/resume handling
> consisted of simply saving the PWM ctrl register on suspend and
> restoring it on resume, without setting the PWM_SW_UPDATE bit.
> When the controller has lost its state over a suspend/resume and thus
> has been reset to the defaults, just restoring the register is not
> enough. We must also set the SW_UPDATE bit to tell the controller to
> latch the restored values into the actual registers.
> 
> Fixing this problem is not as simple as just or-ing in the value which
> is being restored with SW_UPDATE. If the PWM was enabled before we must
> write the new settings + PWM_SW_UPDATE before setting PWM_ENABLE.
> We must also wait for PWM_SW_UPDATE to become 0 again and depending on the
> model we must do this either before or after the setting of PWM_ENABLE.
> 
> All the necessary logic for doing this is already present inside
> pwm_lpss_apply(), so instead of duplicating this inside the resume
> handler, this commit makes the resume handler use pwm_lpss_apply() to
> restore the settings when necessary. This fixes the output-freq and
> duty-cycle being reset to their defaults on resume.

...

> -static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> -			  const struct pwm_state *state)
> +static int __pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> +			    const struct pwm_state *state, bool from_resume)
>  {
>  	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
>  	int ret = 0;
>  
>  	if (state->enabled) {
>  		if (!pwm_is_enabled(pwm)) {
> -			pm_runtime_get_sync(chip->dev);
> +			if (!from_resume)
> +				pm_runtime_get_sync(chip->dev);
> +
>  			ret = pwm_lpss_prepare_enable(lpwm, pwm, state, true);
> -			if (ret)
> +			if (ret && !from_resume)
>  				pm_runtime_put(chip->dev);
>  		} else {
>  			ret = pwm_lpss_prepare_enable(lpwm, pwm, state, false);
>  		}
>  	} else if (pwm_is_enabled(pwm)) {
>  		pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
> -		pm_runtime_put(chip->dev);
> +
> +		if (!from_resume)
> +			pm_runtime_put(chip->dev);
>  	}
>  
>  	return ret;
>  }

Maybe I'm too picky, but I would go even further and split apply to two versions

static int pwm_lpss_apply_on_resume(struct pwm_chip *chip, struct pwm_device *pwm,
			  const struct pwm_state *state)
>  {
>  	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
>  
>  	if (state->enabled)
>  		return pwm_lpss_prepare_enable(lpwm, pwm, state, !pwm_is_enabled(pwm));
>  	if (pwm_is_enabled(pwm)) {
>  		pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
>  	return 0;
>  }

and another one for !from_resume.

> +static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> +			  const struct pwm_state *state)
> +{
> +	return __pwm_lpss_apply(chip, pwm, state, false);
> +}

...

> +		ret = __pwm_lpss_apply(&lpwm->chip, pwm, &saved_state, true);
> +		if (ret)
> +			dev_err(dev, "Error restoring state on resume\n");

I'm wondering if it's a real error why we do not bail out?
Otherwise dev_warn() ?

-- 
With Best Regards,
Andy Shevchenko


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply index

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-17 13:37 [Intel-gfx] [PATCH v5 00/16] acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API Hans de Goede
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 01/16] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase Hans de Goede
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 02/16] ACPI / LPSS: Save Cherry Trail PWM ctx registers only once (at activation) Hans de Goede
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 03/16] pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() Hans de Goede
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 04/16] pwm: lpss: Add range limit check for the base_unit register value Hans de Goede
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 05/16] pwm: lpss: Add pwm_lpss_prepare_enable() helper Hans de Goede
2020-07-28 18:45   ` Andy Shevchenko
2020-07-28 19:49     ` Hans de Goede
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 06/16] pwm: lpss: Use pwm_lpss_apply() when restoring state on resume Hans de Goede
2020-07-28 18:57   ` Andy Shevchenko [this message]
2020-07-28 19:55     ` Hans de Goede
2020-07-29  8:12       ` Andy Shevchenko
2020-08-02 20:51         ` Hans de Goede
2020-08-03  8:41           ` Andy Shevchenko
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 07/16] pwm: crc: Fix period / duty_cycle times being off by a factor of 256 Hans de Goede
2020-07-28 19:36   ` Andy Shevchenko
2020-07-28 20:00     ` Hans de Goede
2020-07-29  8:13   ` Andy Shevchenko
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 08/16] pwm: crc: Fix off-by-one error in the clock-divider calculations Hans de Goede
2020-07-29 10:28   ` Andy Shevchenko
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 09/16] pwm: crc: Fix period changes not having any effect Hans de Goede
2020-07-29 10:30   ` Andy Shevchenko
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 10/16] pwm: crc: Enable/disable PWM output on enable/disable Hans de Goede
2020-07-29 10:32   ` Andy Shevchenko
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 11/16] pwm: crc: Implement apply() method to support the new atomic PWM API Hans de Goede
2020-07-29 10:51   ` Andy Shevchenko
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 12/16] pwm: crc: Implement get_state() method Hans de Goede
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 13/16] drm/i915: panel: Add get_vbt_pwm_freq() helper Hans de Goede
2020-07-17 13:37 ` [Intel-gfx] [PATCH v5 14/16] drm/i915: panel: Honor the VBT PWM frequency for devs with an external PWM controller Hans de Goede
2020-07-17 13:44 ` [Intel-gfx] [PATCH v5 15/16] drm/i915: panel: Honor the VBT PWM min setting " Hans de Goede
2020-07-17 13:44   ` [Intel-gfx] [PATCH v5 16/16] drm/i915: panel: Use atomic PWM API " Hans de Goede
2020-07-27  7:41 ` [Intel-gfx] [PATCH v5 00/16] acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API Thierry Reding
2020-07-29  8:23   ` Andy Shevchenko
2020-07-29  9:32     ` Hans de Goede
2020-07-30  9:26       ` Thierry Reding
2020-08-01 14:33         ` Hans de Goede
2020-07-29 10:54 ` Andy Shevchenko
2020-08-01 14:38   ` Hans de Goede
2020-08-02 11:25     ` Andy Shevchenko
2020-08-02 19:43       ` Hans de Goede

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200728185703.GA3703480@smile.fi.intel.com \
    --to=andriy.shevchenko@linux.intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=hdegoede@redhat.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=lenb@kernel.org \
    --cc=linux-acpi@vger.kernel.org \
    --cc=linux-pwm@vger.kernel.org \
    --cc=mika.westerberg@linux.intel.com \
    --cc=rjw@rjwysocki.net \
    --cc=u.kleine-koenig@pengutronix.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

Intel-GFX Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/intel-gfx/0 intel-gfx/git/0.git
	git clone --mirror https://lore.kernel.org/intel-gfx/1 intel-gfx/git/1.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 intel-gfx intel-gfx/ https://lore.kernel.org/intel-gfx \
		intel-gfx@lists.freedesktop.org
	public-inbox-index intel-gfx

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.freedesktop.lists.intel-gfx


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git