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From: Imre Deak <imre.deak@intel.com>
To: "Almahallawy, Khaled" <khaled.almahallawy@intel.com>
Cc: "Intel-gfx@lists.freedesktop.org" <Intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/dp: DPTX writes Swing/Pre-emphs(DPCD 0x103-0x106) requested during PHY Layer testing.
Date: Tue, 19 Jan 2021 19:26:44 +0200	[thread overview]
Message-ID: <20210119172644.GC1199567@ideak-desk.fi.intel.com> (raw)
In-Reply-To: <097601d8899c497ba574d9360b4292832a9a9d98.camel@intel.com>

On Tue, Jan 19, 2021 at 09:43:56AM +0200, Almahallawy, Khaled wrote:
> > > [...]
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 79c27f91f42c..5044201ca742 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -5503,6 +5503,9 @@ void intel_dp_process_phy_request(struct
> > > intel_dp *intel_dp)
> > >
> > >  intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
> > >
> > > +drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
> > > +intel_dp->train_set, intel_dp-
> > > >lane_count);
> >
> > This should be rebased on a recent change using instead
> > crtc_state->lane_count.
>
> > That's also not completely correct since it's
> > not guaranteed that the output is enabled (having up-to-date link
> > params in crtc_state) at the time of this test request.

Actually intel_dp_prep_phy_test() makes sure that the output is enabled,
so nvm the above.

> [...]
> > I'm also not sure how intel_dp_autotest_phy_ddi_disable()/enable()
> > affects the vswing/pre-emp setting of the source (DPTX) that got
> > inited when the output was last enabled. The vs/pe programming
> > sequence should be also part of the port enabling. Maybe the HW
> > retains the config across the the above port disable/enable calls
> > and so this happens not to be a problem.
> 
> The requested Vswing/Pre-emph from test scope is coming as part of
> short HPD not as part of Link Training, so I’m not sure how we can use
> these requested vswing/pre-emph values as we do for lane count and Link
> rate as in : intel_dp_adjust_compliance_config

Looks like during PHY testing a regular link training should be
performed (including any LTTPRs on the link), and then for DPRX instead
of the regular cr/eq just set the requested vs/pe levels and the test
pattern. If TEST_LANE_COUNT/RATE changes the link needs to be retrained
again, if only the requested test pattern or vs/pe levels change then
changing only these w/o retraining the link should be ok.

> However the rationale behind
> intel_dp_autotest_phy_ddi_disable()/enable() is based on Specs:50482
> which said TRANS_CONF and TRANS_DDI_FUNC_CTL must be disabled prior to
> enabling the test pattern

Ok, makes sense, so this indeed seems to need special casing for PHY
testing.

--Imre
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  reply	other threads:[~2021-01-19 18:44 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-22  6:48 [Intel-gfx] [PATCH] drm/i915/dp: DPTX writes Swing/Pre-emphs(DPCD 0x103-0x106) requested during PHY Layer testing Khaled Almahallawy
2020-08-22  7:08 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-08-22  7:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-08-22  8:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-08-24 21:12 ` [Intel-gfx] [PATCH] " Navare, Manasi
2021-01-13 15:04 ` Imre Deak
2021-01-19  7:43   ` Almahallawy, Khaled
2021-01-19 17:26     ` Imre Deak [this message]
2021-02-26  8:15 ` [Intel-gfx] [PATCH v2] " Khaled Almahallawy
2021-07-06 22:30   ` Almahallawy, Khaled
2021-07-29 16:50   ` Imre Deak
2021-02-26  8:52 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: DPTX writes Swing/Pre-emphs(DPCD 0x103-0x106) requested during PHY Layer testing. (rev2) Patchwork
2021-02-26  9:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-02-26 11:24 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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