From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI v5 10/18] drm/i915/display/vrr: Configure and enable VRR in modeset enable
Date: Fri, 22 Jan 2021 15:26:39 -0800 [thread overview]
Message-ID: <20210122232647.22688-10-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20210122232647.22688-1-manasi.d.navare@intel.com>
This patch computes the VRR parameters from VRR crtc states
and configures them in VRR registers during CRTC enable in
the modeset enable sequence.
v2:
* Remove initialization to 0 (Jani N)
* Use correct pipe %c (Jani N)
v3:
* Remove debug prints (Ville)
* Use cpu_trans instead of pipe for TRANS_VRR regs (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++
drivers/gpu/drm/i915/display/intel_vrr.c | 22 ++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vrr.h | 3 +++
3 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d4c09a1aa06e..d1cb0499a5c4 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -51,6 +51,7 @@
#include "intel_sprite.h"
#include "intel_tc.h"
#include "intel_vdsc.h"
+#include "intel_vrr.h"
struct ddi_buf_trans {
u32 trans1; /* balance leg enable, de-emph level */
@@ -4310,6 +4311,8 @@ static void intel_enable_ddi(struct intel_atomic_state *state,
if (!crtc_state->bigjoiner_slave)
intel_ddi_enable_transcoder_func(encoder, crtc_state);
+ intel_vrr_enable(encoder, crtc_state);
+
intel_enable_pipe(crtc_state);
intel_crtc_vblank_on(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 346ea3c16cc8..b2545ddc8fc5 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -99,3 +99,25 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
crtc_state->vrr.pipeline_full =
min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1);
}
+
+void intel_vrr_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 trans_vrr_ctl;
+
+ if (!crtc_state->vrr.enable)
+ return;
+
+ trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
+ VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
+ VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) |
+ VRR_CTL_PIPELINE_FULL_OVERRIDE;
+
+ intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
+ intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
+ intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl);
+ intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);
+ intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 67c477d6d1a4..80c33fbd0639 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -14,10 +14,13 @@ struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_dp;
+struct intel_encoder;
bool intel_vrr_is_capable(struct drm_connector *connector);
void intel_vrr_check_modeset(struct intel_atomic_state *state);
void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state);
+void intel_vrr_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_VRR_H__ */
--
2.19.1
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next prev parent reply other threads:[~2021-01-22 23:22 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-22 23:26 [Intel-gfx] [CI v5 01/18] drm/i915/display/vrr: Create VRR file and add VRR capability check Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 02/18] drm/i915/display/dp: Attach and set drm connector VRR property Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 03/18] drm/i915: Store framestart_delay in dev_priv Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 04/18] drm/i915: Extract intel_mode_vblank_start() Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 05/18] drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp() Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 06/18] drm/i915/display/dp: Compute VRR state in atomic_check Manasi Navare
2021-01-25 11:41 ` Ville Syrjälä
2021-01-22 23:26 ` [Intel-gfx] [CI v5 07/18] drm/i915/display/dp: Do not enable PSR if VRR is enabled Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 08/18] drm/i915/display: VRR + DRRS cannot be enabled together Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 09/18] drm/i915: Rename VRR_CTL reg fields Manasi Navare
2021-01-22 23:26 ` Manasi Navare [this message]
2021-01-22 23:26 ` [Intel-gfx] [CI v5 11/18] drm/i915/display/vrr: Send VRR push to flip the frame Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 12/18] drm/i915/display/vrr: Disable VRR in modeset disable path Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 13/18] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 14/18] drm/i915/display: Add HW state readout for VRR Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 15/18] drm/i915/display: Helpers for VRR vblank min and max start Manasi Navare
2021-01-25 11:42 ` Ville Syrjälä
2021-01-22 23:26 ` [Intel-gfx] [CI v5 16/18] drm/i915: Add vrr state dump Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 17/18] drm/i915: Fix vblank timestamps with VRR Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 18/18] drm/i915: Fix vblank evasion with vrr Manasi Navare
2021-01-23 2:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v5,01/18] drm/i915/display/vrr: Create VRR file and add VRR capability check Patchwork
2021-01-23 2:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-23 3:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-23 13:56 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-01-25 20:08 ` [Intel-gfx] [CI v6] " Manasi Navare
2021-01-25 20:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v6] drm/i915/display/vrr: Create VRR file and add VRR capability check (rev2) Patchwork
2021-01-25 20:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-25 21:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-26 2:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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