From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 1/8] drm/i915/selftests: Set cache status for huge_gem_object
Date: Wed, 3 Feb 2021 09:01:58 +0000 [thread overview]
Message-ID: <20210203090205.25818-1-chris@chris-wilson.co.uk> (raw)
Set the cache coherency and status using the set-coherency helper.
Otherwise, we forget to mark the new pages as cache dirty.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 14 +++++---------
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index aacf4856ccb4..f6329e462cfc 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -171,10 +171,8 @@ huge_pages_object(struct drm_i915_private *i915,
i915_gem_object_init(obj, &huge_page_ops, &lock_class);
i915_gem_object_set_volatile(obj);
-
- obj->write_domain = I915_GEM_DOMAIN_CPU;
- obj->read_domains = I915_GEM_DOMAIN_CPU;
- obj->cache_level = I915_CACHE_NONE;
+ i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
+ __start_cpu_write(obj);
obj->mm.page_mask = page_mask;
@@ -324,10 +322,8 @@ fake_huge_pages_object(struct drm_i915_private *i915, u64 size, bool single)
i915_gem_object_init(obj, &fake_ops, &lock_class);
i915_gem_object_set_volatile(obj);
-
- obj->write_domain = I915_GEM_DOMAIN_CPU;
- obj->read_domains = I915_GEM_DOMAIN_CPU;
- obj->cache_level = I915_CACHE_NONE;
+ i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
+ __start_cpu_write(obj);
return obj;
}
@@ -994,7 +990,7 @@ __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32 val)
u32 *ptr = kmap_atomic(i915_gem_object_get_page(obj, n));
if (needs_flush & CLFLUSH_BEFORE)
- drm_clflush_virt_range(ptr, PAGE_SIZE);
+ drm_clflush_virt_range(&ptr[dword], sizeof(val));
if (ptr[dword] != val) {
pr_err("n=%lu ptr[%u]=%u, val=%u\n",
--
2.20.1
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next reply other threads:[~2021-02-03 9:02 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-03 9:01 Chris Wilson [this message]
2021-02-03 9:01 ` [Intel-gfx] [CI 2/8] drm/i915/selftests: Use a coherent map to setup scratch batch buffers Chris Wilson
2021-02-03 9:02 ` [Intel-gfx] [CI 3/8] drm/i915/selftests: Replace the unbounded set-domain with an explicit wait Chris Wilson
2021-02-03 9:02 ` [Intel-gfx] [CI 4/8] drm/i915/selftests: Remove redundant set-to-gtt-domain Chris Wilson
2021-02-03 9:02 ` [Intel-gfx] [CI 5/8] drm/i915/selftests: Replace unbound set-domain waits with explicit timeouts Chris Wilson
2021-02-03 9:02 ` [Intel-gfx] [CI 6/8] drm/i915/selftests: Replace an unbounded set-domain wait with a timeout Chris Wilson
2021-02-03 9:02 ` [Intel-gfx] [CI 7/8] drm/i915/selftests: Remove redundant set-to-gtt-domain before batch submission Chris Wilson
2021-02-03 9:02 ` [Intel-gfx] [CI 8/8] drm/i915/gem: Manage all set-domain waits explicitly Chris Wilson
2021-02-03 10:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/8] drm/i915/selftests: Set cache status for huge_gem_object Patchwork
2021-02-03 13:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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