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From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Subject: [Intel-gfx] [PATCH 03/18] drm/i915/guc: Add LRC descriptor context lookup array
Date: Tue, 20 Jul 2021 15:39:06 -0700	[thread overview]
Message-ID: <20210720223921.56160-4-matthew.brost@intel.com> (raw)
In-Reply-To: <20210720223921.56160-1-matthew.brost@intel.com>

Add LRC descriptor context lookup array which can resolve the
intel_context from the LRC descriptor index. In addition to lookup, it
can determine if the LRC descriptor context is currently registered with
the GuC by checking if an entry for a descriptor index is present.
Future patches in the series will make use of this array.

v2:
 (Michal)
  - "linux/xarray.h" -> <linux/xarray.h>
  - s/lrc/LRC
 (John H)
  - Fix commit message

Cc: John Harrison <john.c.harrison@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.h        |  5 +++
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 32 +++++++++++++++++--
 2 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 2625d2d5959f..35783558d261 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -6,6 +6,8 @@
 #ifndef _INTEL_GUC_H_
 #define _INTEL_GUC_H_
 
+#include <linux/xarray.h>
+
 #include "intel_uncore.h"
 #include "intel_guc_fw.h"
 #include "intel_guc_fwif.h"
@@ -46,6 +48,9 @@ struct intel_guc {
 	struct i915_vma *lrc_desc_pool;
 	void *lrc_desc_pool_vaddr;
 
+	/* guc_id to intel_context lookup */
+	struct xarray context_lookup;
+
 	/* Control params for fw initialization */
 	u32 params[GUC_CTL_MAX_DWORDS];
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index a366890fb840..23a94a896a0b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -65,8 +65,6 @@ static inline struct i915_priolist *to_priolist(struct rb_node *rb)
 	return rb_entry(rb, struct i915_priolist, node);
 }
 
-/* Future patches will use this function */
-__attribute__ ((unused))
 static struct guc_lrc_desc *__get_lrc_desc(struct intel_guc *guc, u32 index)
 {
 	struct guc_lrc_desc *base = guc->lrc_desc_pool_vaddr;
@@ -76,6 +74,15 @@ static struct guc_lrc_desc *__get_lrc_desc(struct intel_guc *guc, u32 index)
 	return &base[index];
 }
 
+static inline struct intel_context *__get_context(struct intel_guc *guc, u32 id)
+{
+	struct intel_context *ce = xa_load(&guc->context_lookup, id);
+
+	GEM_BUG_ON(id >= GUC_MAX_LRC_DESCRIPTORS);
+
+	return ce;
+}
+
 static int guc_lrc_desc_pool_create(struct intel_guc *guc)
 {
 	u32 size;
@@ -96,6 +103,25 @@ static void guc_lrc_desc_pool_destroy(struct intel_guc *guc)
 	i915_vma_unpin_and_release(&guc->lrc_desc_pool, I915_VMA_RELEASE_MAP);
 }
 
+static inline void reset_lrc_desc(struct intel_guc *guc, u32 id)
+{
+	struct guc_lrc_desc *desc = __get_lrc_desc(guc, id);
+
+	memset(desc, 0, sizeof(*desc));
+	xa_erase_irq(&guc->context_lookup, id);
+}
+
+static inline bool lrc_desc_registered(struct intel_guc *guc, u32 id)
+{
+	return __get_context(guc, id);
+}
+
+static inline void set_lrc_desc_registered(struct intel_guc *guc, u32 id,
+					   struct intel_context *ce)
+{
+	xa_store_irq(&guc->context_lookup, id, ce, GFP_ATOMIC);
+}
+
 static void guc_add_request(struct intel_guc *guc, struct i915_request *rq)
 {
 	/* Leaving stub as this function will be used in future patches */
@@ -400,6 +426,8 @@ int intel_guc_submission_init(struct intel_guc *guc)
 	 */
 	GEM_BUG_ON(!guc->lrc_desc_pool);
 
+	xa_init_flags(&guc->context_lookup, XA_FLAGS_LOCK_IRQ);
+
 	return 0;
 }
 
-- 
2.28.0

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  parent reply	other threads:[~2021-07-20 22:21 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-20 22:39 [Intel-gfx] [PATCH 00/18] Series to merge a subset of GuC submission Matthew Brost
2021-07-20 22:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2021-07-20 22:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-20 22:35 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-07-20 22:39 ` [Intel-gfx] [PATCH 01/18] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost
2021-07-20 22:39 ` [Intel-gfx] [PATCH 02/18] drm/i915/guc: Remove GuC stage descriptor, add LRC descriptor Matthew Brost
2021-07-20 22:39 ` Matthew Brost [this message]
2021-07-20 22:39 ` [Intel-gfx] [PATCH 04/18] drm/i915/guc: Implement GuC submission tasklet Matthew Brost
2021-07-21  0:11   ` John Harrison
2021-07-20 22:39 ` [Intel-gfx] [PATCH 05/18] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost
2021-07-20 22:39 ` [Intel-gfx] [PATCH 06/18] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost
2021-07-21  1:51   ` John Harrison
2021-07-21 23:57     ` Daniele Ceraolo Spurio
2021-07-20 22:39 ` [Intel-gfx] [PATCH 07/18] drm/i915/guc: Insert fence on context when deregistering Matthew Brost
2021-07-20 22:39 ` [Intel-gfx] [PATCH 08/18] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost
2021-07-20 22:39 ` [Intel-gfx] [PATCH 09/18] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost
2021-07-20 22:39 ` [Intel-gfx] [PATCH 10/18] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost
2021-07-20 22:39 ` [Intel-gfx] [PATCH 11/18] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost
2021-07-20 22:39 ` [Intel-gfx] [PATCH 12/18] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost
2021-07-21 21:10   ` Daniele Ceraolo Spurio
2021-07-20 22:39 ` [Intel-gfx] [PATCH 13/18] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost
2021-07-20 22:39 ` [Intel-gfx] [PATCH 14/18] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost
2021-07-20 22:39 ` [Intel-gfx] [PATCH 15/18] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost
2021-07-20 22:39 ` [Intel-gfx] [PATCH 16/18] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost
2021-07-20 22:39 ` [Intel-gfx] [PATCH 17/18] drm/i915/guc: Add trace point for GuC submit Matthew Brost
2021-07-20 22:39 ` [Intel-gfx] [PATCH 18/18] drm/i915: Add intel_context tracing Matthew Brost
2021-07-20 22:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Series to merge a subset of GuC submission Patchwork
2021-07-21  0:04 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-07-21 21:50 [Intel-gfx] [PATCH 00/18] " Matthew Brost
2021-07-21 21:50 ` [Intel-gfx] [PATCH 03/18] drm/i915/guc: Add LRC descriptor context lookup array Matthew Brost

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