Re: [Intel-gfx] [PATCH v2 06/50] drm/i915/xehp: Extra media engines - Part 1 (engine definitions)

From: Lucas De Marchi <lucas.demarchi@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org, Tomas Winkler <tomas.winkler@intel.com>
Subject: Re: [Intel-gfx] [PATCH v2 06/50] drm/i915/xehp: Extra media engines - Part 1 (engine definitions)
Date: Wed, 21 Jul 2021 11:23:00 -0700	[thread overview]
Message-ID: <20210721182300.2wonb4hmfmtkqlsy@ldmartin-desk2> (raw)
In-Reply-To: <20210714031540.3539704-7-matthew.d.roper@intel.com>

On Tue, Jul 13, 2021 at 08:14:56PM -0700, Matt Roper wrote:
>From: John Harrison <John.C.Harrison@Intel.com>
>
>Xe_HP can have a lot of extra media engines. This patch adds the basic
>definitions for them.
>
>v2:
> - Re-order intel_gt_info and intel_device_info slightly to avoid
>   unnecessary padding now that we've increased the size of
>   intel_engine_mask_t.  (Tvrtko)
>
>Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c     |  7 ++-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 50 ++++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 ++++--
> drivers/gpu/drm/i915/gt/intel_gt_types.h     |  5 +-
> drivers/gpu/drm/i915/i915_reg.h              |  6 +++
> drivers/gpu/drm/i915/intel_device_info.h     |  3 +-
> 6 files changed, 74 insertions(+), 11 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>index 87b06572fd2e..35edc55720f4 100644
>--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>@@ -279,7 +279,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
> 	if (mode & EMIT_INVALIDATE)
> 		aux_inv = rq->engine->mask & ~BIT(BCS0);
> 	if (aux_inv)
>-		cmd += 2 * hweight8(aux_inv) + 2;
>+		cmd += 2 * hweight32(aux_inv) + 2;
>
> 	cs = intel_ring_begin(rq, cmd);
> 	if (IS_ERR(cs))
>@@ -313,9 +313,8 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
> 		struct intel_engine_cs *engine;
> 		unsigned int tmp;
>
>-		*cs++ = MI_LOAD_REGISTER_IMM(hweight8(aux_inv));
>-		for_each_engine_masked(engine, rq->engine->gt,
>-				       aux_inv, tmp) {
>+		*cs++ = MI_LOAD_REGISTER_IMM(hweight32(aux_inv));
>+		for_each_engine_masked(engine, rq->engine->gt, aux_inv, tmp) {
> 			*cs++ = i915_mmio_reg_offset(aux_inv_reg(engine));
> 			*cs++ = AUX_INV;
> 		}
>diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>index 3f8013612a08..6c2cb1400c8c 100644
>--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>@@ -104,6 +104,38 @@ static const struct engine_info intel_engines[] = {
> 			{ .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE }
> 		},
> 	},
>+	[VCS4] = {
>+		.hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */
>+		.class = VIDEO_DECODE_CLASS,
>+		.instance = 4,
>+		.mmio_bases = {
>+			{ .graphics_ver = 11, .base = XEHP_BSD5_RING_BASE }

another weird thing in this... we are using XEHP_BSD5_RING_BASE, but we
set .graphics_ver to 11. Was that a typo? From bspec 11754 and 3293 it
seems the register is there, but it doesn't mean it can actually be used
according to bspec 21137 and 20189. So I guess it was either a typo or a
rebase issue and should be changed to graphics_ver = 12.

thanks
Lucas De Marchi
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