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From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>
Subject: [Intel-gfx] [PATCH 10/10] drm/i915/display/tgl+: Use PPS index from vbt
Date: Wed, 21 Jul 2021 22:43:38 -0700	[thread overview]
Message-ID: <20210722054338.12891-10-jose.souza@intel.com> (raw)
In-Reply-To: <20210722054338.12891-1-jose.souza@intel.com>

Tigerlake and newer has two instances of PPS, to support up to two
eDP panels.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_pps.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index f4c15a1f31d15..ee92f416834e5 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -368,7 +368,8 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
 
 	memset(regs, 0, sizeof(*regs));
 
-	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
+	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ||
+	    DISPLAY_VER(dev_priv) >= 12)
 		pps_idx = bxt_power_sequencer_idx(intel_dp);
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		pps_idx = vlv_power_sequencer_pipe(intel_dp);
-- 
2.32.0

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  parent reply	other threads:[~2021-07-22  5:39 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-22  5:43 [Intel-gfx] [PATCH 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() José Roberto de Souza
2021-07-22  5:43 ` [Intel-gfx] [PATCH 02/10] drm/i915/bios: Start to support two integrated panels José Roberto de Souza
2021-07-26 21:33   ` Matt Atwood
2021-08-16 10:09   ` Jani Nikula
2021-08-16 19:52     ` Ville Syrjälä
2021-07-22  5:43 ` [Intel-gfx] [PATCH 03/10] drm/i915/bios: Enable parse of two integrated panels timing data José Roberto de Souza
2021-07-26 21:36   ` Matt Atwood
2021-07-22  5:43 ` [Intel-gfx] [PATCH 04/10] drm/i915/bios: Enable parse of two integrated panels backlight data José Roberto de Souza
2021-07-26 22:12   ` Matt Atwood
2021-07-22  5:43 ` [Intel-gfx] [PATCH 05/10] drm/i915/bios: Enable parse of two integrated panels eDP data José Roberto de Souza
2021-07-27 21:15   ` Matt Atwood
2021-08-17  8:08   ` Jani Nikula
2021-07-22  5:43 ` [Intel-gfx] [PATCH 06/10] drm/i915/bios: Enable parse of two integrated panels PSR data José Roberto de Souza
2021-07-27 22:53   ` Matt Atwood
2021-07-22  5:43 ` [Intel-gfx] [PATCH 07/10] drm/i915/bios: Enable parse of two DSI panels data José Roberto de Souza
2021-07-28 15:19   ` Matt Atwood
2021-07-22  5:43 ` [Intel-gfx] [PATCH 08/10] drm/i915/bios: Nuke panel_type José Roberto de Souza
2021-07-28 15:21   ` Matt Atwood
2021-07-22  5:43 ` [Intel-gfx] [PATCH 09/10] drm/i915/bios: Only use opregion panel index for display ver 8 and older José Roberto de Souza
2021-07-28 15:22   ` Matt Atwood
2021-08-16 19:39   ` Ville Syrjälä
2021-07-22  5:43 ` José Roberto de Souza [this message]
2021-07-28 15:23   ` [Intel-gfx] [PATCH 10/10] drm/i915/display/tgl+: Use PPS index from vbt Matt Atwood
2021-07-22  6:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() Patchwork
2021-07-22  6:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-22  6:37 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-07-22 19:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() (rev2) Patchwork
2021-07-22 19:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-22 20:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-23  0:01 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-07-26 21:21 ` [Intel-gfx] [PATCH 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() Matt Atwood
2021-07-26 22:23 ` Matt Atwood
2021-08-16  9:59 ` Jani Nikula

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