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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 22/28] drm/i915: rename CNL references in intel_dram.c
Date: Tue, 27 Jul 2021 00:18:39 -0700	[thread overview]
Message-ID: <20210727071845.841554-22-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20210727071845.841554-1-lucas.demarchi@intel.com>

With the removal of CNL, let's consider ICL as the first platform using
those constants.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   | 24 +++++++++++------------
 drivers/gpu/drm/i915/intel_dram.c | 32 +++++++++++++++----------------
 2 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 36bde25426bd..e2a373784d5b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11109,18 +11109,18 @@ enum skl_power_gate {
 #define  SKL_DRAM_RANK_1			(0x0 << 10)
 #define  SKL_DRAM_RANK_2			(0x1 << 10)
 #define  SKL_DRAM_RANK_MASK			(0x1 << 10)
-#define  CNL_DRAM_SIZE_MASK			0x7F
-#define  CNL_DRAM_WIDTH_MASK			(0x3 << 7)
-#define  CNL_DRAM_WIDTH_SHIFT			7
-#define  CNL_DRAM_WIDTH_X8			(0x0 << 7)
-#define  CNL_DRAM_WIDTH_X16			(0x1 << 7)
-#define  CNL_DRAM_WIDTH_X32			(0x2 << 7)
-#define  CNL_DRAM_RANK_MASK			(0x3 << 9)
-#define  CNL_DRAM_RANK_SHIFT			9
-#define  CNL_DRAM_RANK_1			(0x0 << 9)
-#define  CNL_DRAM_RANK_2			(0x1 << 9)
-#define  CNL_DRAM_RANK_3			(0x2 << 9)
-#define  CNL_DRAM_RANK_4			(0x3 << 9)
+#define  ICL_DRAM_SIZE_MASK			0x7F
+#define  ICL_DRAM_WIDTH_MASK			(0x3 << 7)
+#define  ICL_DRAM_WIDTH_SHIFT			7
+#define  ICL_DRAM_WIDTH_X8			(0x0 << 7)
+#define  ICL_DRAM_WIDTH_X16			(0x1 << 7)
+#define  ICL_DRAM_WIDTH_X32			(0x2 << 7)
+#define  ICL_DRAM_RANK_MASK			(0x3 << 9)
+#define  ICL_DRAM_RANK_SHIFT			9
+#define  ICL_DRAM_RANK_1			(0x0 << 9)
+#define  ICL_DRAM_RANK_2			(0x1 << 9)
+#define  ICL_DRAM_RANK_3			(0x2 << 9)
+#define  ICL_DRAM_RANK_4			(0x3 << 9)
 
 #define SA_PERF_STATUS_0_0_0_MCHBAR_PC		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
 #define  DG1_QCLK_RATIO_MASK			REG_GENMASK(9, 2)
diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
index 9675bb94b70b..34d6cf440352 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -77,21 +77,21 @@ static int skl_get_dimm_ranks(u16 val)
 }
 
 /* Returns total Gb for the whole DIMM */
-static int cnl_get_dimm_size(u16 val)
+static int icl_get_dimm_size(u16 val)
 {
-	return (val & CNL_DRAM_SIZE_MASK) * 8 / 2;
+	return (val & ICL_DRAM_SIZE_MASK) * 8 / 2;
 }
 
-static int cnl_get_dimm_width(u16 val)
+static int icl_get_dimm_width(u16 val)
 {
-	if (cnl_get_dimm_size(val) == 0)
+	if (icl_get_dimm_size(val) == 0)
 		return 0;
 
-	switch (val & CNL_DRAM_WIDTH_MASK) {
-	case CNL_DRAM_WIDTH_X8:
-	case CNL_DRAM_WIDTH_X16:
-	case CNL_DRAM_WIDTH_X32:
-		val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
+	switch (val & ICL_DRAM_WIDTH_MASK) {
+	case ICL_DRAM_WIDTH_X8:
+	case ICL_DRAM_WIDTH_X16:
+	case ICL_DRAM_WIDTH_X32:
+		val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT;
 		return 8 << val;
 	default:
 		MISSING_CASE(val);
@@ -99,12 +99,12 @@ static int cnl_get_dimm_width(u16 val)
 	}
 }
 
-static int cnl_get_dimm_ranks(u16 val)
+static int icl_get_dimm_ranks(u16 val)
 {
-	if (cnl_get_dimm_size(val) == 0)
+	if (icl_get_dimm_size(val) == 0)
 		return 0;
 
-	val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
+	val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT;
 
 	return val + 1;
 }
@@ -121,10 +121,10 @@ skl_dram_get_dimm_info(struct drm_i915_private *i915,
 		       struct dram_dimm_info *dimm,
 		       int channel, char dimm_name, u16 val)
 {
-	if (GRAPHICS_VER(i915) >= 10) {
-		dimm->size = cnl_get_dimm_size(val);
-		dimm->width = cnl_get_dimm_width(val);
-		dimm->ranks = cnl_get_dimm_ranks(val);
+	if (GRAPHICS_VER(i915) >= 11) {
+		dimm->size = icl_get_dimm_size(val);
+		dimm->width = icl_get_dimm_width(val);
+		dimm->ranks = icl_get_dimm_ranks(val);
 	} else {
 		dimm->size = skl_get_dimm_size(val);
 		dimm->width = skl_get_dimm_width(val);
-- 
2.31.1

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  parent reply	other threads:[~2021-07-27  7:19 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-27  7:18 [Intel-gfx] [CI 01/28] drm/i915/display: remove PORT_F workaround for CNL Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 02/28] drm/i915/display: remove explicit CNL handling from intel_cdclk.c Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 03/28] drm/i915/display: remove explicit CNL handling from intel_color.c Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 04/28] drm/i915/display: remove explicit CNL handling from intel_combo_phy.c Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 05/28] drm/i915/display: remove explicit CNL handling from intel_crtc.c Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 06/28] drm/i915/display: remove explicit CNL handling from intel_ddi.c Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 07/28] drm/i915/display: remove explicit CNL handling from intel_display_debugfs.c Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 08/28] drm/i915/display: remove explicit CNL handling from intel_dmc.c Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 09/28] drm/i915/display: remove explicit CNL handling from intel_dp.c Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 10/28] drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.c Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 11/28] drm/i915/display: remove explicit CNL handling from intel_vdsc.c Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 12/28] drm/i915/display: remove explicit CNL handling from skl_universal_plane.c Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 13/28] drm/i915/display: remove explicit CNL handling from intel_display_power.c Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 14/28] drm/i915/display: remove CNL ddi buf translation tables Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 15/28] drm/i915/display: rename CNL references in skl_scaler.c Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 16/28] drm/i915: remove explicit CNL handling from i915_irq.c Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 17/28] drm/i915: remove explicit CNL handling from intel_pm.c Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 18/28] drm/i915: remove explicit CNL handling from intel_mocs.c Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 19/28] drm/i915: remove explicit CNL handling from intel_pch.c Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 20/28] drm/i915: remove explicit CNL handling from intel_wopcm.c Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 21/28] drm/i915/gt: remove explicit CNL handling from intel_sseu.c Lucas De Marchi
2021-07-27  7:18 ` Lucas De Marchi [this message]
2021-07-27  7:18 ` [Intel-gfx] [CI 23/28] drm/i915/gt: rename CNL references in intel_engine.h Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 24/28] drm/i915: finish removal of CNL Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 25/28] drm/i915: remove GRAPHICS_VER == 10 Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 26/28] drm/i915: rename/remove CNL registers Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 27/28] drm/i915: replace random CNL comments Lucas De Marchi
2021-07-27  7:18 ` [Intel-gfx] [CI 28/28] drm/i915: switch num_scalers/num_sprites to consider DISPLAY_VER Lucas De Marchi
2021-07-27 16:45   ` [Intel-gfx] [PATCH v2.1] " Lucas De Marchi
2021-07-27  7:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,01/28] drm/i915/display: remove PORT_F workaround for CNL Patchwork
2021-07-27  7:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-27  8:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-27 13:48 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-07-27 17:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,01/28] drm/i915/display: remove PORT_F workaround for CNL (rev2) Patchwork
2021-07-27 17:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-27 18:18 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-28  3:23 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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