* [Intel-gfx] [PATCH CI 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port()
@ 2021-07-29 21:55 José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 02/10] drm/i915/bios: Start to support two integrated panels José Roberto de Souza
` (12 more replies)
0 siblings, 13 replies; 14+ messages in thread
From: José Roberto de Souza @ 2021-07-29 21:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Allow MIPI DSI ports to be parsed like any other DDI port.
This will be helpful to integrate into just one function the parse of
information about integrated panels(eDP and DSI).
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 22 +++++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index aa667fa711584..a6cb33f847a43 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1709,10 +1709,10 @@ static enum port dvo_port_to_port(struct drm_i915_private *i915,
* so look for all the possible values for each port.
*/
static const int port_mapping[][3] = {
- [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
- [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
- [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
- [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+ [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, DVO_PORT_MIPIA },
+ [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, DVO_PORT_MIPIB },
+ [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, DVO_PORT_MIPIC },
+ [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, DVO_PORT_MIPID },
[PORT_E] = { DVO_PORT_HDMIE, DVO_PORT_DPE, DVO_PORT_CRT },
[PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },
[PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },
@@ -1868,6 +1868,12 @@ intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata)
devdata->child.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR;
}
+static bool
+intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data *devdata)
+{
+ return devdata->child.device_type & DEVICE_TYPE_MIPI_OUTPUT;
+}
+
static bool is_port_valid(struct drm_i915_private *i915, enum port port)
{
/*
@@ -1886,7 +1892,8 @@ static void parse_ddi_port(struct drm_i915_private *i915,
{
const struct child_device_config *child = &devdata->child;
struct ddi_vbt_port_info *info;
- bool is_dvi, is_hdmi, is_dp, is_edp, is_crt, supports_typec_usb, supports_tbt;
+ bool is_dvi, is_hdmi, is_dp, is_edp, is_crt, supports_typec_usb;
+ bool supports_tbt, is_dsi;
int dp_boost_level, hdmi_boost_level;
enum port port;
@@ -1917,16 +1924,17 @@ static void parse_ddi_port(struct drm_i915_private *i915,
is_crt = intel_bios_encoder_supports_crt(devdata);
is_hdmi = intel_bios_encoder_supports_hdmi(devdata);
is_edp = intel_bios_encoder_supports_edp(devdata);
+ is_dsi = intel_bios_encoder_supports_dsi(devdata);
supports_typec_usb = intel_bios_encoder_supports_typec_usb(devdata);
supports_tbt = intel_bios_encoder_supports_tbt(devdata);
drm_dbg_kms(&i915->drm,
- "Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n",
+ "Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d DSI:%d\n",
port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp,
HAS_LSPCON(i915) && child->lspcon,
supports_typec_usb, supports_tbt,
- devdata->dsc != NULL);
+ devdata->dsc != NULL, is_dsi);
if (is_dvi) {
u8 ddc_pin;
--
2.32.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH CI 02/10] drm/i915/bios: Start to support two integrated panels
2021-07-29 21:55 [Intel-gfx] [PATCH CI 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() José Roberto de Souza
@ 2021-07-29 21:55 ` José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 03/10] drm/i915/bios: Enable parse of two integrated panels timing data José Roberto de Souza
` (11 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: José Roberto de Souza @ 2021-07-29 21:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
VBT has support for up two integrated panels but i915 only supports one.
So here stating to add the basic support for two integrated panels
and moving the DRRS to ddi_vbt_port_info instead of keeping a global
one.
Other VBT blocks will be converted in following patches.
While at is also nucking lvds_dither as it is not used.
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 185 +++++++++++++-----
drivers/gpu/drm/i915/display/intel_bios.h | 2 +
drivers/gpu/drm/i915/display/intel_dp.c | 5 +-
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 +
drivers/gpu/drm/i915/i915_drv.h | 5 +-
5 files changed, 150 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index a6cb33f847a43..9439bfe32b136 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -211,22 +211,20 @@ get_lvds_fp_timing(const struct bdb_header *bdb,
return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);
}
-/* Parse general panel options */
-static void
-parse_panel_options(struct drm_i915_private *i915,
- const struct bdb_header *bdb)
+/*
+ * Parse and set vbt.panel_type, it will be used by the VBT blocks that are
+ * not being called from parse_integrated_panel() yet.
+ */
+static void parse_panel_type(struct drm_i915_private *i915,
+ const struct bdb_header *bdb)
{
const struct bdb_lvds_options *lvds_options;
- int panel_type;
- int drrs_mode;
- int ret;
+ int ret, panel_type;
lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
if (!lvds_options)
return;
- i915->vbt.lvds_dither = lvds_options->pixel_dither;
-
ret = intel_opregion_get_panel_type(i915);
if (ret >= 0) {
drm_WARN_ON(&i915->drm, ret > 0xf);
@@ -246,9 +244,25 @@ parse_panel_options(struct drm_i915_private *i915,
}
i915->vbt.panel_type = panel_type;
+}
+
+/* Parse general panel options */
+static void
+parse_panel_options(struct drm_i915_private *i915,
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info,
+ int panel_index)
+{
+ const struct bdb_lvds_options *lvds_options;
+ int drrs_mode;
+
+ lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
+ if (!lvds_options)
+ return;
+
+ drrs_mode = lvds_options->dps_panel_type_bits >> (panel_index * 2);
+ drrs_mode &= MODE_MASK;
- drrs_mode = (lvds_options->dps_panel_type_bits
- >> (panel_type * 2)) & MODE_MASK;
/*
* VBT has static DRRS = 0 and seamless DRRS = 2.
* The below piece of code is required to adjust vbt.drrs_type
@@ -256,16 +270,16 @@ parse_panel_options(struct drm_i915_private *i915,
*/
switch (drrs_mode) {
case 0:
- i915->vbt.drrs_type = STATIC_DRRS_SUPPORT;
+ info->drrs_type = STATIC_DRRS_SUPPORT;
drm_dbg_kms(&i915->drm, "DRRS supported mode is static\n");
break;
case 2:
- i915->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT;
+ info->drrs_type = SEAMLESS_DRRS_SUPPORT;
drm_dbg_kms(&i915->drm,
"DRRS supported mode is seamless\n");
break;
default:
- i915->vbt.drrs_type = DRRS_NOT_SUPPORTED;
+ info->drrs_type = DRRS_NOT_SUPPORTED;
drm_dbg_kms(&i915->drm,
"DRRS not supported (VBT input)\n");
break;
@@ -710,28 +724,42 @@ parse_driver_features(struct drm_i915_private *i915,
i915->vbt.int_lvds_support = 0;
}
- if (bdb->version < 228) {
- drm_dbg_kms(&i915->drm, "DRRS State Enabled:%d\n",
- driver->drrs_enabled);
- /*
- * If DRRS is not supported, drrs_type has to be set to 0.
- * This is because, VBT is configured in such a way that
- * static DRRS is 0 and DRRS not supported is represented by
- * driver->drrs_enabled=false
- */
- if (!driver->drrs_enabled)
- i915->vbt.drrs_type = DRRS_NOT_SUPPORTED;
-
+ if (bdb->version < 228)
i915->vbt.psr.enable = driver->psr_enabled;
- }
+}
+
+static void
+parse_driver_features_drrs_only(struct drm_i915_private *i915,
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info)
+{
+ const struct bdb_driver_features *driver;
+
+ if (bdb->version >= 228)
+ return;
+
+ driver = find_section(bdb, BDB_DRIVER_FEATURES);
+ if (!driver)
+ return;
+
+ drm_dbg_kms(&i915->drm, "DRRS State Enabled:%d\n", driver->drrs_enabled);
+ /*
+ * If DRRS is not supported, drrs_type has to be set to 0.
+ * This is because, VBT is configured in such a way that
+ * static DRRS is 0 and DRRS not supported is represented by
+ * driver->drrs_enabled=false
+ */
+ if (!driver->drrs_enabled)
+ info->drrs_type = DRRS_NOT_SUPPORTED;
}
static void
parse_power_conservation_features(struct drm_i915_private *i915,
- const struct bdb_header *bdb)
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info,
+ int panel_index)
{
const struct bdb_lfp_power *power;
- u8 panel_type = i915->vbt.panel_type;
if (bdb->version < 228)
return;
@@ -740,7 +768,7 @@ parse_power_conservation_features(struct drm_i915_private *i915,
if (!power)
return;
- i915->vbt.psr.enable = power->psr & BIT(panel_type);
+ i915->vbt.psr.enable = power->psr & BIT(panel_index);
/*
* If DRRS is not supported, drrs_type has to be set to 0.
@@ -748,11 +776,11 @@ parse_power_conservation_features(struct drm_i915_private *i915,
* static DRRS is 0 and DRRS not supported is represented by
* power->drrs & BIT(panel_type)=false
*/
- if (!(power->drrs & BIT(panel_type)))
- i915->vbt.drrs_type = DRRS_NOT_SUPPORTED;
+ if (!(power->drrs & BIT(panel_index)))
+ info->drrs_type = DRRS_NOT_SUPPORTED;
if (bdb->version >= 232)
- i915->vbt.edp.hobl = power->hobl & BIT(panel_type);
+ i915->vbt.edp.hobl = power->hobl & BIT(panel_index);
}
static void
@@ -1887,6 +1915,74 @@ static bool is_port_valid(struct drm_i915_private *i915, enum port port)
return true;
}
+static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt)
+{
+ const void *_vbt = vbt;
+
+ return _vbt + vbt->bdb_offset;
+}
+
+static int
+get_lfp_panel_index(struct drm_i915_private *i915,
+ const struct bdb_header *bdb, int lfp_panel_instance)
+{
+ const struct bdb_lvds_options *lvds_options;
+
+ lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
+ if (!lvds_options)
+ return -1;
+
+ switch (lfp_panel_instance) {
+ case 1:
+ return lvds_options->panel_type;
+ case 2:
+ return lvds_options->panel_type2;
+ default:
+ break;
+ }
+
+ return -1;
+}
+
+static void parse_integrated_panel(struct drm_i915_private *i915,
+ struct intel_bios_encoder_data *devdata,
+ struct ddi_vbt_port_info *info)
+{
+ const struct vbt_header *vbt = i915->opregion.vbt;
+ const struct bdb_header *bdb;
+ int lfp_inst = 0, panel_index, opregion_panel_index;
+
+ if (devdata->child.handle == HANDLE_LFP_1)
+ lfp_inst = 1;
+ else if (devdata->child.handle == HANDLE_LFP_2)
+ lfp_inst = 2;
+
+ if (lfp_inst == 0)
+ return;
+
+ bdb = get_bdb_header(vbt);
+ panel_index = get_lfp_panel_index(i915, bdb, lfp_inst);
+
+ opregion_panel_index = intel_opregion_get_panel_type(i915);
+ /*
+ * TODO: the current implementation always use the panel index from
+ * opregion if available due to issues with old platforms.
+ * But this do not supports two panels and in SKL or newer I never saw a
+ * system were this call returns a valid value.
+ * So will change this to only use opregion up to BDW in a separated
+ * commit.
+ */
+ if (opregion_panel_index >= 0)
+ panel_index = opregion_panel_index;
+
+ if (panel_index == -1)
+ return;
+
+ parse_panel_options(i915, bdb, info, panel_index);
+ parse_power_conservation_features(i915, bdb, info, panel_index);
+ parse_driver_features_drrs_only(i915, bdb, info);
+}
+
static void parse_ddi_port(struct drm_i915_private *i915,
struct intel_bios_encoder_data *devdata)
{
@@ -2018,6 +2114,8 @@ static void parse_ddi_port(struct drm_i915_private *i915,
port_name(port), info->dp_max_link_rate);
}
+ parse_integrated_panel(i915, devdata, info);
+
info->devdata = devdata;
}
@@ -2144,9 +2242,6 @@ init_vbt_defaults(struct drm_i915_private *i915)
/* Default to having backlight */
i915->vbt.backlight.present = true;
- /* LFP panel data */
- i915->vbt.lvds_dither = 1;
-
/* SDVO panel data */
i915->vbt.sdvo_lvds_vbt_mode = NULL;
@@ -2227,13 +2322,6 @@ init_vbt_missing_defaults(struct drm_i915_private *i915)
i915->vbt.version = 155;
}
-static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt)
-{
- const void *_vbt = vbt;
-
- return _vbt + vbt->bdb_offset;
-}
-
/**
* intel_bios_is_valid_vbt - does the given buffer contain a valid VBT
* @buf: pointer to a buffer to validate
@@ -2387,12 +2475,11 @@ void intel_bios_init(struct drm_i915_private *i915)
/* Grab useful general definitions */
parse_general_features(i915, bdb);
parse_general_definitions(i915, bdb);
- parse_panel_options(i915, bdb);
+ parse_panel_type(i915, bdb);
parse_panel_dtd(i915, bdb);
parse_lfp_backlight(i915, bdb);
parse_sdvo_panel_data(i915, bdb);
parse_driver_features(i915, bdb);
- parse_power_conservation_features(i915, bdb);
parse_edp(i915, bdb);
parse_psr(i915, bdb);
parse_mipi_config(i915, bdb);
@@ -3012,3 +3099,11 @@ intel_bios_encoder_data_lookup(struct drm_i915_private *i915, enum port port)
{
return i915->vbt.ddi_port_info[port].devdata;
}
+
+enum drrs_support_type
+intel_bios_drrs_type(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ return i915->vbt.ddi_port_info[encoder->port].drrs_type;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index 4709c4d298059..bad282b64c5e6 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -266,4 +266,6 @@ bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devda
int intel_bios_encoder_dp_boost_level(const struct intel_bios_encoder_data *devdata);
int intel_bios_encoder_hdmi_boost_level(const struct intel_bios_encoder_data *devdata);
+enum drrs_support_type intel_bios_drrs_type(struct intel_encoder *encoder);
+
#endif /* _INTEL_BIOS_H_ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a54e339947c65..80a2caf4b8053 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5136,6 +5136,7 @@ intel_dp_drrs_init(struct intel_connector *connector,
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct drm_display_mode *downclock_mode = NULL;
+ enum drrs_support_type drrs_type = intel_bios_drrs_type(connector->encoder);
INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
mutex_init(&dev_priv->drrs.mutex);
@@ -5146,7 +5147,7 @@ intel_dp_drrs_init(struct intel_connector *connector,
return NULL;
}
- if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
+ if (drrs_type != SEAMLESS_DRRS_SUPPORT) {
drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
return NULL;
}
@@ -5158,7 +5159,7 @@ intel_dp_drrs_init(struct intel_connector *connector,
return NULL;
}
- dev_priv->drrs.type = dev_priv->vbt.drrs_type;
+ dev_priv->drrs.type = drrs_type;
dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index dbe24d7e73759..cd927d13250f1 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -359,6 +359,9 @@ enum vbt_gmbus_ddi {
#define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR13P5 6
#define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR20 7
+#define HANDLE_LFP_1 0x0008
+#define HANDLE_LFP_2 0x0080
+
/*
* The child device config, aka the display device data structure, provides a
* description of a port and its configuration on the platform.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8bb3661d3b2db..df096a283d52a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -650,6 +650,8 @@ struct ddi_vbt_port_info {
u8 alternate_ddc_pin;
int dp_max_link_rate; /* 0 for not limited by VBT */
+
+ enum drrs_support_type drrs_type;
};
enum psr_lines_to_wait {
@@ -668,7 +670,6 @@ struct intel_vbt_data {
/* Feature bits */
unsigned int int_tv_support:1;
- unsigned int lvds_dither:1;
unsigned int int_crt_support:1;
unsigned int lvds_use_ssc:1;
unsigned int int_lvds_support:1;
@@ -679,8 +680,6 @@ struct intel_vbt_data {
unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
enum drm_panel_orientation orientation;
- enum drrs_support_type drrs_type;
-
struct {
int rate;
int lanes;
--
2.32.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH CI 03/10] drm/i915/bios: Enable parse of two integrated panels timing data
2021-07-29 21:55 [Intel-gfx] [PATCH CI 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 02/10] drm/i915/bios: Start to support two integrated panels José Roberto de Souza
@ 2021-07-29 21:55 ` José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 04/10] drm/i915/bios: Enable parse of two integrated panels backlight data José Roberto de Souza
` (10 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: José Roberto de Souza @ 2021-07-29 21:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Continuing the conversion from single integrated VBT data to two.
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 53 +++++++++++++-------
drivers/gpu/drm/i915/display/intel_bios.h | 1 +
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 7 ++-
drivers/gpu/drm/i915/display/intel_panel.c | 7 +--
drivers/gpu/drm/i915/i915_drv.h | 3 +-
5 files changed, 48 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 9439bfe32b136..fdde8777854ee 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -289,14 +289,15 @@ parse_panel_options(struct drm_i915_private *i915,
/* Try to find integrated panel timing data */
static void
parse_lfp_panel_dtd(struct drm_i915_private *i915,
- const struct bdb_header *bdb)
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info,
+ int panel_index)
{
const struct bdb_lvds_lfp_data *lvds_lfp_data;
const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;
const struct lvds_dvo_timing *panel_dvo_timing;
const struct lvds_fp_timing *fp_timing;
struct drm_display_mode *panel_fixed_mode;
- int panel_type = i915->vbt.panel_type;
lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
if (!lvds_lfp_data)
@@ -308,7 +309,7 @@ parse_lfp_panel_dtd(struct drm_i915_private *i915,
panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data,
lvds_lfp_data_ptrs,
- panel_type);
+ panel_index);
panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
if (!panel_fixed_mode)
@@ -316,7 +317,7 @@ parse_lfp_panel_dtd(struct drm_i915_private *i915,
fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing);
- i915->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
+ info->lfp_lvds_vbt_mode = panel_fixed_mode;
drm_dbg_kms(&i915->drm,
"Found panel mode in BIOS VBT legacy lfp table:\n");
@@ -324,7 +325,7 @@ parse_lfp_panel_dtd(struct drm_i915_private *i915,
fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data,
lvds_lfp_data_ptrs,
- panel_type);
+ panel_index);
if (fp_timing) {
/* check the resolution, just to be sure */
if (fp_timing->x_res == panel_fixed_mode->hdisplay &&
@@ -339,7 +340,9 @@ parse_lfp_panel_dtd(struct drm_i915_private *i915,
static void
parse_generic_dtd(struct drm_i915_private *i915,
- const struct bdb_header *bdb)
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info,
+ int panel_index)
{
const struct bdb_generic_dtd *generic_dtd;
const struct generic_dtd_entry *dtd;
@@ -363,14 +366,14 @@ parse_generic_dtd(struct drm_i915_private *i915,
num_dtd = (get_blocksize(generic_dtd) -
sizeof(struct bdb_generic_dtd)) / generic_dtd->gdtd_size;
- if (i915->vbt.panel_type >= num_dtd) {
+ if (panel_index >= num_dtd) {
drm_err(&i915->drm,
- "Panel type %d not found in table of %d DTD's\n",
- i915->vbt.panel_type, num_dtd);
+ "Panel index %d not found in table of %d DTD's\n",
+ panel_index, num_dtd);
return;
}
- dtd = &generic_dtd->dtd[i915->vbt.panel_type];
+ dtd = &generic_dtd->dtd[panel_index];
panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
if (!panel_fixed_mode)
@@ -413,12 +416,14 @@ parse_generic_dtd(struct drm_i915_private *i915,
"Found panel mode in BIOS VBT generic dtd table:\n");
drm_mode_debug_printmodeline(panel_fixed_mode);
- i915->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
+ info->lfp_lvds_vbt_mode = panel_fixed_mode;
}
static void
parse_panel_dtd(struct drm_i915_private *i915,
- const struct bdb_header *bdb)
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info,
+ int panel_index)
{
/*
* Older VBTs provided provided DTD information for internal displays
@@ -429,9 +434,9 @@ parse_panel_dtd(struct drm_i915_private *i915,
* back to trying the old LFP block if that fails.
*/
if (bdb->version >= 229)
- parse_generic_dtd(i915, bdb);
- if (!i915->vbt.lfp_lvds_vbt_mode)
- parse_lfp_panel_dtd(i915, bdb);
+ parse_generic_dtd(i915, bdb, info, panel_index);
+ if (!info->lfp_lvds_vbt_mode)
+ parse_lfp_panel_dtd(i915, bdb, info, panel_index);
}
static void
@@ -1981,6 +1986,7 @@ static void parse_integrated_panel(struct drm_i915_private *i915,
parse_panel_options(i915, bdb, info, panel_index);
parse_power_conservation_features(i915, bdb, info, panel_index);
parse_driver_features_drrs_only(i915, bdb, info);
+ parse_panel_dtd(i915, bdb, info, panel_index);
}
static void parse_ddi_port(struct drm_i915_private *i915,
@@ -2476,7 +2482,6 @@ void intel_bios_init(struct drm_i915_private *i915)
parse_general_features(i915, bdb);
parse_general_definitions(i915, bdb);
parse_panel_type(i915, bdb);
- parse_panel_dtd(i915, bdb);
parse_lfp_backlight(i915, bdb);
parse_sdvo_panel_data(i915, bdb);
parse_driver_features(i915, bdb);
@@ -2509,6 +2514,7 @@ void intel_bios_init(struct drm_i915_private *i915)
void intel_bios_driver_remove(struct drm_i915_private *i915)
{
struct intel_bios_encoder_data *devdata, *n;
+ int i;
list_for_each_entry_safe(devdata, n, &i915->vbt.display_devices, node) {
list_del(&devdata->node);
@@ -2516,10 +2522,13 @@ void intel_bios_driver_remove(struct drm_i915_private *i915)
kfree(devdata);
}
+ for (i = 0; i < I915_MAX_PORTS; i++) {
+ kfree(i915->vbt.ddi_port_info[i].lfp_lvds_vbt_mode);
+ i915->vbt.ddi_port_info[i].lfp_lvds_vbt_mode = NULL;
+ }
+
kfree(i915->vbt.sdvo_lvds_vbt_mode);
i915->vbt.sdvo_lvds_vbt_mode = NULL;
- kfree(i915->vbt.lfp_lvds_vbt_mode);
- i915->vbt.lfp_lvds_vbt_mode = NULL;
kfree(i915->vbt.dsi.data);
i915->vbt.dsi.data = NULL;
kfree(i915->vbt.dsi.pps);
@@ -3107,3 +3116,11 @@ intel_bios_drrs_type(struct intel_encoder *encoder)
return i915->vbt.ddi_port_info[encoder->port].drrs_type;
}
+
+const struct drm_display_mode *
+intel_bios_lfp_lvds_info(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ return i915->vbt.ddi_port_info[encoder->port].lfp_lvds_vbt_mode;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index bad282b64c5e6..f133c51c155cd 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -267,5 +267,6 @@ int intel_bios_encoder_dp_boost_level(const struct intel_bios_encoder_data *devd
int intel_bios_encoder_hdmi_boost_level(const struct intel_bios_encoder_data *devdata);
enum drrs_support_type intel_bios_drrs_type(struct intel_encoder *encoder);
+const struct drm_display_mode *intel_bios_lfp_lvds_info(struct intel_encoder *encoder);
#endif /* _INTEL_BIOS_H_ */
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index c2a2cd1f84dc5..2218de0773bf0 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -729,10 +729,15 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
struct drm_i915_private *dev_priv = to_i915(dev);
struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
- struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
+ const struct drm_display_mode *mode = intel_bios_lfp_lvds_info(&intel_dsi->base);
u16 burst_mode_ratio;
enum port port;
+ if (!mode) {
+ drm_dbg_kms(&dev_priv->drm, "lfp_lvds_vbt_mode not set\n");
+ return false;
+ }
+
drm_dbg_kms(&dev_priv->drm, "\n");
intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 7d7a60b4d2de7..a88e30c966fe7 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -153,12 +153,13 @@ intel_panel_vbt_fixed_mode(struct intel_connector *connector)
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct drm_display_info *info = &connector->base.display_info;
struct drm_display_mode *fixed_mode;
+ const struct drm_display_mode *lfp_lvds_vbt_mode;
- if (!dev_priv->vbt.lfp_lvds_vbt_mode)
+ lfp_lvds_vbt_mode = intel_bios_lfp_lvds_info(connector->encoder);
+ if (!lfp_lvds_vbt_mode)
return NULL;
- fixed_mode = drm_mode_duplicate(&dev_priv->drm,
- dev_priv->vbt.lfp_lvds_vbt_mode);
+ fixed_mode = drm_mode_duplicate(&dev_priv->drm, lfp_lvds_vbt_mode);
if (!fixed_mode)
return NULL;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index df096a283d52a..ef3a86e4aba02 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -652,6 +652,8 @@ struct ddi_vbt_port_info {
int dp_max_link_rate; /* 0 for not limited by VBT */
enum drrs_support_type drrs_type;
+
+ struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
};
enum psr_lines_to_wait {
@@ -665,7 +667,6 @@ struct intel_vbt_data {
/* bdb version */
u16 version;
- struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
/* Feature bits */
--
2.32.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH CI 04/10] drm/i915/bios: Enable parse of two integrated panels backlight data
2021-07-29 21:55 [Intel-gfx] [PATCH CI 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 02/10] drm/i915/bios: Start to support two integrated panels José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 03/10] drm/i915/bios: Enable parse of two integrated panels timing data José Roberto de Souza
@ 2021-07-29 21:55 ` José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 05/10] drm/i915/bios: Enable parse of two integrated panels eDP data José Roberto de Souza
` (9 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: José Roberto de Souza @ 2021-07-29 21:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Continuing the conversion from single integrated VBT data to two, now
handling backlight data.
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 59 +++++++++++--------
drivers/gpu/drm/i915/display/intel_bios.h | 1 +
.../drm/i915/display/intel_dp_aux_backlight.c | 11 ++--
.../i915/display/intel_dsi_dcs_backlight.c | 5 +-
drivers/gpu/drm/i915/display/intel_panel.c | 32 ++++++----
drivers/gpu/drm/i915/display/intel_pps.c | 8 ++-
drivers/gpu/drm/i915/i915_drv.h | 18 +++---
7 files changed, 83 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index fdde8777854ee..de461cc9fead9 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -441,11 +441,12 @@ parse_panel_dtd(struct drm_i915_private *i915,
static void
parse_lfp_backlight(struct drm_i915_private *i915,
- const struct bdb_header *bdb)
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info,
+ int panel_index)
{
const struct bdb_lfp_backlight_data *backlight_data;
const struct lfp_backlight_data_entry *entry;
- int panel_type = i915->vbt.panel_type;
u16 level;
backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
@@ -459,38 +460,38 @@ parse_lfp_backlight(struct drm_i915_private *i915,
return;
}
- entry = &backlight_data->data[panel_type];
+ entry = &backlight_data->data[panel_index];
- i915->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;
- if (!i915->vbt.backlight.present) {
+ info->backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;
+ if (!info->backlight.present) {
drm_dbg_kms(&i915->drm,
"PWM backlight not present in VBT (type %u)\n",
entry->type);
return;
}
- i915->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
+ info->backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
if (bdb->version >= 191 &&
get_blocksize(backlight_data) >= sizeof(*backlight_data)) {
const struct lfp_backlight_control_method *method;
- method = &backlight_data->backlight_control[panel_type];
- i915->vbt.backlight.type = method->type;
- i915->vbt.backlight.controller = method->controller;
+ method = &backlight_data->backlight_control[panel_index];
+ info->backlight.type = method->type;
+ info->backlight.controller = method->controller;
}
- i915->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
- i915->vbt.backlight.active_low_pwm = entry->active_low_pwm;
+ info->backlight.pwm_freq_hz = entry->pwm_freq_hz;
+ info->backlight.active_low_pwm = entry->active_low_pwm;
if (bdb->version >= 234) {
u16 min_level;
bool scale;
- level = backlight_data->brightness_level[panel_type].level;
- min_level = backlight_data->brightness_min_level[panel_type].level;
+ level = backlight_data->brightness_level[panel_index].level;
+ min_level = backlight_data->brightness_min_level[panel_index].level;
if (bdb->version >= 236)
- scale = backlight_data->brightness_precision_bits[panel_type] == 16;
+ scale = backlight_data->brightness_precision_bits[panel_index] == 16;
else
scale = level > 255;
@@ -501,20 +502,20 @@ parse_lfp_backlight(struct drm_i915_private *i915,
drm_warn(&i915->drm, "Brightness min level > 255\n");
level = 255;
}
- i915->vbt.backlight.min_brightness = min_level;
+ info->backlight.min_brightness = min_level;
} else {
- level = backlight_data->level[panel_type];
- i915->vbt.backlight.min_brightness = entry->min_brightness;
+ level = backlight_data->level[panel_index];
+ info->backlight.min_brightness = entry->min_brightness;
}
drm_dbg_kms(&i915->drm,
"VBT backlight PWM modulation frequency %u Hz, "
"active %s, min brightness %u, level %u, controller %u\n",
- i915->vbt.backlight.pwm_freq_hz,
- i915->vbt.backlight.active_low_pwm ? "low" : "high",
- i915->vbt.backlight.min_brightness,
+ info->backlight.pwm_freq_hz,
+ info->backlight.active_low_pwm ? "low" : "high",
+ info->backlight.min_brightness,
level,
- i915->vbt.backlight.controller);
+ info->backlight.controller);
}
/* Try to find sdvo panel data */
@@ -1987,6 +1988,7 @@ static void parse_integrated_panel(struct drm_i915_private *i915,
parse_power_conservation_features(i915, bdb, info, panel_index);
parse_driver_features_drrs_only(i915, bdb, info);
parse_panel_dtd(i915, bdb, info, panel_index);
+ parse_lfp_backlight(i915, bdb, info, panel_index);
}
static void parse_ddi_port(struct drm_i915_private *i915,
@@ -2120,6 +2122,9 @@ static void parse_ddi_port(struct drm_i915_private *i915,
port_name(port), info->dp_max_link_rate);
}
+ /* Default to having backlight */
+ info->backlight.present = true;
+
parse_integrated_panel(i915, devdata, info);
info->devdata = devdata;
@@ -2245,9 +2250,6 @@ init_vbt_defaults(struct drm_i915_private *i915)
{
i915->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC;
- /* Default to having backlight */
- i915->vbt.backlight.present = true;
-
/* SDVO panel data */
i915->vbt.sdvo_lvds_vbt_mode = NULL;
@@ -2482,7 +2484,6 @@ void intel_bios_init(struct drm_i915_private *i915)
parse_general_features(i915, bdb);
parse_general_definitions(i915, bdb);
parse_panel_type(i915, bdb);
- parse_lfp_backlight(i915, bdb);
parse_sdvo_panel_data(i915, bdb);
parse_driver_features(i915, bdb);
parse_edp(i915, bdb);
@@ -3124,3 +3125,11 @@ intel_bios_lfp_lvds_info(struct intel_encoder *encoder)
return i915->vbt.ddi_port_info[encoder->port].lfp_lvds_vbt_mode;
}
+
+const struct vbt_backlight_info *
+intel_bios_backlight_info(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ return &i915->vbt.ddi_port_info[encoder->port].backlight;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index f133c51c155cd..5b6167c97a8d9 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -268,5 +268,6 @@ int intel_bios_encoder_hdmi_boost_level(const struct intel_bios_encoder_data *de
enum drrs_support_type intel_bios_drrs_type(struct intel_encoder *encoder);
const struct drm_display_mode *intel_bios_lfp_lvds_info(struct intel_encoder *encoder);
+const struct vbt_backlight_info *intel_bios_backlight_info(struct intel_encoder *encoder);
#endif /* _INTEL_BIOS_H_ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 6ac568617ef37..401a9d9533158 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -310,13 +310,14 @@ static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector,
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_panel *panel = &connector->panel;
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ const struct vbt_backlight_info *backlight_info;
u16 current_level;
u8 current_mode;
int ret;
+ backlight_info = intel_bios_backlight_info(connector->encoder);
ret = drm_edp_backlight_init(&intel_dp->aux, &panel->backlight.edp.vesa.info,
- i915->vbt.backlight.pwm_freq_hz, intel_dp->edp_dpcd,
+ backlight_info->pwm_freq_hz, intel_dp->edp_dpcd,
¤t_level, ¤t_mode);
if (ret < 0)
return ret;
@@ -383,7 +384,9 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector)
struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
bool try_intel_interface = false, try_vesa_interface = false;
+ const struct vbt_backlight_info *backlight_info;
+ backlight_info = intel_bios_backlight_info(connector->encoder);
/* Check the VBT and user's module parameters to figure out which
* interfaces to probe
*/
@@ -391,7 +394,7 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector)
case INTEL_DP_AUX_BACKLIGHT_OFF:
return -ENODEV;
case INTEL_DP_AUX_BACKLIGHT_AUTO:
- switch (i915->vbt.backlight.type) {
+ switch (backlight_info->type) {
case INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE:
try_vesa_interface = true;
break;
@@ -403,7 +406,7 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector)
}
break;
case INTEL_DP_AUX_BACKLIGHT_ON:
- if (i915->vbt.backlight.type != INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE)
+ if (backlight_info->type != INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE)
try_intel_interface = true;
try_vesa_interface = true;
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
index 584c14c4cbd0e..4dbd0c6754af9 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
@@ -166,11 +166,12 @@ static const struct intel_panel_bl_funcs dcs_bl_funcs = {
int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector)
{
struct drm_device *dev = intel_connector->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
struct intel_panel *panel = &intel_connector->panel;
+ const struct vbt_backlight_info *backlight_info;
- if (dev_priv->vbt.backlight.type != INTEL_BACKLIGHT_DSI_DCS)
+ backlight_info = intel_bios_backlight_info(encoder);
+ if (backlight_info->type != INTEL_BACKLIGHT_DSI_DCS)
return -ENODEV;
if (drm_WARN_ON(dev, encoder->type != INTEL_OUTPUT_DSI))
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index a88e30c966fe7..9c892476d8621 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -1596,9 +1596,14 @@ static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * mul);
}
-static u16 get_vbt_pwm_freq(struct drm_i915_private *dev_priv)
+static u16 get_vbt_pwm_freq(struct intel_connector *connector)
{
- u16 pwm_freq_hz = dev_priv->vbt.backlight.pwm_freq_hz;
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ const struct vbt_backlight_info *backlight_info;
+ u16 pwm_freq_hz;
+
+ backlight_info = intel_bios_backlight_info(connector->encoder);
+ pwm_freq_hz = backlight_info->pwm_freq_hz;
if (pwm_freq_hz) {
drm_dbg_kms(&dev_priv->drm,
@@ -1618,7 +1623,7 @@ static u32 get_backlight_max_vbt(struct intel_connector *connector)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_panel *panel = &connector->panel;
- u16 pwm_freq_hz = get_vbt_pwm_freq(dev_priv);
+ u16 pwm_freq_hz = get_vbt_pwm_freq(connector);
u32 pwm;
if (!panel->backlight.pwm_funcs->hz_to_pwm) {
@@ -1643,11 +1648,14 @@ static u32 get_backlight_max_vbt(struct intel_connector *connector)
static u32 get_backlight_min_vbt(struct intel_connector *connector)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ const struct vbt_backlight_info *backlight_info;
struct intel_panel *panel = &connector->panel;
int min;
drm_WARN_ON(&dev_priv->drm, panel->backlight.pwm_level_max == 0);
+ backlight_info = intel_bios_backlight_info(connector->encoder);
+
/*
* XXX: If the vbt value is 255, it makes min equal to max, which leads
* to problems. There are such machines out there. Either our
@@ -1655,11 +1663,11 @@ static u32 get_backlight_min_vbt(struct intel_connector *connector)
* against this by letting the minimum be at most (arbitrarily chosen)
* 25% of the max.
*/
- min = clamp_t(int, dev_priv->vbt.backlight.min_brightness, 0, 64);
- if (min != dev_priv->vbt.backlight.min_brightness) {
+ min = clamp_t(int, backlight_info->min_brightness, 0, 64);
+ if (min != backlight_info->min_brightness) {
drm_dbg_kms(&dev_priv->drm,
"clamping VBT min backlight %d/255 to %d/255\n",
- dev_priv->vbt.backlight.min_brightness, min);
+ backlight_info->min_brightness, min);
}
/* vbt value is a coefficient in range [0..255] */
@@ -1845,10 +1853,12 @@ static int
bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ const struct vbt_backlight_info *backlight_info;
struct intel_panel *panel = &connector->panel;
u32 pwm_ctl, val;
- panel->backlight.controller = dev_priv->vbt.backlight.controller;
+ backlight_info = intel_bios_backlight_info(connector->encoder);
+ panel->backlight.controller = backlight_info->controller;
pwm_ctl = intel_de_read(dev_priv,
BXT_BLC_PWM_CTL(panel->backlight.controller));
@@ -1950,11 +1960,11 @@ static int ext_pwm_setup_backlight(struct intel_connector *connector,
drm_dbg_kms(&dev_priv->drm, "PWM already enabled at freq %ld, VBT freq %d, level %d\n",
NSEC_PER_SEC / (unsigned long)panel->backlight.pwm_state.period,
- get_vbt_pwm_freq(dev_priv), level);
+ get_vbt_pwm_freq(connector), level);
} else {
/* Set period from VBT frequency, leave other settings at 0. */
panel->backlight.pwm_state.period =
- NSEC_PER_SEC / get_vbt_pwm_freq(dev_priv);
+ NSEC_PER_SEC / get_vbt_pwm_freq(connector);
}
drm_info(&dev_priv->drm, "Using %s PWM for LCD backlight control\n",
@@ -2037,10 +2047,12 @@ int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe)
{
struct drm_i915_private *dev_priv = to_i915(connector->dev);
struct intel_connector *intel_connector = to_intel_connector(connector);
+ const struct vbt_backlight_info *backlight_info;
struct intel_panel *panel = &intel_connector->panel;
int ret;
- if (!dev_priv->vbt.backlight.present) {
+ backlight_info = intel_bios_backlight_info(intel_connector->encoder);
+ if (!backlight_info->present) {
if (dev_priv->quirks & QUIRK_BACKLIGHT_PRESENT) {
drm_dbg_kms(&dev_priv->drm,
"no backlight present per VBT, but present per quirk\n");
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index a36ec4a818ff5..96894d70a92c1 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -207,7 +207,13 @@ static int
bxt_power_sequencer_idx(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- int backlight_controller = dev_priv->vbt.backlight.controller;
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = &dig_port->base;
+ const struct vbt_backlight_info *backlight_info;
+ int backlight_controller;
+
+ backlight_info = intel_bios_backlight_info(encoder);
+ backlight_controller = backlight_info->controller;
lockdep_assert_held(&dev_priv->pps_mutex);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ef3a86e4aba02..699d0e4603a38 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -654,6 +654,15 @@ struct ddi_vbt_port_info {
enum drrs_support_type drrs_type;
struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
+
+ struct vbt_backlight_info {
+ u16 pwm_freq_hz;
+ bool present;
+ bool active_low_pwm;
+ u8 min_brightness; /* min_brightness/255 of max */
+ u8 controller; /* brightness controller number */
+ enum intel_backlight_type type;
+ } backlight;
};
enum psr_lines_to_wait {
@@ -704,15 +713,6 @@ struct intel_vbt_data {
int psr2_tp2_tp3_wakeup_time_us;
} psr;
- struct {
- u16 pwm_freq_hz;
- bool present;
- bool active_low_pwm;
- u8 min_brightness; /* min_brightness/255 of max */
- u8 controller; /* brightness controller number */
- enum intel_backlight_type type;
- } backlight;
-
/* MIPI DSI */
struct {
u16 panel_id;
--
2.32.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH CI 05/10] drm/i915/bios: Enable parse of two integrated panels eDP data
2021-07-29 21:55 [Intel-gfx] [PATCH CI 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() José Roberto de Souza
` (2 preceding siblings ...)
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 04/10] drm/i915/bios: Enable parse of two integrated panels backlight data José Roberto de Souza
@ 2021-07-29 21:55 ` José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 06/10] drm/i915/bios: Enable parse of two integrated panels PSR data José Roberto de Souza
` (8 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: José Roberto de Souza @ 2021-07-29 21:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Continuing the conversion from single integrated VBT data to two, now
handling eDP data.
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/g4x_dp.c | 9 ++-
drivers/gpu/drm/i915/display/intel_bios.c | 62 ++++++++-------
drivers/gpu/drm/i915/display/intel_bios.h | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 9 ++-
.../drm/i915/display/intel_ddi_buf_trans.c | 77 ++++++++++---------
drivers/gpu/drm/i915/display/intel_dp.c | 7 +-
drivers/gpu/drm/i915/display/intel_pps.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 24 +++---
8 files changed, 104 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index de0f358184aa3..273bc5295ae33 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -340,6 +340,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
u32 tmp, flags = 0;
enum port port = encoder->port;
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
if (encoder->type == INTEL_OUTPUT_EDP)
pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
@@ -396,8 +397,8 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
intel_dotclock_calculate(pipe_config->port_clock,
&pipe_config->dp_m_n);
- if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
- pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
+ if (intel_dp_is_edp(intel_dp) && vbt_edp_info->bpp &&
+ pipe_config->pipe_bpp > vbt_edp_info->bpp) {
/*
* This is a big fat ugly hack.
*
@@ -413,8 +414,8 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
*/
drm_dbg_kms(&dev_priv->drm,
"pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
- pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
- dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
+ pipe_config->pipe_bpp, vbt_edp_info->bpp);
+ vbt_edp_info->bpp = pipe_config->pipe_bpp;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index de461cc9fead9..dac81a5ebdaa0 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -786,45 +786,45 @@ parse_power_conservation_features(struct drm_i915_private *i915,
info->drrs_type = DRRS_NOT_SUPPORTED;
if (bdb->version >= 232)
- i915->vbt.edp.hobl = power->hobl & BIT(panel_index);
+ info->edp.hobl = power->hobl & BIT(panel_index);
}
static void
-parse_edp(struct drm_i915_private *i915, const struct bdb_header *bdb)
+parse_edp(struct drm_i915_private *i915, const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info, int panel_index)
{
const struct bdb_edp *edp;
const struct edp_power_seq *edp_pps;
const struct edp_fast_link_params *edp_link_params;
- int panel_type = i915->vbt.panel_type;
edp = find_section(bdb, BDB_EDP);
if (!edp)
return;
- switch ((edp->color_depth >> (panel_type * 2)) & 3) {
+ switch ((edp->color_depth >> (panel_index * 2)) & 3) {
case EDP_18BPP:
- i915->vbt.edp.bpp = 18;
+ info->edp.bpp = 18;
break;
case EDP_24BPP:
- i915->vbt.edp.bpp = 24;
+ info->edp.bpp = 24;
break;
case EDP_30BPP:
- i915->vbt.edp.bpp = 30;
+ info->edp.bpp = 30;
break;
}
/* Get the eDP sequencing and link info */
- edp_pps = &edp->power_seqs[panel_type];
- edp_link_params = &edp->fast_link_params[panel_type];
+ edp_pps = &edp->power_seqs[panel_index];
+ edp_link_params = &edp->fast_link_params[panel_index];
- i915->vbt.edp.pps = *edp_pps;
+ info->edp.pps = *edp_pps;
switch (edp_link_params->rate) {
case EDP_RATE_1_62:
- i915->vbt.edp.rate = DP_LINK_BW_1_62;
+ info->edp.rate = DP_LINK_BW_1_62;
break;
case EDP_RATE_2_7:
- i915->vbt.edp.rate = DP_LINK_BW_2_7;
+ info->edp.rate = DP_LINK_BW_2_7;
break;
default:
drm_dbg_kms(&i915->drm,
@@ -835,13 +835,13 @@ parse_edp(struct drm_i915_private *i915, const struct bdb_header *bdb)
switch (edp_link_params->lanes) {
case EDP_LANE_1:
- i915->vbt.edp.lanes = 1;
+ info->edp.lanes = 1;
break;
case EDP_LANE_2:
- i915->vbt.edp.lanes = 2;
+ info->edp.lanes = 2;
break;
case EDP_LANE_4:
- i915->vbt.edp.lanes = 4;
+ info->edp.lanes = 4;
break;
default:
drm_dbg_kms(&i915->drm,
@@ -852,16 +852,16 @@ parse_edp(struct drm_i915_private *i915, const struct bdb_header *bdb)
switch (edp_link_params->preemphasis) {
case EDP_PREEMPHASIS_NONE:
- i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0;
+ info->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0;
break;
case EDP_PREEMPHASIS_3_5dB:
- i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1;
+ info->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1;
break;
case EDP_PREEMPHASIS_6dB:
- i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2;
+ info->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2;
break;
case EDP_PREEMPHASIS_9_5dB:
- i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3;
+ info->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3;
break;
default:
drm_dbg_kms(&i915->drm,
@@ -872,16 +872,16 @@ parse_edp(struct drm_i915_private *i915, const struct bdb_header *bdb)
switch (edp_link_params->vswing) {
case EDP_VSWING_0_4V:
- i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
+ info->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
break;
case EDP_VSWING_0_6V:
- i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
+ info->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
break;
case EDP_VSWING_0_8V:
- i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
+ info->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
break;
case EDP_VSWING_1_2V:
- i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
+ info->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
break;
default:
drm_dbg_kms(&i915->drm,
@@ -895,11 +895,11 @@ parse_edp(struct drm_i915_private *i915, const struct bdb_header *bdb)
/* Don't read from VBT if module parameter has valid value*/
if (i915->params.edp_vswing) {
- i915->vbt.edp.low_vswing =
+ info->edp.low_vswing =
i915->params.edp_vswing == 1;
} else {
- vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF;
- i915->vbt.edp.low_vswing = vswing == 0;
+ vswing = (edp->edp_vswing_preemph >> (panel_index * 4)) & 0xF;
+ info->edp.low_vswing = vswing == 0;
}
}
}
@@ -1989,6 +1989,7 @@ static void parse_integrated_panel(struct drm_i915_private *i915,
parse_driver_features_drrs_only(i915, bdb, info);
parse_panel_dtd(i915, bdb, info, panel_index);
parse_lfp_backlight(i915, bdb, info, panel_index);
+ parse_edp(i915, bdb, info, panel_index);
}
static void parse_ddi_port(struct drm_i915_private *i915,
@@ -2486,7 +2487,6 @@ void intel_bios_init(struct drm_i915_private *i915)
parse_panel_type(i915, bdb);
parse_sdvo_panel_data(i915, bdb);
parse_driver_features(i915, bdb);
- parse_edp(i915, bdb);
parse_psr(i915, bdb);
parse_mipi_config(i915, bdb);
parse_mipi_sequence(i915, bdb);
@@ -3133,3 +3133,11 @@ intel_bios_backlight_info(struct intel_encoder *encoder)
return &i915->vbt.ddi_port_info[encoder->port].backlight;
}
+
+struct vbt_edp_info *
+intel_bios_edp_info(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ return &i915->vbt.ddi_port_info[encoder->port].edp;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index 5b6167c97a8d9..8fd9b52f921f7 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -269,5 +269,6 @@ int intel_bios_encoder_hdmi_boost_level(const struct intel_bios_encoder_data *de
enum drrs_support_type intel_bios_drrs_type(struct intel_encoder *encoder);
const struct drm_display_mode *intel_bios_lfp_lvds_info(struct intel_encoder *encoder);
const struct vbt_backlight_info *intel_bios_backlight_info(struct intel_encoder *encoder);
+struct vbt_edp_info *intel_bios_edp_info(struct intel_encoder *encoder);
#endif /* _INTEL_BIOS_H_ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 85856d0406374..ec2b8801768f5 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3783,6 +3783,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
/* XXX: DSI transcoder paranoia */
@@ -3807,8 +3808,8 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
pipe_config->has_audio =
intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
- if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
- pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
+ if (encoder->type == INTEL_OUTPUT_EDP && vbt_edp_info->bpp &&
+ pipe_config->pipe_bpp > vbt_edp_info->bpp) {
/*
* This is a big fat ugly hack.
*
@@ -3824,8 +3825,8 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
*/
drm_dbg_kms(&dev_priv->drm,
"pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
- pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
- dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
+ pipe_config->pipe_bpp, vbt_edp_info->bpp);
+ vbt_edp_info->bpp = pipe_config->pipe_bpp;
}
if (!pipe_config->bigjoiner_slave)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 923c962e86a39..38d3e444027f0 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1193,14 +1193,14 @@ bdw_get_buf_trans(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
return intel_get_buf_trans(&bdw_ddi_translations_fdi, n_entries);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
return intel_get_buf_trans(&bdw_ddi_translations_hdmi, n_entries);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
- i915->vbt.edp.low_vswing)
+ vbt_edp_info->low_vswing)
return intel_get_buf_trans(&bdw_ddi_translations_edp, n_entries);
else
return intel_get_buf_trans(&bdw_ddi_translations_dp, n_entries);
@@ -1230,12 +1230,12 @@ skl_y_get_buf_trans(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
return intel_get_buf_trans(&skl_y_ddi_translations_hdmi, n_entries);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
- i915->vbt.edp.low_vswing)
+ vbt_edp_info->low_vswing)
return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_edp, n_entries);
else
return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_dp, n_entries);
@@ -1246,12 +1246,12 @@ skl_u_get_buf_trans(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
- i915->vbt.edp.low_vswing)
+ vbt_edp_info->low_vswing)
return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_edp, n_entries);
else
return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_dp, n_entries);
@@ -1262,12 +1262,12 @@ skl_get_buf_trans(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
- i915->vbt.edp.low_vswing)
+ vbt_edp_info->low_vswing)
return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_edp, n_entries);
else
return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_dp, n_entries);
@@ -1278,12 +1278,12 @@ kbl_y_get_buf_trans(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
return intel_get_buf_trans(&skl_y_ddi_translations_hdmi, n_entries);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
- i915->vbt.edp.low_vswing)
+ vbt_edp_info->low_vswing)
return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_edp, n_entries);
else
return _skl_get_buf_trans_dp(encoder, &kbl_y_ddi_translations_dp, n_entries);
@@ -1294,12 +1294,12 @@ kbl_u_get_buf_trans(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
- i915->vbt.edp.low_vswing)
+ vbt_edp_info->low_vswing)
return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_edp, n_entries);
else
return _skl_get_buf_trans_dp(encoder, &kbl_u_ddi_translations_dp, n_entries);
@@ -1310,12 +1310,12 @@ kbl_get_buf_trans(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
- i915->vbt.edp.low_vswing)
+ vbt_edp_info->low_vswing)
return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_edp, n_entries);
else
return _skl_get_buf_trans_dp(encoder, &kbl_ddi_translations_dp, n_entries);
@@ -1326,12 +1326,12 @@ bxt_get_buf_trans(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
return intel_get_buf_trans(&bxt_ddi_translations_hdmi, n_entries);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
- i915->vbt.edp.low_vswing)
+ vbt_edp_info->low_vswing)
return intel_get_buf_trans(&bxt_ddi_translations_edp, n_entries);
else
return intel_get_buf_trans(&bxt_ddi_translations_dp, n_entries);
@@ -1384,10 +1384,11 @@ cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
static const struct intel_ddi_buf_trans *
cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
{
+ const struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
- if (dev_priv->vbt.edp.low_vswing) {
+ if (vbt_edp_info->low_vswing) {
if (voltage == VOLTAGE_INFO_0_85V) {
return intel_get_buf_trans(&cnl_ddi_translations_edp_0_85V,
n_entries);
@@ -1433,12 +1434,12 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ const struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
if (crtc_state->port_clock > 540000) {
return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3,
n_entries);
- } else if (dev_priv->vbt.edp.low_vswing) {
+ } else if (vbt_edp_info->low_vswing) {
return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2,
n_entries);
}
@@ -1500,12 +1501,12 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ const struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
- dev_priv->vbt.edp.low_vswing)
+ vbt_edp_info->low_vswing)
return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
else
return intel_get_buf_trans(&ehl_combo_phy_ddi_translations_dp, n_entries);
@@ -1527,12 +1528,12 @@ jsl_get_combo_buf_trans(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ const struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
- dev_priv->vbt.edp.low_vswing)
+ vbt_edp_info->low_vswing)
return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
else
return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, n_entries);
@@ -1564,16 +1565,16 @@ tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ const struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
if (crtc_state->port_clock > 540000) {
return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3,
n_entries);
- } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
+ } else if (vbt_edp_info->hobl && !intel_dp->hobl_failed) {
return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl,
n_entries);
- } else if (dev_priv->vbt.edp.low_vswing) {
+ } else if (vbt_edp_info->low_vswing) {
return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2,
n_entries);
}
@@ -1612,16 +1613,16 @@ dg1_get_combo_buf_trans_edp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ const struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
if (crtc_state->port_clock > 540000)
return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3,
n_entries);
- else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed)
+ else if (vbt_edp_info->hobl && !intel_dp->hobl_failed)
return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl,
n_entries);
- else if (dev_priv->vbt.edp.low_vswing)
+ else if (vbt_edp_info->low_vswing)
return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2,
n_entries);
else
@@ -1657,16 +1658,16 @@ rkl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ const struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
if (crtc_state->port_clock > 540000) {
return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3,
n_entries);
- } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
+ } else if (vbt_edp_info->hobl && !intel_dp->hobl_failed) {
return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl,
n_entries);
- } else if (dev_priv->vbt.edp.low_vswing) {
+ } else if (vbt_edp_info->low_vswing) {
return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2,
n_entries);
}
@@ -1703,14 +1704,14 @@ adls_get_combo_buf_trans_edp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
if (crtc_state->port_clock > 540000)
return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr3, n_entries);
- else if (i915->vbt.edp.hobl && !intel_dp->hobl_failed)
+ else if (vbt_edp_info->hobl && !intel_dp->hobl_failed)
return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, n_entries);
- else if (i915->vbt.edp.low_vswing)
+ else if (vbt_edp_info->low_vswing)
return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr2, n_entries);
else
return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
@@ -1745,16 +1746,16 @@ adlp_get_combo_buf_trans_edp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ const struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
if (crtc_state->port_clock > 540000) {
return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_edp_hbr3,
n_entries);
- } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
+ } else if (vbt_edp_info->hobl && !intel_dp->hobl_failed) {
return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl,
n_entries);
- } else if (dev_priv->vbt.edp.low_vswing) {
+ } else if (vbt_edp_info->low_vswing) {
return intel_get_buf_trans(&adlp_combo_phy_ddi_translations_edp_up_to_hbr2,
n_entries);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 80a2caf4b8053..f96cbbab15db0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1009,6 +1009,7 @@ static int intel_dp_max_bpp(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_connector *intel_connector = intel_dp->attached_connector;
+ struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(intel_connector->encoder);
int bpp, bpc;
bpc = crtc_state->pipe_bpp / 3;
@@ -1027,11 +1028,11 @@ static int intel_dp_max_bpp(struct intel_dp *intel_dp,
if (intel_dp_is_edp(intel_dp)) {
/* Get bpp from vbt only for panels that dont have bpp in edid */
if (intel_connector->base.display_info.bpc == 0 &&
- dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
+ vbt_edp_info->bpp && vbt_edp_info->bpp < bpp) {
drm_dbg_kms(&dev_priv->drm,
"clamping bpp for eDP panel to BIOS-provided %i\n",
- dev_priv->vbt.edp.bpp);
- bpp = dev_priv->vbt.edp.bpp;
+ vbt_edp_info->bpp);
+ bpp = vbt_edp_info->bpp;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 96894d70a92c1..f4c15a1f31d15 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1161,6 +1161,8 @@ intel_pps_verify_state(struct intel_dp *intel_dp)
static void pps_init_delays(struct intel_dp *intel_dp)
{
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ const struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct edp_power_seq cur, vbt, spec,
*final = &intel_dp->pps.pps_delays;
@@ -1175,7 +1177,7 @@ static void pps_init_delays(struct intel_dp *intel_dp)
intel_pps_dump_state("cur", &cur);
- vbt = dev_priv->vbt.edp.pps;
+ vbt = vbt_edp_info->pps;
/* On Toshiba Satellite P50-C-18C system the VBT T12 delay
* of 500ms appears to be too short. Ocassionally the panel
* just fails to power back on. Increasing the delay to 800ms
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 699d0e4603a38..5b84f2129c2bf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -663,6 +663,18 @@ struct ddi_vbt_port_info {
u8 controller; /* brightness controller number */
enum intel_backlight_type type;
} backlight;
+
+ struct vbt_edp_info {
+ int rate;
+ int lanes;
+ int preemphasis;
+ int vswing;
+ bool low_vswing;
+ bool initialized;
+ int bpp;
+ struct edp_power_seq pps;
+ bool hobl;
+ } edp;
};
enum psr_lines_to_wait {
@@ -690,18 +702,6 @@ struct intel_vbt_data {
unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
enum drm_panel_orientation orientation;
- struct {
- int rate;
- int lanes;
- int preemphasis;
- int vswing;
- bool low_vswing;
- bool initialized;
- int bpp;
- struct edp_power_seq pps;
- bool hobl;
- } edp;
-
struct {
bool enable;
bool full_link;
--
2.32.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH CI 06/10] drm/i915/bios: Enable parse of two integrated panels PSR data
2021-07-29 21:55 [Intel-gfx] [PATCH CI 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() José Roberto de Souza
` (3 preceding siblings ...)
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 05/10] drm/i915/bios: Enable parse of two integrated panels eDP data José Roberto de Souza
@ 2021-07-29 21:55 ` José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 07/10] drm/i915/bios: Enable parse of two DSI panels data José Roberto de Souza
` (7 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: José Roberto de Souza @ 2021-07-29 21:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Continuing the conversion from single integrated VBT data to two, now
handling PSR data.
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 73 +++++++++++++----------
drivers/gpu/drm/i915/display/intel_bios.h | 2 +
drivers/gpu/drm/i915/display/intel_psr.c | 30 ++++++----
drivers/gpu/drm/i915/i915_drv.h | 34 +++++------
4 files changed, 77 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index dac81a5ebdaa0..40fa63336cd9d 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -729,15 +729,12 @@ parse_driver_features(struct drm_i915_private *i915,
driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS)
i915->vbt.int_lvds_support = 0;
}
-
- if (bdb->version < 228)
- i915->vbt.psr.enable = driver->psr_enabled;
}
static void
-parse_driver_features_drrs_only(struct drm_i915_private *i915,
- const struct bdb_header *bdb,
- struct ddi_vbt_port_info *info)
+parse_driver_features_drrs_psr_only(struct drm_i915_private *i915,
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info)
{
const struct bdb_driver_features *driver;
@@ -757,6 +754,8 @@ parse_driver_features_drrs_only(struct drm_i915_private *i915,
*/
if (!driver->drrs_enabled)
info->drrs_type = DRRS_NOT_SUPPORTED;
+
+ info->psr.enable = driver->psr_enabled;
}
static void
@@ -774,7 +773,7 @@ parse_power_conservation_features(struct drm_i915_private *i915,
if (!power)
return;
- i915->vbt.psr.enable = power->psr & BIT(panel_index);
+ info->psr.enable = power->psr & BIT(panel_index);
/*
* If DRRS is not supported, drrs_type has to be set to 0.
@@ -905,11 +904,11 @@ parse_edp(struct drm_i915_private *i915, const struct bdb_header *bdb,
}
static void
-parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb)
+parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info, int panel_index)
{
const struct bdb_psr *psr;
const struct psr_table *psr_table;
- int panel_type = i915->vbt.panel_type;
psr = find_section(bdb, BDB_PSR);
if (!psr) {
@@ -917,27 +916,27 @@ parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb)
return;
}
- psr_table = &psr->psr_table[panel_type];
+ psr_table = &psr->psr_table[panel_index];
- i915->vbt.psr.full_link = psr_table->full_link;
- i915->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
+ info->psr.full_link = psr_table->full_link;
+ info->psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
/* Allowed VBT values goes from 0 to 15 */
- i915->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
+ info->psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames;
switch (psr_table->lines_to_wait) {
case 0:
- i915->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT;
+ info->psr.lines_to_wait = PSR_0_LINES_TO_WAIT;
break;
case 1:
- i915->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT;
+ info->psr.lines_to_wait = PSR_1_LINE_TO_WAIT;
break;
case 2:
- i915->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT;
+ info->psr.lines_to_wait = PSR_4_LINES_TO_WAIT;
break;
case 3:
- i915->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT;
+ info->psr.lines_to_wait = PSR_8_LINES_TO_WAIT;
break;
default:
drm_dbg_kms(&i915->drm,
@@ -954,13 +953,13 @@ parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb)
(DISPLAY_VER(i915) >= 9 && !IS_BROXTON(i915))) {
switch (psr_table->tp1_wakeup_time) {
case 0:
- i915->vbt.psr.tp1_wakeup_time_us = 500;
+ info->psr.tp1_wakeup_time_us = 500;
break;
case 1:
- i915->vbt.psr.tp1_wakeup_time_us = 100;
+ info->psr.tp1_wakeup_time_us = 100;
break;
case 3:
- i915->vbt.psr.tp1_wakeup_time_us = 0;
+ info->psr.tp1_wakeup_time_us = 0;
break;
default:
drm_dbg_kms(&i915->drm,
@@ -968,19 +967,19 @@ parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb)
psr_table->tp1_wakeup_time);
fallthrough;
case 2:
- i915->vbt.psr.tp1_wakeup_time_us = 2500;
+ info->psr.tp1_wakeup_time_us = 2500;
break;
}
switch (psr_table->tp2_tp3_wakeup_time) {
case 0:
- i915->vbt.psr.tp2_tp3_wakeup_time_us = 500;
+ info->psr.tp2_tp3_wakeup_time_us = 500;
break;
case 1:
- i915->vbt.psr.tp2_tp3_wakeup_time_us = 100;
+ info->psr.tp2_tp3_wakeup_time_us = 100;
break;
case 3:
- i915->vbt.psr.tp2_tp3_wakeup_time_us = 0;
+ info->psr.tp2_tp3_wakeup_time_us = 0;
break;
default:
drm_dbg_kms(&i915->drm,
@@ -988,18 +987,18 @@ parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb)
psr_table->tp2_tp3_wakeup_time);
fallthrough;
case 2:
- i915->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
+ info->psr.tp2_tp3_wakeup_time_us = 2500;
break;
}
} else {
- i915->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
- i915->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
+ info->psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
+ info->psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
}
if (bdb->version >= 226) {
u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
- wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
+ wakeup_time = (wakeup_time >> (2 * panel_index)) & 0x3;
switch (wakeup_time) {
case 0:
wakeup_time = 500;
@@ -1015,10 +1014,10 @@ parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb)
wakeup_time = 2500;
break;
}
- i915->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time;
+ info->psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time;
} else {
/* Reusing PSR1 wakeup time for PSR2 in older VBTs */
- i915->vbt.psr.psr2_tp2_tp3_wakeup_time_us = i915->vbt.psr.tp2_tp3_wakeup_time_us;
+ info->psr.psr2_tp2_tp3_wakeup_time_us = info->psr.tp2_tp3_wakeup_time_us;
}
}
@@ -1986,10 +1985,11 @@ static void parse_integrated_panel(struct drm_i915_private *i915,
parse_panel_options(i915, bdb, info, panel_index);
parse_power_conservation_features(i915, bdb, info, panel_index);
- parse_driver_features_drrs_only(i915, bdb, info);
+ parse_driver_features_drrs_psr_only(i915, bdb, info);
parse_panel_dtd(i915, bdb, info, panel_index);
parse_lfp_backlight(i915, bdb, info, panel_index);
parse_edp(i915, bdb, info, panel_index);
+ parse_psr(i915, bdb, info, panel_index);
}
static void parse_ddi_port(struct drm_i915_private *i915,
@@ -2487,7 +2487,6 @@ void intel_bios_init(struct drm_i915_private *i915)
parse_panel_type(i915, bdb);
parse_sdvo_panel_data(i915, bdb);
parse_driver_features(i915, bdb);
- parse_psr(i915, bdb);
parse_mipi_config(i915, bdb);
parse_mipi_sequence(i915, bdb);
@@ -3141,3 +3140,13 @@ intel_bios_edp_info(struct intel_encoder *encoder)
return &i915->vbt.ddi_port_info[encoder->port].edp;
}
+
+const struct vbt_psr_info *
+intel_bios_psr_info(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = &dig_port->base;
+
+ return &i915->vbt.ddi_port_info[encoder->port].psr;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index 8fd9b52f921f7..c701871d9a74d 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -35,6 +35,7 @@
struct drm_i915_private;
struct intel_bios_encoder_data;
struct intel_crtc_state;
+struct intel_dp;
struct intel_encoder;
enum port;
@@ -270,5 +271,6 @@ enum drrs_support_type intel_bios_drrs_type(struct intel_encoder *encoder);
const struct drm_display_mode *intel_bios_lfp_lvds_info(struct intel_encoder *encoder);
const struct vbt_backlight_info *intel_bios_backlight_info(struct intel_encoder *encoder);
struct vbt_edp_info *intel_bios_edp_info(struct intel_encoder *encoder);
+const struct vbt_psr_info *intel_bios_psr_info(struct intel_dp *intel_dp);
#endif /* _INTEL_BIOS_H_ */
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 1b0daf649e823..d86161f82ab08 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -429,6 +429,7 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
{
+ const struct vbt_psr_info *vbt_psr_info = intel_bios_psr_info(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 val = 0;
@@ -441,20 +442,20 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
goto check_tp3_sel;
}
- if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
+ if (vbt_psr_info->tp1_wakeup_time_us == 0)
val |= EDP_PSR_TP1_TIME_0us;
- else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
+ else if (vbt_psr_info->tp1_wakeup_time_us <= 100)
val |= EDP_PSR_TP1_TIME_100us;
- else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
+ else if (vbt_psr_info->tp1_wakeup_time_us <= 500)
val |= EDP_PSR_TP1_TIME_500us;
else
val |= EDP_PSR_TP1_TIME_2500us;
- if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
+ if (vbt_psr_info->tp2_tp3_wakeup_time_us == 0)
val |= EDP_PSR_TP2_TP3_TIME_0us;
- else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
+ else if (vbt_psr_info->tp2_tp3_wakeup_time_us <= 100)
val |= EDP_PSR_TP2_TP3_TIME_100us;
- else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+ else if (vbt_psr_info->tp2_tp3_wakeup_time_us <= 500)
val |= EDP_PSR_TP2_TP3_TIME_500us;
else
val |= EDP_PSR_TP2_TP3_TIME_2500us;
@@ -471,13 +472,14 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
{
+ const struct vbt_psr_info *vbt_psr_info = intel_bios_psr_info(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
int idle_frames;
/* Let's use 6 as the minimum to cover all known cases including the
* off-by-one issue that HW has in some cases.
*/
- idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
+ idle_frames = max(6, vbt_psr_info->idle_frames);
idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf))
@@ -513,18 +515,19 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
{
+ const struct vbt_psr_info *vbt_psr_info = intel_bios_psr_info(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 val = 0;
if (dev_priv->params.psr_safest_params)
return EDP_PSR2_TP2_TIME_2500us;
- if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
- dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
+ if (vbt_psr_info->psr2_tp2_tp3_wakeup_time_us >= 0 &&
+ vbt_psr_info->psr2_tp2_tp3_wakeup_time_us <= 50)
val |= EDP_PSR2_TP2_TIME_50us;
- else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
+ else if (vbt_psr_info->psr2_tp2_tp3_wakeup_time_us <= 100)
val |= EDP_PSR2_TP2_TIME_100us;
- else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
+ else if (vbt_psr_info->psr2_tp2_tp3_wakeup_time_us <= 500)
val |= EDP_PSR2_TP2_TIME_500us;
else
val |= EDP_PSR2_TP2_TIME_2500us;
@@ -2163,6 +2166,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
*/
void intel_psr_init(struct intel_dp *intel_dp)
{
+ const struct vbt_psr_info *vbt_psr_info = intel_bios_psr_info(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -2195,7 +2199,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE;
if (dev_priv->params.enable_psr == -1)
- if (DISPLAY_VER(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
+ if (DISPLAY_VER(dev_priv) < 9 || !vbt_psr_info->enable)
dev_priv->params.enable_psr = 0;
/* Set link_standby x link_off defaults */
@@ -2204,7 +2208,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
intel_dp->psr.link_standby = false;
else if (DISPLAY_VER(dev_priv) < 12)
/* For new platforms up to TGL let's respect VBT back again */
- intel_dp->psr.link_standby = dev_priv->vbt.psr.full_link;
+ intel_dp->psr.link_standby = vbt_psr_info->full_link;
INIT_WORK(&intel_dp->psr.work, intel_psr_work);
INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5b84f2129c2bf..2db6c4461b39e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -636,6 +636,13 @@ i915_fence_timeout(const struct drm_i915_private *i915)
/* Amount of PSF GV points, BSpec precisely defines this */
#define I915_NUM_PSF_GV_POINTS 3
+enum psr_lines_to_wait {
+ PSR_0_LINES_TO_WAIT = 0,
+ PSR_1_LINE_TO_WAIT,
+ PSR_4_LINES_TO_WAIT,
+ PSR_8_LINES_TO_WAIT
+};
+
struct ddi_vbt_port_info {
/* Non-NULL if port present. */
struct intel_bios_encoder_data *devdata;
@@ -675,13 +682,17 @@ struct ddi_vbt_port_info {
struct edp_power_seq pps;
bool hobl;
} edp;
-};
-enum psr_lines_to_wait {
- PSR_0_LINES_TO_WAIT = 0,
- PSR_1_LINE_TO_WAIT,
- PSR_4_LINES_TO_WAIT,
- PSR_8_LINES_TO_WAIT
+ struct vbt_psr_info {
+ bool enable;
+ bool full_link;
+ bool require_aux_wakeup;
+ int idle_frames;
+ enum psr_lines_to_wait lines_to_wait;
+ int tp1_wakeup_time_us;
+ int tp2_tp3_wakeup_time_us;
+ int psr2_tp2_tp3_wakeup_time_us;
+ } psr;
};
struct intel_vbt_data {
@@ -702,17 +713,6 @@ struct intel_vbt_data {
unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
enum drm_panel_orientation orientation;
- struct {
- bool enable;
- bool full_link;
- bool require_aux_wakeup;
- int idle_frames;
- enum psr_lines_to_wait lines_to_wait;
- int tp1_wakeup_time_us;
- int tp2_tp3_wakeup_time_us;
- int psr2_tp2_tp3_wakeup_time_us;
- } psr;
-
/* MIPI DSI */
struct {
u16 panel_id;
--
2.32.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH CI 07/10] drm/i915/bios: Enable parse of two DSI panels data
2021-07-29 21:55 [Intel-gfx] [PATCH CI 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() José Roberto de Souza
` (4 preceding siblings ...)
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 06/10] drm/i915/bios: Enable parse of two integrated panels PSR data José Roberto de Souza
@ 2021-07-29 21:55 ` José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 08/10] drm/i915/bios: Nuke panel_type José Roberto de Souza
` (6 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: José Roberto de Souza @ 2021-07-29 21:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Continuing the conversion from single integrated VBT data to two, now
handling DSI data.
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 12 +-
drivers/gpu/drm/i915/display/intel_bios.c | 163 ++++++++++---------
drivers/gpu/drm/i915/display/intel_bios.h | 1 +
drivers/gpu/drm/i915/display/intel_dsi.c | 8 +-
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 58 ++++---
drivers/gpu/drm/i915/display/intel_panel.c | 3 +-
drivers/gpu/drm/i915/display/vlv_dsi.c | 14 +-
drivers/gpu/drm/i915/i915_drv.h | 30 ++--
8 files changed, 161 insertions(+), 128 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 43ec7fcd3f5d2..0a8360d196cc7 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1846,7 +1846,8 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
{
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
+ const struct vbt_dsi_info *vbt_dsi_info = intel_bios_dsi_info(&intel_dsi->base);
+ struct mipi_config *mipi_config = vbt_dsi_info->config;
u32 tlpx_ns;
u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
u32 ths_prepare_ns, tclk_trail_ns;
@@ -1977,6 +1978,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
struct intel_connector *intel_connector;
struct drm_connector *connector;
struct drm_display_mode *fixed_mode;
+ const struct vbt_dsi_info *vbt_dsi_info;
enum port port;
if (!intel_bios_is_dsi_present(dev_priv, &port))
@@ -2044,13 +2046,15 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
intel_panel_setup_backlight(connector, INVALID_PIPE);
- if (dev_priv->vbt.dsi.config->dual_link)
+ vbt_dsi_info = intel_bios_dsi_info(encoder);
+
+ if (vbt_dsi_info->config->dual_link)
intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
else
intel_dsi->ports = BIT(port);
- intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
- intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
+ intel_dsi->dcs_backlight_ports = vbt_dsi_info->bl_ports;
+ intel_dsi->dcs_cabc_ports = vbt_dsi_info->cabc_ports;
for_each_dsi_port(port, intel_dsi->ports) {
struct intel_dsi_host *host;
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 40fa63336cd9d..aa98bef4b8a57 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1022,55 +1022,56 @@ parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb,
}
static void parse_dsi_backlight_ports(struct drm_i915_private *i915,
- u16 version, enum port port)
+ u16 version, enum port port,
+ struct ddi_vbt_port_info *info)
{
- if (!i915->vbt.dsi.config->dual_link || version < 197) {
- i915->vbt.dsi.bl_ports = BIT(port);
- if (i915->vbt.dsi.config->cabc_supported)
- i915->vbt.dsi.cabc_ports = BIT(port);
+ if (!info->dsi.config->dual_link || version < 197) {
+ info->dsi.bl_ports = BIT(port);
+ if (info->dsi.config->cabc_supported)
+ info->dsi.cabc_ports = BIT(port);
return;
}
- switch (i915->vbt.dsi.config->dl_dcs_backlight_ports) {
+ switch (info->dsi.config->dl_dcs_backlight_ports) {
case DL_DCS_PORT_A:
- i915->vbt.dsi.bl_ports = BIT(PORT_A);
+ info->dsi.bl_ports = BIT(PORT_A);
break;
case DL_DCS_PORT_C:
- i915->vbt.dsi.bl_ports = BIT(PORT_C);
+ info->dsi.bl_ports = BIT(PORT_C);
break;
default:
case DL_DCS_PORT_A_AND_C:
- i915->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C);
+ info->dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C);
break;
}
- if (!i915->vbt.dsi.config->cabc_supported)
+ if (!info->dsi.config->cabc_supported)
return;
- switch (i915->vbt.dsi.config->dl_dcs_cabc_ports) {
+ switch (info->dsi.config->dl_dcs_cabc_ports) {
case DL_DCS_PORT_A:
- i915->vbt.dsi.cabc_ports = BIT(PORT_A);
+ info->dsi.cabc_ports = BIT(PORT_A);
break;
case DL_DCS_PORT_C:
- i915->vbt.dsi.cabc_ports = BIT(PORT_C);
+ info->dsi.cabc_ports = BIT(PORT_C);
break;
default:
case DL_DCS_PORT_A_AND_C:
- i915->vbt.dsi.cabc_ports =
- BIT(PORT_A) | BIT(PORT_C);
+ info->dsi.cabc_ports = BIT(PORT_A) | BIT(PORT_C);
break;
}
}
static void
parse_mipi_config(struct drm_i915_private *i915,
- const struct bdb_header *bdb)
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info,
+ int panel_index)
{
const struct bdb_mipi_config *start;
const struct mipi_config *config;
const struct mipi_pps_data *pps;
- int panel_type = i915->vbt.panel_type;
enum port port;
/* parse MIPI blocks only if LFP type is MIPI */
@@ -1078,14 +1079,14 @@ parse_mipi_config(struct drm_i915_private *i915,
return;
/* Initialize this to undefined indicating no generic MIPI support */
- i915->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID;
+ info->dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID;
/* Block #40 is already parsed and panel_fixed_mode is
* stored in i915->lfp_lvds_vbt_mode
* resuse this when needed
*/
- /* Parse #52 for panel index used from panel_type already
+ /* Parse #52 for panel index used from panel_index already
* parsed
*/
start = find_section(bdb, BDB_MIPI_CONFIG);
@@ -1095,27 +1096,27 @@ parse_mipi_config(struct drm_i915_private *i915,
}
drm_dbg(&i915->drm, "Found MIPI Config block, panel index = %d\n",
- panel_type);
+ panel_index);
/*
* get hold of the correct configuration block and pps data as per
- * the panel_type as index
+ * the panel_index as index
*/
- config = &start->config[panel_type];
- pps = &start->pps[panel_type];
+ config = &start->config[panel_index];
+ pps = &start->pps[panel_index];
/* store as of now full data. Trim when we realise all is not needed */
- i915->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL);
- if (!i915->vbt.dsi.config)
+ info->dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL);
+ if (!info->dsi.config)
return;
- i915->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL);
- if (!i915->vbt.dsi.pps) {
- kfree(i915->vbt.dsi.config);
+ info->dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL);
+ if (!info->dsi.pps) {
+ kfree(info->dsi.config);
return;
}
- parse_dsi_backlight_ports(i915, bdb->version, port);
+ parse_dsi_backlight_ports(i915, bdb->version, port, info);
/* FIXME is the 90 vs. 270 correct? */
switch (config->rotation) {
@@ -1124,25 +1125,25 @@ parse_mipi_config(struct drm_i915_private *i915,
* Most (all?) VBTs claim 0 degrees despite having
* an upside down panel, thus we do not trust this.
*/
- i915->vbt.dsi.orientation =
+ info->dsi.orientation =
DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
break;
case ENABLE_ROTATION_90:
- i915->vbt.dsi.orientation =
+ info->dsi.orientation =
DRM_MODE_PANEL_ORIENTATION_RIGHT_UP;
break;
case ENABLE_ROTATION_180:
- i915->vbt.dsi.orientation =
+ info->dsi.orientation =
DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
break;
case ENABLE_ROTATION_270:
- i915->vbt.dsi.orientation =
+ info->dsi.orientation =
DRM_MODE_PANEL_ORIENTATION_LEFT_UP;
break;
}
/* We have mandatory mipi config blocks. Initialize as generic panel */
- i915->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
+ info->dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
}
/* Find the sequence block and size for the given panel. */
@@ -1305,13 +1306,14 @@ static int goto_next_sequence_v3(const u8 *data, int index, int total)
* Get len of pre-fixed deassert fragment from a v1 init OTP sequence,
* skip all delay + gpio operands and stop at the first DSI packet op.
*/
-static int get_init_otp_deassert_fragment_len(struct drm_i915_private *i915)
+static int get_init_otp_deassert_fragment_len(struct drm_i915_private *i915,
+ struct ddi_vbt_port_info *info)
{
- const u8 *data = i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
+ const u8 *data = info->dsi.sequence[MIPI_SEQ_INIT_OTP];
int index, len;
if (drm_WARN_ON(&i915->drm,
- !data || i915->vbt.dsi.seq_version != 1))
+ !data || info->dsi.seq_version != 1))
return 0;
/* index = 1 to skip sequence byte */
@@ -1339,7 +1341,8 @@ static int get_init_otp_deassert_fragment_len(struct drm_i915_private *i915)
* these devices we split the init OTP sequence into a deassert sequence and
* the actual init OTP part.
*/
-static void fixup_mipi_sequences(struct drm_i915_private *i915)
+static void fixup_mipi_sequences(struct drm_i915_private *i915,
+ struct ddi_vbt_port_info *info)
{
u8 *init_otp;
int len;
@@ -1349,18 +1352,18 @@ static void fixup_mipi_sequences(struct drm_i915_private *i915)
return;
/* Limit this to v1 vid-mode sequences */
- if (i915->vbt.dsi.config->is_cmd_mode ||
- i915->vbt.dsi.seq_version != 1)
+ if (info->dsi.config->is_cmd_mode ||
+ info->dsi.seq_version != 1)
return;
/* Only do this if there are otp and assert seqs and no deassert seq */
- if (!i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] ||
- !i915->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] ||
- i915->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET])
+ if (!info->dsi.sequence[MIPI_SEQ_INIT_OTP] ||
+ !info->dsi.sequence[MIPI_SEQ_ASSERT_RESET] ||
+ info->dsi.sequence[MIPI_SEQ_DEASSERT_RESET])
return;
/* The deassert-sequence ends at the first DSI packet */
- len = get_init_otp_deassert_fragment_len(i915);
+ len = get_init_otp_deassert_fragment_len(i915, info);
if (!len)
return;
@@ -1368,26 +1371,27 @@ static void fixup_mipi_sequences(struct drm_i915_private *i915)
"Using init OTP fragment to deassert reset\n");
/* Copy the fragment, update seq byte and terminate it */
- init_otp = (u8 *)i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
- i915->vbt.dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL);
- if (!i915->vbt.dsi.deassert_seq)
+ init_otp = (u8 *)info->dsi.sequence[MIPI_SEQ_INIT_OTP];
+ info->dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL);
+ if (!info->dsi.deassert_seq)
return;
- i915->vbt.dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET;
- i915->vbt.dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END;
+ info->dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET;
+ info->dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END;
/* Use the copy for deassert */
- i915->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] =
- i915->vbt.dsi.deassert_seq;
+ info->dsi.sequence[MIPI_SEQ_DEASSERT_RESET] =
+ info->dsi.deassert_seq;
/* Replace the last byte of the fragment with init OTP seq byte */
init_otp[len - 1] = MIPI_SEQ_INIT_OTP;
/* And make MIPI_MIPI_SEQ_INIT_OTP point to it */
- i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1;
+ info->dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1;
}
static void
parse_mipi_sequence(struct drm_i915_private *i915,
- const struct bdb_header *bdb)
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info,
+ int panel_index)
{
- int panel_type = i915->vbt.panel_type;
const struct bdb_mipi_sequence *sequence;
const u8 *seq_data;
u32 seq_size;
@@ -1395,7 +1399,7 @@ parse_mipi_sequence(struct drm_i915_private *i915,
int index = 0;
/* Only our generic panel driver uses the sequence block. */
- if (i915->vbt.dsi.panel_id != MIPI_DSI_GENERIC_PANEL_ID)
+ if (info->dsi.panel_id != MIPI_DSI_GENERIC_PANEL_ID)
return;
sequence = find_section(bdb, BDB_MIPI_SEQUENCE);
@@ -1416,7 +1420,7 @@ parse_mipi_sequence(struct drm_i915_private *i915,
drm_dbg(&i915->drm, "Found MIPI sequence block v%u\n",
sequence->version);
- seq_data = find_panel_sequence_block(sequence, panel_type, &seq_size);
+ seq_data = find_panel_sequence_block(sequence, panel_index, &seq_size);
if (!seq_data)
return;
@@ -1441,7 +1445,7 @@ parse_mipi_sequence(struct drm_i915_private *i915,
drm_dbg_kms(&i915->drm,
"Unsupported sequence %u\n", seq_id);
- i915->vbt.dsi.sequence[seq_id] = data + index;
+ info->dsi.sequence[seq_id] = data + index;
if (sequence->version >= 3)
index = goto_next_sequence_v3(data, index, seq_size);
@@ -1454,18 +1458,18 @@ parse_mipi_sequence(struct drm_i915_private *i915,
}
}
- i915->vbt.dsi.data = data;
- i915->vbt.dsi.size = seq_size;
- i915->vbt.dsi.seq_version = sequence->version;
+ info->dsi.data = data;
+ info->dsi.size = seq_size;
+ info->dsi.seq_version = sequence->version;
- fixup_mipi_sequences(i915);
+ fixup_mipi_sequences(i915, info);
drm_dbg(&i915->drm, "MIPI related VBT parsing complete\n");
return;
err:
kfree(data);
- memset(i915->vbt.dsi.sequence, 0, sizeof(i915->vbt.dsi.sequence));
+ memset(info->dsi.sequence, 0, sizeof(info->dsi.sequence));
}
static void
@@ -1990,6 +1994,8 @@ static void parse_integrated_panel(struct drm_i915_private *i915,
parse_lfp_backlight(i915, bdb, info, panel_index);
parse_edp(i915, bdb, info, panel_index);
parse_psr(i915, bdb, info, panel_index);
+ parse_mipi_config(i915, bdb, info, panel_index);
+ parse_mipi_sequence(i915, bdb, info, panel_index);
}
static void parse_ddi_port(struct drm_i915_private *i915,
@@ -2487,8 +2493,6 @@ void intel_bios_init(struct drm_i915_private *i915)
parse_panel_type(i915, bdb);
parse_sdvo_panel_data(i915, bdb);
parse_driver_features(i915, bdb);
- parse_mipi_config(i915, bdb);
- parse_mipi_sequence(i915, bdb);
/* Depends on child device list */
parse_compression_parameters(i915, bdb);
@@ -2523,20 +2527,23 @@ void intel_bios_driver_remove(struct drm_i915_private *i915)
}
for (i = 0; i < I915_MAX_PORTS; i++) {
- kfree(i915->vbt.ddi_port_info[i].lfp_lvds_vbt_mode);
- i915->vbt.ddi_port_info[i].lfp_lvds_vbt_mode = NULL;
+ struct ddi_vbt_port_info *info = &i915->vbt.ddi_port_info[i];
+
+ kfree(info->lfp_lvds_vbt_mode);
+ info->lfp_lvds_vbt_mode = NULL;
+
+ kfree(info->dsi.data);
+ info->dsi.data = NULL;
+ kfree(info->dsi.pps);
+ info->dsi.pps = NULL;
+ kfree(info->dsi.config);
+ info->dsi.config = NULL;
+ kfree(info->dsi.deassert_seq);
+ info->dsi.deassert_seq = NULL;
}
kfree(i915->vbt.sdvo_lvds_vbt_mode);
i915->vbt.sdvo_lvds_vbt_mode = NULL;
- kfree(i915->vbt.dsi.data);
- i915->vbt.dsi.data = NULL;
- kfree(i915->vbt.dsi.pps);
- i915->vbt.dsi.pps = NULL;
- kfree(i915->vbt.dsi.config);
- i915->vbt.dsi.config = NULL;
- kfree(i915->vbt.dsi.deassert_seq);
- i915->vbt.dsi.deassert_seq = NULL;
}
/**
@@ -3150,3 +3157,11 @@ intel_bios_psr_info(struct intel_dp *intel_dp)
return &i915->vbt.ddi_port_info[encoder->port].psr;
}
+
+const struct vbt_dsi_info *
+intel_bios_dsi_info(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+ return &i915->vbt.ddi_port_info[encoder->port].dsi;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index c701871d9a74d..6e953a89c84cb 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -272,5 +272,6 @@ const struct drm_display_mode *intel_bios_lfp_lvds_info(struct intel_encoder *en
const struct vbt_backlight_info *intel_bios_backlight_info(struct intel_encoder *encoder);
struct vbt_edp_info *intel_bios_edp_info(struct intel_encoder *encoder);
const struct vbt_psr_info *intel_bios_psr_info(struct intel_dp *intel_dp);
+const struct vbt_dsi_info *intel_bios_dsi_info(struct intel_encoder *encoder);
#endif /* _INTEL_BIOS_H_ */
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c
index f453ceb8d1494..2cd819a7f9dd6 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi.c
@@ -115,14 +115,10 @@ struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
enum drm_panel_orientation
intel_dsi_get_panel_orientation(struct intel_connector *connector)
{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ const struct vbt_dsi_info *vbt_dsi_info = intel_bios_dsi_info(connector->encoder);
enum drm_panel_orientation orientation;
- orientation = dev_priv->vbt.dsi.orientation;
- if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
- return orientation;
-
- orientation = dev_priv->vbt.orientation;
+ orientation = vbt_dsi_info->orientation;
if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
return orientation;
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 2218de0773bf0..24de775ee7b30 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -225,9 +225,11 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
return data;
}
-static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
+static void vlv_exec_gpio(struct intel_dsi *intel_dsi,
u8 gpio_source, u8 gpio_index, bool value)
{
+ const struct vbt_dsi_info *vbt_dsi_info = intel_bios_dsi_info(&intel_dsi->base);
+ struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
struct gpio_map *map;
u16 pconf0, padval;
u32 tmp;
@@ -241,7 +243,7 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
map = &vlv_gpio_table[gpio_index];
- if (dev_priv->vbt.dsi.seq_version >= 3) {
+ if (vbt_dsi_info->seq_version >= 3) {
/* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
port = IOSF_PORT_GPIO_NC;
} else {
@@ -272,14 +274,16 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
}
-static void chv_exec_gpio(struct drm_i915_private *dev_priv,
+static void chv_exec_gpio(struct intel_dsi *intel_dsi,
u8 gpio_source, u8 gpio_index, bool value)
{
+ const struct vbt_dsi_info *vbt_dsi_info = intel_bios_dsi_info(&intel_dsi->base);
+ struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
u16 cfg0, cfg1;
u16 family_num;
u8 port;
- if (dev_priv->vbt.dsi.seq_version >= 3) {
+ if (vbt_dsi_info->seq_version >= 3) {
if (gpio_index >= CHV_GPIO_IDX_START_SE) {
/* XXX: it's unclear whether 255->57 is part of SE. */
gpio_index -= CHV_GPIO_IDX_START_SE;
@@ -325,9 +329,10 @@ static void chv_exec_gpio(struct drm_i915_private *dev_priv,
vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
}
-static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
+static void bxt_exec_gpio(struct intel_dsi *intel_dsi,
u8 gpio_source, u8 gpio_index, bool value)
{
+ struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
/* XXX: this table is a quick ugly hack. */
static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
@@ -351,14 +356,17 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
gpiod_set_value(gpio_desc, value);
}
-static void icl_exec_gpio(struct drm_i915_private *dev_priv,
+static void icl_exec_gpio(struct intel_dsi *intel_dsi,
u8 gpio_source, u8 gpio_index, bool value)
{
- drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
+ struct drm_device *drm = intel_dsi->base.base.dev;
+
+ drm_dbg_kms(drm, "Skipping ICL GPIO element execution\n");
}
static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
{
+ const struct vbt_dsi_info *vbt_dsi_info = intel_bios_dsi_info(&intel_dsi->base);
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
u8 gpio_source, gpio_index = 0, gpio_number;
@@ -366,13 +374,13 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
drm_dbg_kms(&dev_priv->drm, "\n");
- if (dev_priv->vbt.dsi.seq_version >= 3)
+ if (vbt_dsi_info->seq_version >= 3)
gpio_index = *data++;
gpio_number = *data++;
/* gpio source in sequence v2 only */
- if (dev_priv->vbt.dsi.seq_version == 2)
+ if (vbt_dsi_info->seq_version == 2)
gpio_source = (*data >> 1) & 3;
else
gpio_source = 0;
@@ -381,13 +389,13 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
value = *data++ & 1;
if (DISPLAY_VER(dev_priv) >= 11)
- icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
+ icl_exec_gpio(intel_dsi, gpio_source, gpio_index, value);
else if (IS_VALLEYVIEW(dev_priv))
- vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
+ vlv_exec_gpio(intel_dsi, gpio_source, gpio_number, value);
else if (IS_CHERRYVIEW(dev_priv))
- chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
+ chv_exec_gpio(intel_dsi, gpio_source, gpio_number, value);
else
- bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value);
+ bxt_exec_gpio(intel_dsi, gpio_source, gpio_index, value);
return data;
}
@@ -577,15 +585,16 @@ static const char *sequence_name(enum mipi_seq seq_id)
static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
enum mipi_seq seq_id)
{
+ const struct vbt_dsi_info *vbt_dsi_info = intel_bios_dsi_info(&intel_dsi->base);
struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
const u8 *data;
fn_mipi_elem_exec mipi_elem_exec;
if (drm_WARN_ON(&dev_priv->drm,
- seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence)))
+ seq_id >= ARRAY_SIZE(vbt_dsi_info->sequence)))
return;
- data = dev_priv->vbt.dsi.sequence[seq_id];
+ data = vbt_dsi_info->sequence[seq_id];
if (!data)
return;
@@ -598,7 +607,7 @@ static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
data++;
/* Skip Size of Sequence. */
- if (dev_priv->vbt.dsi.seq_version >= 3)
+ if (vbt_dsi_info->seq_version >= 3)
data += 4;
while (1) {
@@ -614,7 +623,7 @@ static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
mipi_elem_exec = NULL;
/* Size of Operation. */
- if (dev_priv->vbt.dsi.seq_version >= 3)
+ if (vbt_dsi_info->seq_version >= 3)
operation_size = *data++;
if (mipi_elem_exec) {
@@ -662,10 +671,10 @@ void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
{
- struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+ const struct vbt_dsi_info *vbt_dsi_info = intel_bios_dsi_info(&intel_dsi->base);
/* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
- if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
+ if (is_vid_mode(intel_dsi) && vbt_dsi_info->seq_version >= 3)
return;
msleep(msec);
@@ -727,8 +736,9 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
{
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
- struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
+ const struct vbt_dsi_info *vbt_dsi_info = intel_bios_dsi_info(&intel_dsi->base);
+ struct mipi_config *mipi_config = vbt_dsi_info->config;
+ struct mipi_pps_data *pps = vbt_dsi_info->pps;
const struct drm_display_mode *mode = intel_bios_lfp_lvds_info(&intel_dsi->base);
u16 burst_mode_ratio;
enum port port;
@@ -870,7 +880,8 @@ void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on)
{
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
+ const struct vbt_dsi_info *vbt_dsi_info = intel_bios_dsi_info(&intel_dsi->base);
+ struct mipi_config *mipi_config = vbt_dsi_info->config;
enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
bool want_backlight_gpio = false;
bool want_panel_gpio = false;
@@ -925,7 +936,8 @@ void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi)
{
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
+ const struct vbt_dsi_info *vbt_dsi_info = intel_bios_dsi_info(&intel_dsi->base);
+ struct mipi_config *mipi_config = vbt_dsi_info->config;
if (intel_dsi->gpio_panel) {
gpiod_put(intel_dsi->gpio_panel);
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 9c892476d8621..92d93ddf28140 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -1924,6 +1924,7 @@ cnp_setup_backlight(struct intel_connector *connector, enum pipe unused)
static int ext_pwm_setup_backlight(struct intel_connector *connector,
enum pipe pipe)
{
+ const struct vbt_dsi_info *vbt_dsi_info = intel_bios_dsi_info(connector->encoder);
struct drm_device *dev = connector->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_panel *panel = &connector->panel;
@@ -1931,7 +1932,7 @@ static int ext_pwm_setup_backlight(struct intel_connector *connector,
u32 level;
/* Get the right PWM chip for DSI backlight according to VBT */
- if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
+ if (vbt_dsi_info->config->pwm_blc == PPS_BLC_PMIC) {
panel->backlight.pwm = pwm_get(dev->dev, "pwm_pmic_backlight");
desc = "PMIC";
} else {
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 0ee4ff341e25d..0758726fa19bd 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -780,6 +780,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state,
const struct drm_connector_state *conn_state)
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+ const struct vbt_dsi_info *vbt_dsi_info = intel_bios_dsi_info(&intel_dsi->base);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -837,7 +838,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state,
* the delay in that case. If there is no deassert-seq, then an
* unconditional msleep is used to give the panel time to power-on.
*/
- if (dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) {
+ if (vbt_dsi_info->sequence[MIPI_SEQ_DEASSERT_RESET]) {
intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
} else {
@@ -1665,7 +1666,8 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
{
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
+ const struct vbt_dsi_info *vbt_dsi_info = intel_bios_dsi_info(&intel_dsi->base);
+ struct mipi_config *mipi_config = vbt_dsi_info->config;
u32 tlpx_ns, extra_byte_count, tlpx_ui;
u32 ui_num, ui_den;
u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
@@ -1835,6 +1837,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
struct intel_connector *intel_connector;
struct drm_connector *connector;
struct drm_display_mode *current_mode, *fixed_mode;
+ const struct vbt_dsi_info *vbt_dsi_info;
enum port port;
enum pipe pipe;
@@ -1898,14 +1901,15 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
intel_encoder->pipe_mask = BIT(PIPE_B);
intel_dsi->panel_power_off_time = ktime_get_boottime();
+ vbt_dsi_info = intel_bios_dsi_info(intel_encoder);
- if (dev_priv->vbt.dsi.config->dual_link)
+ if (vbt_dsi_info->config->dual_link)
intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
else
intel_dsi->ports = BIT(port);
- intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
- intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
+ intel_dsi->dcs_backlight_ports = vbt_dsi_info->bl_ports;
+ intel_dsi->dcs_cabc_ports = vbt_dsi_info->cabc_ports;
/* Create a DSI host (and a device) for each port. */
for_each_dsi_port(port, intel_dsi->ports) {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2db6c4461b39e..3535759796033 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -693,6 +693,21 @@ struct ddi_vbt_port_info {
int tp2_tp3_wakeup_time_us;
int psr2_tp2_tp3_wakeup_time_us;
} psr;
+
+ /* MIPI DSI */
+ struct vbt_dsi_info {
+ u16 panel_id;
+ struct mipi_config *config;
+ struct mipi_pps_data *pps;
+ u16 bl_ports;
+ u16 cabc_ports;
+ u8 seq_version;
+ u32 size;
+ u8 *data;
+ const u8 *sequence[MIPI_SEQ_MAX];
+ u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
+ enum drm_panel_orientation orientation;
+ } dsi;
};
struct intel_vbt_data {
@@ -713,21 +728,6 @@ struct intel_vbt_data {
unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
enum drm_panel_orientation orientation;
- /* MIPI DSI */
- struct {
- u16 panel_id;
- struct mipi_config *config;
- struct mipi_pps_data *pps;
- u16 bl_ports;
- u16 cabc_ports;
- u8 seq_version;
- u32 size;
- u8 *data;
- const u8 *sequence[MIPI_SEQ_MAX];
- u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
- enum drm_panel_orientation orientation;
- } dsi;
-
int crt_ddc_pin;
struct list_head display_devices;
--
2.32.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH CI 08/10] drm/i915/bios: Nuke panel_type
2021-07-29 21:55 [Intel-gfx] [PATCH CI 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() José Roberto de Souza
` (5 preceding siblings ...)
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 07/10] drm/i915/bios: Enable parse of two DSI panels data José Roberto de Souza
@ 2021-07-29 21:55 ` José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 09/10] drm/i915/bios: Only use opregion panel index for display ver 8 and older José Roberto de Souza
` (5 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: José Roberto de Souza @ 2021-07-29 21:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
All the users were converted, now we can drop it.
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 36 -----------------------
drivers/gpu/drm/i915/i915_drv.h | 1 -
2 files changed, 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index aa98bef4b8a57..ded04e5b7772b 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -211,41 +211,6 @@ get_lvds_fp_timing(const struct bdb_header *bdb,
return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);
}
-/*
- * Parse and set vbt.panel_type, it will be used by the VBT blocks that are
- * not being called from parse_integrated_panel() yet.
- */
-static void parse_panel_type(struct drm_i915_private *i915,
- const struct bdb_header *bdb)
-{
- const struct bdb_lvds_options *lvds_options;
- int ret, panel_type;
-
- lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
- if (!lvds_options)
- return;
-
- ret = intel_opregion_get_panel_type(i915);
- if (ret >= 0) {
- drm_WARN_ON(&i915->drm, ret > 0xf);
- panel_type = ret;
- drm_dbg_kms(&i915->drm, "Panel type: %d (OpRegion)\n",
- panel_type);
- } else {
- if (lvds_options->panel_type > 0xf) {
- drm_dbg_kms(&i915->drm,
- "Invalid VBT panel type 0x%x\n",
- lvds_options->panel_type);
- return;
- }
- panel_type = lvds_options->panel_type;
- drm_dbg_kms(&i915->drm, "Panel type: %d (VBT)\n",
- panel_type);
- }
-
- i915->vbt.panel_type = panel_type;
-}
-
/* Parse general panel options */
static void
parse_panel_options(struct drm_i915_private *i915,
@@ -2490,7 +2455,6 @@ void intel_bios_init(struct drm_i915_private *i915)
/* Grab useful general definitions */
parse_general_features(i915, bdb);
parse_general_definitions(i915, bdb);
- parse_panel_type(i915, bdb);
parse_sdvo_panel_data(i915, bdb);
parse_driver_features(i915, bdb);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3535759796033..ad8c838b7df41 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -723,7 +723,6 @@ struct intel_vbt_data {
unsigned int int_lvds_support:1;
unsigned int display_clock_mode:1;
unsigned int fdi_rx_polarity_inverted:1;
- unsigned int panel_type:4;
int lvds_ssc_freq;
unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
enum drm_panel_orientation orientation;
--
2.32.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH CI 09/10] drm/i915/bios: Only use opregion panel index for display ver 8 and older
2021-07-29 21:55 [Intel-gfx] [PATCH CI 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() José Roberto de Souza
` (6 preceding siblings ...)
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 08/10] drm/i915/bios: Nuke panel_type José Roberto de Souza
@ 2021-07-29 21:55 ` José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 10/10] drm/i915/display/tgl+: Use PPS index from vbt José Roberto de Souza
` (4 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: José Roberto de Souza @ 2021-07-29 21:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
On newer platform this opregion call always fails, also it do not
support multiple panels so dropping it.
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 19 +++++++------------
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index ded04e5b7772b..8775983a75c6b 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1924,7 +1924,7 @@ static void parse_integrated_panel(struct drm_i915_private *i915,
{
const struct vbt_header *vbt = i915->opregion.vbt;
const struct bdb_header *bdb;
- int lfp_inst = 0, panel_index, opregion_panel_index;
+ int lfp_inst = 0, panel_index;
if (devdata->child.handle == HANDLE_LFP_1)
lfp_inst = 1;
@@ -1937,17 +1937,12 @@ static void parse_integrated_panel(struct drm_i915_private *i915,
bdb = get_bdb_header(vbt);
panel_index = get_lfp_panel_index(i915, bdb, lfp_inst);
- opregion_panel_index = intel_opregion_get_panel_type(i915);
- /*
- * TODO: the current implementation always use the panel index from
- * opregion if available due to issues with old platforms.
- * But this do not supports two panels and in SKL or newer I never saw a
- * system were this call returns a valid value.
- * So will change this to only use opregion up to BDW in a separated
- * commit.
- */
- if (opregion_panel_index >= 0)
- panel_index = opregion_panel_index;
+ if (DISPLAY_VER(i915) < 9) {
+ int opregion_panel_index = intel_opregion_get_panel_type(i915);
+
+ if (opregion_panel_index >= 0)
+ opregion_panel_index = panel_index;
+ }
if (panel_index == -1)
return;
--
2.32.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH CI 10/10] drm/i915/display/tgl+: Use PPS index from vbt
2021-07-29 21:55 [Intel-gfx] [PATCH CI 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() José Roberto de Souza
` (7 preceding siblings ...)
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 09/10] drm/i915/bios: Only use opregion panel index for display ver 8 and older José Roberto de Souza
@ 2021-07-29 21:55 ` José Roberto de Souza
2021-07-29 22:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() Patchwork
` (3 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: José Roberto de Souza @ 2021-07-29 21:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Tigerlake and newer has two instances of PPS, to support up to two
eDP panels.
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_pps.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index f4c15a1f31d15..ee92f416834e5 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -368,7 +368,8 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
memset(regs, 0, sizeof(*regs));
- if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
+ if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ||
+ DISPLAY_VER(dev_priv) >= 12)
pps_idx = bxt_power_sequencer_idx(intel_dp);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
pps_idx = vlv_power_sequencer_pipe(intel_dp);
--
2.32.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port()
2021-07-29 21:55 [Intel-gfx] [PATCH CI 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() José Roberto de Souza
` (8 preceding siblings ...)
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 10/10] drm/i915/display/tgl+: Use PPS index from vbt José Roberto de Souza
@ 2021-07-29 22:00 ` Patchwork
2021-07-29 22:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2021-07-29 22:00 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port()
URL : https://patchwork.freedesktop.org/series/93210/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
311c3d22baba drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port()
-:77: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "devdata->dsc"
#77: FILE: drivers/gpu/drm/i915/display/intel_bios.c:1937:
+ devdata->dsc != NULL, is_dsi);
total: 0 errors, 0 warnings, 1 checks, 54 lines checked
db14d408c50c drm/i915/bios: Start to support two integrated panels
8533acd4179c drm/i915/bios: Enable parse of two integrated panels timing data
08c75431bf45 drm/i915/bios: Enable parse of two integrated panels backlight data
75d73519ca13 drm/i915/bios: Enable parse of two integrated panels eDP data
4b6c19a53732 drm/i915/bios: Enable parse of two integrated panels PSR data
dae060ccab5f drm/i915/bios: Enable parse of two DSI panels data
32dda397f679 drm/i915/bios: Nuke panel_type
da2fd3b4d9c3 drm/i915/bios: Only use opregion panel index for display ver 8 and older
09e6d17ef019 drm/i915/display/tgl+: Use PPS index from vbt
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port()
2021-07-29 21:55 [Intel-gfx] [PATCH CI 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() José Roberto de Souza
` (9 preceding siblings ...)
2021-07-29 22:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() Patchwork
@ 2021-07-29 22:01 ` Patchwork
2021-07-29 22:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-30 9:19 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
12 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2021-07-29 22:01 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port()
URL : https://patchwork.freedesktop.org/series/93210/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1901:21: expected struct i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1901:21: got void [noderef] __iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1901:21: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1410:34: expected struct i915_address_space *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1410:34: got struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1410:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: expected struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: got struct i915_address_space *
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: expected struct i915_address_space *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: got struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1268:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/i915_perf.c:1443:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1497:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'xehp_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'xehp_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'xehp_fwtable_write8' - different lock contexts for basic block
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port()
2021-07-29 21:55 [Intel-gfx] [PATCH CI 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() José Roberto de Souza
` (10 preceding siblings ...)
2021-07-29 22:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-07-29 22:26 ` Patchwork
2021-07-30 9:19 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
12 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2021-07-29 22:26 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4554 bytes --]
== Series Details ==
Series: series starting with [CI,01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port()
URL : https://patchwork.freedesktop.org/series/93210/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10420 -> Patchwork_20745
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/index.html
Known issues
------------
Here are the changes found in Patchwork_20745 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +26 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-soraka: NOTRUN -> [FAIL][3] ([i915#579])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/fi-kbl-soraka/igt@i915_pm_rpm@basic-rte.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][4] ([i915#1886] / [i915#2291])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#533])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][7] ([i915#541]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
Participating hosts (39 -> 33)
------------------------------
Additional (1): fi-kbl-soraka
Missing (7): fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus bat-jsl-1
Build changes
-------------
* Linux: CI_DRM_10420 -> Patchwork_20745
CI-20190529: 20190529
CI_DRM_10420: 863957775825d20952875034f22937aec4a71a23 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6158: bb1c96b29234f86cd71d9cbd019aafada9097f24 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20745: 09e6d17ef019efe80f88ff8cca0a566e52220890 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
09e6d17ef019 drm/i915/display/tgl+: Use PPS index from vbt
da2fd3b4d9c3 drm/i915/bios: Only use opregion panel index for display ver 8 and older
32dda397f679 drm/i915/bios: Nuke panel_type
dae060ccab5f drm/i915/bios: Enable parse of two DSI panels data
4b6c19a53732 drm/i915/bios: Enable parse of two integrated panels PSR data
75d73519ca13 drm/i915/bios: Enable parse of two integrated panels eDP data
08c75431bf45 drm/i915/bios: Enable parse of two integrated panels backlight data
8533acd4179c drm/i915/bios: Enable parse of two integrated panels timing data
db14d408c50c drm/i915/bios: Start to support two integrated panels
311c3d22baba drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/index.html
[-- Attachment #1.2: Type: text/html, Size: 5580 bytes --]
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port()
2021-07-29 21:55 [Intel-gfx] [PATCH CI 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() José Roberto de Souza
` (11 preceding siblings ...)
2021-07-29 22:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-07-30 9:19 ` Patchwork
12 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2021-07-30 9:19 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30317 bytes --]
== Series Details ==
Series: series starting with [CI,01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port()
URL : https://patchwork.freedesktop.org/series/93210/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10420_full -> Patchwork_20745_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_20745_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@display-3x:
- shard-tglb: NOTRUN -> [SKIP][1] ([i915#1839])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-tglb6/igt@feature_discovery@display-3x.html
* igt@gem_ctx_persistence@legacy-engines-mixed:
- shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +4 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-snb7/igt@gem_ctx_persistence@legacy-engines-mixed.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][3] -> [TIMEOUT][4] ([i915#2369] / [i915#3063] / [i915#3648])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-tglb8/igt@gem_eio@unwedge-stress.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-tglb8/igt@gem_eio@unwedge-stress.html
- shard-snb: NOTRUN -> [FAIL][5] ([i915#3354])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-snb7/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][6] ([i915#2842])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-kbl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][7] -> [FAIL][8] ([i915#2842])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-iclb8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-iclb8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_params@no-vebox:
- shard-iclb: NOTRUN -> [SKIP][9] ([fdo#109283])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-iclb3/igt@gem_exec_params@no-vebox.html
* igt@gem_pwrite@basic-exhaustion:
- shard-apl: NOTRUN -> [WARN][10] ([i915#2658])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-apl2/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#3323])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-kbl4/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@input-checking:
- shard-snb: NOTRUN -> [DMESG-WARN][12] ([i915#3002])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-snb7/igt@gem_userptr_blits@input-checking.html
* igt@gen3_render_tiledx_blits:
- shard-tglb: NOTRUN -> [SKIP][13] ([fdo#109289])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-tglb6/igt@gen3_render_tiledx_blits.html
* igt@gen9_exec_parse@bb-start-param:
- shard-tglb: NOTRUN -> [SKIP][14] ([i915#2856])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-tglb6/igt@gen9_exec_parse@bb-start-param.html
* igt@i915_pm_dc@dc5-dpms:
- shard-kbl: NOTRUN -> [FAIL][15] ([i915#545]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-kbl6/igt@i915_pm_dc@dc5-dpms.html
- shard-skl: NOTRUN -> [FAIL][16] ([i915#545])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-skl9/igt@i915_pm_dc@dc5-dpms.html
* igt@i915_suspend@debugfs-reader:
- shard-apl: NOTRUN -> [DMESG-WARN][17] ([i915#180])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-apl2/igt@i915_suspend@debugfs-reader.html
* igt@i915_suspend@forcewake:
- shard-kbl: [PASS][18] -> [DMESG-WARN][19] ([i915#180]) +3 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-kbl2/igt@i915_suspend@forcewake.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-kbl7/igt@i915_suspend@forcewake.html
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#1769])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-iclb3/igt@kms_atomic_transition@plane-all-modeset-transition.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#3777]) +2 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-apl6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][22] ([fdo#109271]) +73 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-skl9/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][23] ([i915#3689])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-tglb6/igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@vga-hpd-without-ddc:
- shard-snb: NOTRUN -> [SKIP][24] ([fdo#109271] / [fdo#111827]) +23 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-snb7/igt@kms_chamelium@vga-hpd-without-ddc.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-kbl: NOTRUN -> [SKIP][25] ([fdo#109271] / [fdo#111827]) +7 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-kbl4/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-b-gamma:
- shard-iclb: NOTRUN -> [SKIP][26] ([fdo#109284] / [fdo#111827]) +2 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-iclb3/igt@kms_color_chamelium@pipe-b-gamma.html
* igt@kms_color_chamelium@pipe-c-ctm-0-25:
- shard-apl: NOTRUN -> [SKIP][27] ([fdo#109271] / [fdo#111827]) +28 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-apl1/igt@kms_color_chamelium@pipe-c-ctm-0-25.html
* igt@kms_color_chamelium@pipe-c-ctm-negative:
- shard-skl: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +5 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-skl7/igt@kms_color_chamelium@pipe-c-ctm-negative.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-iclb: NOTRUN -> [SKIP][29] ([i915#3116])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-iclb3/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@legacy:
- shard-kbl: NOTRUN -> [TIMEOUT][30] ([i915#1319])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-kbl4/igt@kms_content_protection@legacy.html
- shard-apl: NOTRUN -> [TIMEOUT][31] ([i915#1319])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-apl7/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-onscreen:
- shard-skl: [PASS][32] -> [FAIL][33] ([i915#3444])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-skl3/igt@kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-256x85-random:
- shard-apl: NOTRUN -> [FAIL][34] ([i915#3444])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html
* igt@kms_cursor_crc@pipe-c-cursor-32x10-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][35] ([i915#3359])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-tglb6/igt@kms_cursor_crc@pipe-c-cursor-32x10-rapid-movement.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-kbl: NOTRUN -> [SKIP][36] ([fdo#109271]) +123 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-kbl4/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
- shard-skl: [PASS][37] -> [FAIL][38] ([i915#2346])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
* igt@kms_cursor_legacy@pipe-d-torture-move:
- shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109278]) +6 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-iclb3/igt@kms_cursor_legacy@pipe-d-torture-move.html
* igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size:
- shard-skl: [PASS][40] -> [DMESG-WARN][41] ([i915#1982]) +4 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl10/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-skl1/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1:
- shard-skl: [PASS][42] -> [FAIL][43] ([i915#2122]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl2/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-skl3/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-apl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#2672])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-apl2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite:
- shard-snb: NOTRUN -> [SKIP][45] ([fdo#109271]) +396 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-2p-rte:
- shard-tglb: NOTRUN -> [SKIP][46] ([fdo#111825]) +6 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-2p-rte.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109280]) +3 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-iclb3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#533]) +3 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-apl2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: NOTRUN -> [FAIL][49] ([fdo#108145] / [i915#265])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][50] ([fdo#108145] / [i915#265]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-kbl: NOTRUN -> [FAIL][51] ([fdo#108145] / [i915#265])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-kbl4/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][52] ([i915#265])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-apl8/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][53] -> [FAIL][54] ([fdo#108145] / [i915#265]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_lowres@pipe-c-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][55] ([fdo#112054])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-tglb6/igt@kms_plane_lowres@pipe-c-tiling-yf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#658]) +6 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-apl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2:
- shard-kbl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#658])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-kbl4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: NOTRUN -> [SKIP][58] ([fdo#109642] / [fdo#111068] / [i915#658])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-iclb3/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-tglb: NOTRUN -> [FAIL][59] ([i915#132] / [i915#3467])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-tglb6/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [PASS][60] -> [SKIP][61] ([fdo#109441]) +2 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-iclb1/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#2437])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-apl7/igt@kms_writeback@writeback-check-output.html
* igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame:
- shard-apl: NOTRUN -> [SKIP][63] ([fdo#109271]) +323 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-apl3/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html
* igt@sysfs_clients@fair-1:
- shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#2994]) +3 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-apl6/igt@sysfs_clients@fair-1.html
* igt@sysfs_clients@fair-3:
- shard-kbl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#2994]) +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-kbl6/igt@sysfs_clients@fair-3.html
- shard-skl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#2994])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-skl9/igt@sysfs_clients@fair-3.html
* igt@sysfs_heartbeat_interval@precise@vecs0:
- shard-glk: [PASS][67] -> [FAIL][68] ([i915#1755])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-glk8/igt@sysfs_heartbeat_interval@precise@vecs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-glk8/igt@sysfs_heartbeat_interval@precise@vecs0.html
- shard-iclb: [PASS][69] -> [FAIL][70] ([i915#1755])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-iclb8/igt@sysfs_heartbeat_interval@precise@vecs0.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-iclb8/igt@sysfs_heartbeat_interval@precise@vecs0.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][71] ([i915#2842]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_workarounds@suspend-resume-context:
- shard-skl: [INCOMPLETE][73] ([i915#198]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl2/igt@gem_workarounds@suspend-resume-context.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-skl9/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_pm_backlight@bad-brightness:
- {shard-rkl}: [SKIP][75] ([i915#3012]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-1/igt@i915_pm_backlight@bad-brightness.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-rkl-6/igt@i915_pm_backlight@bad-brightness.html
* igt@i915_pm_backlight@fade_with_suspend:
- shard-skl: [INCOMPLETE][77] ([i915#146] / [i915#198]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl1/igt@i915_pm_backlight@fade_with_suspend.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-skl7/igt@i915_pm_backlight@fade_with_suspend.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][79] ([i915#454]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
* igt@kms_big_fb@linear-16bpp-rotate-180:
- {shard-rkl}: [SKIP][81] ([i915#3638]) -> [PASS][82] +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-1/igt@kms_big_fb@linear-16bpp-rotate-180.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-rkl-6/igt@kms_big_fb@linear-16bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180:
- {shard-rkl}: [SKIP][83] ([i915#3721]) -> [PASS][84] +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-iclb: [DMESG-WARN][85] ([i915#3621]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-iclb1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-iclb3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- {shard-rkl}: [FAIL][87] ([i915#3678]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-1/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-rkl-6/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_color@pipe-b-ctm-0-5:
- {shard-rkl}: [SKIP][89] ([i915#1149] / [i915#1849]) -> [PASS][90] +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-1/igt@kms_color@pipe-b-ctm-0-5.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-rkl-6/igt@kms_color@pipe-b-ctm-0-5.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding:
- {shard-rkl}: [SKIP][91] ([fdo#112022]) -> [PASS][92] +4 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-1/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
* igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic:
- {shard-rkl}: [SKIP][93] ([fdo#111825]) -> [PASS][94] +2 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-1/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
* igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled:
- {shard-rkl}: [SKIP][95] ([fdo#111314]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-1/igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][97] ([i915#79]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1:
- shard-glk: [FAIL][99] ([i915#2122]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: [DMESG-WARN][101] ([i915#180]) -> [PASS][102] +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-glk: [FAIL][103] ([i915#2546]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-glk5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-glk9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render:
- shard-tglb: [INCOMPLETE][105] -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
- {shard-rkl}: [SKIP][107] ([i915#1849]) -> [PASS][108] +8 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][109] ([i915#1188]) -> [PASS][110] +2 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-kbl: [DMESG-WARN][111] ([i915#180]) -> [PASS][112] +5 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][113] ([fdo#108145] / [i915#265]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@cursor_render:
- {shard-rkl}: [SKIP][115] ([i915#1072]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-1/igt@kms_psr@cursor_render.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-rkl-6/igt@kms_psr@cursor_render.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][117] ([fdo#109441]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-iclb7/igt@kms_psr@psr2_sprite_mmap_gtt.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_vblank@pipe-c-query-forked-hang:
- {shard-rkl}: [SKIP][119] ([i915#1845]) -> [PASS][120] +3 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-rkl-1/igt@kms_vblank@pipe-c-query-forked-hang.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-rkl-6/igt@kms_vblank@pipe-c-query-forked-hang.html
* igt@perf@polling-small-buf:
- shard-skl: [FAIL][121] ([i915#1722]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl6/igt@perf@polling-small-buf.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-skl7/igt@perf@polling-small-buf.html
* igt@sysfs_heartbeat_interval@precise@vecs0:
- shard-tglb: [FAIL][123] ([i915#1755]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-tglb1/igt@sysfs_heartbeat_interval@precise@vecs0.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-tglb1/igt@sysfs_heartbeat_interval@precise@vecs0.html
- shard-skl: [FAIL][125] ([i915#1755]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl9/igt@sysfs_heartbeat_interval@precise@vecs0.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-skl9/igt@sysfs_heartbeat_interval@precise@vecs0.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][127] ([i915#588]) -> [SKIP][128] ([i915#658])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-iclb1/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][129] ([i915#2684]) -> [WARN][130] ([i915#1804] / [i915#2684])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-iclb1/igt@i915_pm_rc6_residency@rc6-fence.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-iclb3/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: [FAIL][131] ([i915#3743]) -> [FAIL][132] ([i915#3722])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-skl2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-skl1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-3:
- shard-iclb: [SKIP][133] ([i915#2920]) -> [SKIP][134] ([i915#658]) +2 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-iclb1/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-iclb: [SKIP][135] ([i915#658]) -> [SKIP][136] ([i915#2920]) +1 similar issue
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-iclb4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2426] / [i915#2505] / [i915#3002] / [i915#3363]) -> ([FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151]) ([i915#180] / [i915#1814] / [i915#2426] / [i915#3002] / [i915#3363] / [i915#602])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-kbl6/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-kbl7/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-kbl7/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-kbl6/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-kbl1/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/shard-kbl3/igt@runner@aborted.html
[143]:
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20745/index.html
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-- links below jump to the message on this page --
2021-07-29 21:55 [Intel-gfx] [PATCH CI 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 02/10] drm/i915/bios: Start to support two integrated panels José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 03/10] drm/i915/bios: Enable parse of two integrated panels timing data José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 04/10] drm/i915/bios: Enable parse of two integrated panels backlight data José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 05/10] drm/i915/bios: Enable parse of two integrated panels eDP data José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 06/10] drm/i915/bios: Enable parse of two integrated panels PSR data José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 07/10] drm/i915/bios: Enable parse of two DSI panels data José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 08/10] drm/i915/bios: Nuke panel_type José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 09/10] drm/i915/bios: Only use opregion panel index for display ver 8 and older José Roberto de Souza
2021-07-29 21:55 ` [Intel-gfx] [PATCH CI 10/10] drm/i915/display/tgl+: Use PPS index from vbt José Roberto de Souza
2021-07-29 22:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port() Patchwork
2021-07-29 22:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-29 22:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-30 9:19 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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