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From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 07/14] drm/i915/guc/slpc: Add methods to set min/max frequency
Date: Thu, 29 Jul 2021 19:01:00 -0700	[thread overview]
Message-ID: <20210730020107.31415-8-vinay.belgaumkar@intel.com> (raw)
In-Reply-To: <20210730020107.31415-1-vinay.belgaumkar@intel.com>

Add param set h2g helpers to set the min and max frequencies
for use by SLPC.

v2: Address review comments (Michal W)
v3: Check for positive error code (Michal W)
v4: Print generic error in set_param (Michal W)

Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Sundaresan Sujaritha <sujaritha.sundaresan@intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 89 +++++++++++++++++++++
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h |  2 +
 2 files changed, 91 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index f26cf07ec87b..2635feb59576 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -111,6 +111,21 @@ static u32 slpc_get_state(struct intel_guc_slpc *slpc)
 	return data->header.global_state;
 }
 
+static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
+{
+	u32 request[] = {
+		GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
+		SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2),
+		id,
+		value,
+	};
+	int ret;
+
+	ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
+
+	return ret > 0 ? -EPROTO : ret;
+}
+
 static bool slpc_is_running(struct intel_guc_slpc *slpc)
 {
 	return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
@@ -148,6 +163,22 @@ static int slpc_query_task_state(struct intel_guc_slpc *slpc)
 	return ret;
 }
 
+static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
+{
+	struct intel_guc *guc = slpc_to_guc(slpc);
+	struct drm_i915_private *i915 = slpc_to_i915(slpc);
+	int ret;
+
+	GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+
+	ret = guc_action_slpc_set_param(guc, id, value);
+	if (ret)
+		drm_err(&i915->drm, "Failed to set param %d to %u (%pe)\n",
+			id, value, ERR_PTR(ret));
+
+	return ret;
+}
+
 static const char *slpc_global_state_to_string(enum slpc_global_state state)
 {
 	switch (state) {
@@ -231,6 +262,64 @@ static void slpc_shared_data_reset(struct slpc_shared_data *data)
 			      SLPC_PARAM_TASK_DISABLE_DCC);
 }
 
+/**
+ * intel_guc_slpc_set_max_freq() - Set max frequency limit for SLPC.
+ * @slpc: pointer to intel_guc_slpc.
+ * @val: frequency (MHz)
+ *
+ * This function will invoke GuC SLPC action to update the max frequency
+ * limit for unslice.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
+{
+	struct drm_i915_private *i915 = slpc_to_i915(slpc);
+	intel_wakeref_t wakeref;
+	int ret;
+
+	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+		ret = slpc_set_param(slpc,
+				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+				     val);
+
+		/* Return standardized err code for sysfs calls */
+		if (ret)
+			ret = -EIO;
+	}
+
+	return ret;
+}
+
+/**
+ * intel_guc_slpc_set_min_freq() - Set min frequency limit for SLPC.
+ * @slpc: pointer to intel_guc_slpc.
+ * @val: frequency (MHz)
+ *
+ * This function will invoke GuC SLPC action to update the min unslice
+ * frequency.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
+{
+	struct drm_i915_private *i915 = slpc_to_i915(slpc);
+	intel_wakeref_t wakeref;
+	int ret;
+
+	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+		ret = slpc_set_param(slpc,
+				     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+				     val);
+
+		/* Return standardized err code for sysfs calls */
+		if (ret)
+			ret = -EIO;
+	}
+
+	return ret;
+}
+
 /*
  * intel_guc_slpc_enable() - Start SLPC
  * @slpc: pointer to intel_guc_slpc.
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
index bc139682ad0f..788d87ff7b58 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
@@ -29,5 +29,7 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc);
 int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
 int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
 void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
+int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val);
+int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val);
 
 #endif
-- 
2.25.0

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  parent reply	other threads:[~2021-07-30  2:01 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-30  2:00 [Intel-gfx] [PATCH v5 00/14] drm/i915/guc/slpc: Enable GuC based power management features Vinay Belgaumkar
2021-07-30  2:00 ` [Intel-gfx] [PATCH 01/14] drm/i915/guc/slpc: Initial definitions for SLPC Vinay Belgaumkar
2021-07-30  2:00 ` [Intel-gfx] [PATCH 02/14] drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled Vinay Belgaumkar
2021-07-30  2:00 ` [Intel-gfx] [PATCH 03/14] drm/i915/guc/slpc: Adding SLPC communication interfaces Vinay Belgaumkar
2021-07-30  2:00 ` [Intel-gfx] [PATCH 04/14] drm/i915/guc/slpc: Allocate, initialize and release SLPC Vinay Belgaumkar
2021-07-30  2:00 ` [Intel-gfx] [PATCH 05/14] drm/i915/guc/slpc: Enable SLPC and add related H2G events Vinay Belgaumkar
2021-07-30  2:00 ` [Intel-gfx] [PATCH 06/14] drm/i915/guc/slpc: Remove BUG_ON in guc_submission_disable Vinay Belgaumkar
2021-07-30  2:01 ` Vinay Belgaumkar [this message]
2021-07-30  2:01 ` [Intel-gfx] [PATCH 08/14] drm/i915/guc/slpc: Add get max/min freq hooks Vinay Belgaumkar
2021-07-30  2:01 ` [Intel-gfx] [PATCH 09/14] drm/i915/guc/slpc: Add debugfs for SLPC info Vinay Belgaumkar
2021-07-30  2:01 ` [Intel-gfx] [PATCH 10/14] drm/i915/guc/slpc: Enable ARAT timer interrupt Vinay Belgaumkar
2021-07-30  2:01 ` [Intel-gfx] [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits Vinay Belgaumkar
2021-07-30  2:01 ` [Intel-gfx] [PATCH 12/14] drm/i915/guc/slpc: Sysfs hooks for SLPC Vinay Belgaumkar
2021-07-30  2:01 ` [Intel-gfx] [PATCH 13/14] drm/i915/guc/slpc: Add SLPC selftest Vinay Belgaumkar
2021-07-30 19:55   ` Matthew Brost
2021-07-30  2:01 ` [Intel-gfx] [PATCH 14/14] drm/i915/guc/rc: Setup and enable GuCRC feature Vinay Belgaumkar
2021-07-30  2:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc/slpc: Enable GuC based power management features (rev3) Patchwork
2021-07-30  2:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-30  3:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-30 11:37 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2021-07-30 20:21 [Intel-gfx] [PATCH v6 00/14] drm/i915/guc/slpc: Enable GuC based power management features Vinay Belgaumkar
2021-07-30 20:21 ` [Intel-gfx] [PATCH 07/14] drm/i915/guc/slpc: Add methods to set min/max frequency Vinay Belgaumkar
2021-07-28 21:11 [Intel-gfx] [PATCH v4 00/14] drm/i915/guc/slpc: Enable GuC based power management features Vinay Belgaumkar
2021-07-28 21:11 ` [Intel-gfx] [PATCH 07/14] drm/i915/guc/slpc: Add methods to set min/max frequency Vinay Belgaumkar
2021-07-29 16:33   ` Michal Wajdeczko
2021-07-21 16:11 [Intel-gfx] [PATCH v2 00/14] drm/i915/guc: Enable GuC based power management features Vinay Belgaumkar
2021-07-21 16:11 ` [Intel-gfx] [PATCH 07/14] drm/i915/guc/slpc: Add methods to set min/max frequency Vinay Belgaumkar
2021-07-21 17:42   ` Michal Wajdeczko
2021-07-23 19:35     ` Belgaumkar, Vinay

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