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* [Intel-gfx] [PATCH i-g-t v3 01/11] lib/i915/gem_mman: add FIXED mmap mode
@ 2021-07-30  8:53 Matthew Auld
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 02/11] lib/i915/gem_mman: add fixed mode to mmap__device_coherent Matthew Auld
                   ` (9 more replies)
  0 siblings, 10 replies; 16+ messages in thread
From: Matthew Auld @ 2021-07-30  8:53 UTC (permalink / raw)
  To: igt-dev; +Cc: Daniel Vetter, intel-gfx

We need this for discrete.

v2(Ashutosh):
 - use the new i915_drm_local.h infrastructure, and drop the LOCAL prefix

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ramalingam C <ramalingam.c@intel.com>
---
 lib/i915/gem_mman.c       | 36 ++++++++++++++++++++++++++++++++++++
 lib/i915/gem_mman.h       |  4 ++++
 lib/i915/i915_drm_local.h |  2 ++
 3 files changed, 42 insertions(+)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 4b4f2114..11df0d76 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -27,6 +27,7 @@
 #include <errno.h>
 
 #include "igt_core.h"
+#include "igt_gt.h"
 #include "igt_device.h"
 #include "ioctl_wrappers.h"
 #include "intel_chipset.h"
@@ -497,6 +498,41 @@ void *gem_mmap_offset__cpu(int fd, uint32_t handle, uint64_t offset,
 	return ptr;
 }
 
+void *__gem_mmap_offset__fixed(int fd, uint32_t handle, uint64_t offset,
+			       uint64_t size, unsigned prot)
+{
+	return __gem_mmap_offset(fd, handle, offset, size, prot,
+				 I915_MMAP_OFFSET_FIXED);
+}
+
+/**
+ * gem_mmap_offset__fixed: Used to mmap objects on discrete platforms
+ * @fd: open i915 drm file descriptor
+ * @handle: gem buffer object handle
+ * @offset: offset in the gem buffer of the mmap arena
+ * @size: size of the mmap arena
+ * @prot: memory protection bits as used by mmap()
+ *
+ * Like __gem_mmap_offset__fixed() except we assert on failure.
+ *
+ * For discrete the caching attributes for the pages are fixed at allocation
+ * time, and can't be changed. The FIXED mode will simply use the same caching *
+ * mode of the allocated pages. This mode will always be coherent with GPU
+ * access.
+ *
+ * On non-discrete platforms this mode is not supported.
+ *
+ * Returns: A pointer to the created memory mapping
+ */
+void *gem_mmap_offset__fixed(int fd, uint32_t handle, uint64_t offset,
+			   uint64_t size, unsigned prot)
+{
+	void *ptr = __gem_mmap_offset__fixed(fd, handle, offset, size, prot);
+
+	igt_assert(ptr);
+	return ptr;
+}
+
 /**
  * __gem_mmap__cpu_coherent:
  * @fd: open i915 drm file descriptor
diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h
index 5695d2ad..290c997d 100644
--- a/lib/i915/gem_mman.h
+++ b/lib/i915/gem_mman.h
@@ -37,6 +37,8 @@ bool gem_mmap_offset__has_wc(int fd);
 void *gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot);
 void *gem_mmap_offset__wc(int fd, uint32_t handle, uint64_t offset,
 			  uint64_t size, unsigned prot);
+void *gem_mmap_offset__fixed(int fd, uint32_t handle, uint64_t offset,
+			     uint64_t size, unsigned prot);
 void *gem_mmap__device_coherent(int fd, uint32_t handle, uint64_t offset,
 				uint64_t size, unsigned prot);
 void *gem_mmap__cpu_coherent(int fd, uint32_t handle, uint64_t offset,
@@ -54,6 +56,8 @@ void *__gem_mmap_offset__cpu(int fd, uint32_t handle, uint64_t offset,
 void *__gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot);
 void *__gem_mmap_offset__wc(int fd, uint32_t handle, uint64_t offset,
 			    uint64_t size, unsigned prot);
+void *__gem_mmap_offset__fixed(int fd, uint32_t handle, uint64_t offset,
+			       uint64_t size, unsigned prot);
 void *__gem_mmap__device_coherent(int fd, uint32_t handle, uint64_t offset,
 				  uint64_t size, unsigned prot);
 void *__gem_mmap_offset(int fd, uint32_t handle, uint64_t offset, uint64_t size,
diff --git a/lib/i915/i915_drm_local.h b/lib/i915/i915_drm_local.h
index dd646aed..0e3cef81 100644
--- a/lib/i915/i915_drm_local.h
+++ b/lib/i915/i915_drm_local.h
@@ -20,6 +20,8 @@ extern "C" {
  * clean these up when kernel uapi headers are sync'd.
  */
 
+#define I915_MMAP_OFFSET_FIXED 4
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.26.3

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [Intel-gfx] [PATCH i-g-t v3 02/11] lib/i915/gem_mman: add fixed mode to mmap__device_coherent
  2021-07-30  8:53 [Intel-gfx] [PATCH i-g-t v3 01/11] lib/i915/gem_mman: add FIXED mmap mode Matthew Auld
@ 2021-07-30  8:53 ` Matthew Auld
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 03/11] lib/i915/gem_mman: add fixed mode to gem_mmap_offset__cpu Matthew Auld
                   ` (8 subsequent siblings)
  9 siblings, 0 replies; 16+ messages in thread
From: Matthew Auld @ 2021-07-30  8:53 UTC (permalink / raw)
  To: igt-dev; +Cc: Daniel Vetter, intel-gfx

On discrete we need to fallback to this mode.

v2(Ashutosh):
 - Move it up the pecking order

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ramalingam C <ramalingam.c@intel.com>
---
 lib/i915/gem_mman.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 11df0d76..c432bb16 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -382,9 +382,11 @@ void *__gem_mmap__device_coherent(int fd, uint32_t handle, uint64_t offset,
 {
 	void *ptr = __gem_mmap_offset(fd, handle, offset, size, prot,
 				      I915_MMAP_OFFSET_WC);
+
+	if (!ptr)
+		ptr = __gem_mmap_offset__fixed(fd, handle, offset, size, prot);
 	if (!ptr)
 		ptr = __gem_mmap__wc(fd, handle, offset, size, prot);
-
 	if (!ptr)
 		ptr = __gem_mmap__gtt(fd, handle, size, prot);
 
-- 
2.26.3

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [Intel-gfx] [PATCH i-g-t v3 03/11] lib/i915/gem_mman: add fixed mode to gem_mmap_offset__cpu
  2021-07-30  8:53 [Intel-gfx] [PATCH i-g-t v3 01/11] lib/i915/gem_mman: add FIXED mmap mode Matthew Auld
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 02/11] lib/i915/gem_mman: add fixed mode to mmap__device_coherent Matthew Auld
@ 2021-07-30  8:53 ` Matthew Auld
  2021-08-02  6:29   ` Dixit, Ashutosh
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 04/11] lib/i915/gem_mman: add fixed mode to gem_mmap__cpu Matthew Auld
                   ` (7 subsequent siblings)
  9 siblings, 1 reply; 16+ messages in thread
From: Matthew Auld @ 2021-07-30  8:53 UTC (permalink / raw)
  To: igt-dev; +Cc: Daniel Vetter, intel-gfx

On discrete we only support the new fixed mode.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ramalingam C <ramalingam.c@intel.com>
---
 lib/i915/gem_mman.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index c432bb16..563a7ccf 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -474,8 +474,14 @@ void *gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, uns
 void *__gem_mmap_offset__cpu(int fd, uint32_t handle, uint64_t offset,
 			     uint64_t size, unsigned prot)
 {
-	return __gem_mmap_offset(fd, handle, offset, size, prot,
+	void *ptr;
+
+	ptr = __gem_mmap_offset(fd, handle, offset, size, prot,
 				 I915_MMAP_OFFSET_WB);
+	if (!ptr)
+		ptr = __gem_mmap_offset__fixed(fd, handle, offset, size, prot);
+
+	return ptr;
 }
 
 /**
-- 
2.26.3

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [Intel-gfx] [PATCH i-g-t v3 04/11] lib/i915/gem_mman: add fixed mode to gem_mmap__cpu
  2021-07-30  8:53 [Intel-gfx] [PATCH i-g-t v3 01/11] lib/i915/gem_mman: add FIXED mmap mode Matthew Auld
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 02/11] lib/i915/gem_mman: add fixed mode to mmap__device_coherent Matthew Auld
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 03/11] lib/i915/gem_mman: add fixed mode to gem_mmap_offset__cpu Matthew Auld
@ 2021-07-30  8:53 ` Matthew Auld
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 05/11] lib/i915/gem_mman: update mmap_offset_types with FIXED Matthew Auld
                   ` (6 subsequent siblings)
  9 siblings, 0 replies; 16+ messages in thread
From: Matthew Auld @ 2021-07-30  8:53 UTC (permalink / raw)
  To: igt-dev; +Cc: Daniel Vetter, intel-gfx

On discrete we only support the new fixed mode.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ramalingam C <ramalingam.c@intel.com>
---
 lib/i915/gem_mman.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 563a7ccf..c134e973 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -436,7 +436,13 @@ void *gem_mmap__device_coherent(int fd, uint32_t handle, uint64_t offset,
  */
 void *__gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot)
 {
-	return __gem_mmap(fd, handle, offset, size, prot, 0);
+	void *ptr;
+
+	ptr = __gem_mmap(fd, handle, offset, size, prot, 0);
+	if (!ptr)
+		ptr = __gem_mmap_offset__fixed(fd, handle, offset, size, prot);
+
+	return ptr;
 }
 
 /**
-- 
2.26.3

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [Intel-gfx] [PATCH i-g-t v3 05/11] lib/i915/gem_mman: update mmap_offset_types with FIXED
  2021-07-30  8:53 [Intel-gfx] [PATCH i-g-t v3 01/11] lib/i915/gem_mman: add FIXED mmap mode Matthew Auld
                   ` (2 preceding siblings ...)
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 04/11] lib/i915/gem_mman: add fixed mode to gem_mmap__cpu Matthew Auld
@ 2021-07-30  8:53 ` Matthew Auld
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 06/11] lib/ioctl_wrappers: update mmap_{read, write} for discrete Matthew Auld
                   ` (5 subsequent siblings)
  9 siblings, 0 replies; 16+ messages in thread
From: Matthew Auld @ 2021-07-30  8:53 UTC (permalink / raw)
  To: igt-dev; +Cc: Daniel Vetter, intel-gfx

We need to also iterate the fixed mode in the tests which rely on this.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ramalingam C <ramalingam.c@intel.com>
---
 lib/i915/gem_mman.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index c134e973..c69dc6f5 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -621,6 +621,7 @@ const struct mmap_offset mmap_offset_types[] = {
 	{ "wb", I915_MMAP_OFFSET_WB, I915_GEM_DOMAIN_CPU },
 	{ "wc", I915_MMAP_OFFSET_WC, I915_GEM_DOMAIN_WC },
 	{ "uc", I915_MMAP_OFFSET_UC, I915_GEM_DOMAIN_WC },
+	{ "fixed", I915_MMAP_OFFSET_FIXED, 0},
 	{},
 };
 
-- 
2.26.3

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [Intel-gfx] [PATCH i-g-t v3 06/11] lib/ioctl_wrappers: update mmap_{read, write} for discrete
  2021-07-30  8:53 [Intel-gfx] [PATCH i-g-t v3 01/11] lib/i915/gem_mman: add FIXED mmap mode Matthew Auld
                   ` (3 preceding siblings ...)
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 05/11] lib/i915/gem_mman: update mmap_offset_types with FIXED Matthew Auld
@ 2021-07-30  8:53 ` Matthew Auld
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 07/11] lib/intel_bufops: " Matthew Auld
                   ` (4 subsequent siblings)
  9 siblings, 0 replies; 16+ messages in thread
From: Matthew Auld @ 2021-07-30  8:53 UTC (permalink / raw)
  To: igt-dev; +Cc: Daniel Vetter, intel-gfx

We can no longer just call get_caching or set_domain, and the mmap mode
must be FIXED. This should bring back gem_exec_basic and a few others in
CI on DG1.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ramalingam C <ramalingam.c@intel.com>
---
 lib/ioctl_wrappers.c | 25 +++++++++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 25c5e495..7e27a1b3 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -339,7 +339,18 @@ static void mmap_write(int fd, uint32_t handle, uint64_t offset,
 	if (!length)
 		return;
 
-	if (is_cache_coherent(fd, handle)) {
+	if (gem_has_lmem(fd)) {
+		/*
+		 * set/get_caching and set_domain are no longer supported on
+		 * discrete, also the only mmap mode supportd is FIXED.
+		 */
+		map = gem_mmap_offset__fixed(fd, handle, 0,
+					     offset + length,
+					     PROT_READ | PROT_WRITE);
+		igt_assert_eq(gem_wait(fd, handle, 0), 0);
+	}
+
+	if (!map && is_cache_coherent(fd, handle)) {
 		/* offset arg for mmap functions must be 0 */
 		map = __gem_mmap__cpu_coherent(fd, handle, 0, offset + length,
 					       PROT_READ | PROT_WRITE);
@@ -369,7 +380,17 @@ static void mmap_read(int fd, uint32_t handle, uint64_t offset, void *buf, uint6
 	if (!length)
 		return;
 
-	if (gem_has_llc(fd) || is_cache_coherent(fd, handle)) {
+	if (gem_has_lmem(fd)) {
+		/*
+		 * set/get_caching and set_domain are no longer supported on
+		 * discrete, also the only supported mmap mode is FIXED.
+		 */
+		map = gem_mmap_offset__fixed(fd, handle, 0,
+					     offset + length, PROT_READ);
+		igt_assert_eq(gem_wait(fd, handle, 0), 0);
+	}
+
+	if (!map && (gem_has_llc(fd) || is_cache_coherent(fd, handle))) {
 		/* offset arg for mmap functions must be 0 */
 		map = __gem_mmap__cpu_coherent(fd, handle, 0,
 					       offset + length, PROT_READ);
-- 
2.26.3

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [Intel-gfx] [PATCH i-g-t v3 07/11] lib/intel_bufops: update mmap_{read, write} for discrete
  2021-07-30  8:53 [Intel-gfx] [PATCH i-g-t v3 01/11] lib/i915/gem_mman: add FIXED mmap mode Matthew Auld
                   ` (4 preceding siblings ...)
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 06/11] lib/ioctl_wrappers: update mmap_{read, write} for discrete Matthew Auld
@ 2021-07-30  8:53 ` Matthew Auld
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 08/11] lib/ioctl_wrappers: update set_domain " Matthew Auld
                   ` (3 subsequent siblings)
  9 siblings, 0 replies; 16+ messages in thread
From: Matthew Auld @ 2021-07-30  8:53 UTC (permalink / raw)
  To: igt-dev; +Cc: Daniel Vetter, intel-gfx

On discrete we can no longer call get_caching or set_domain, and the
mmap mode must be FIXED.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ramalingam C <ramalingam.c@intel.com>
---
 lib/intel_bufops.c | 25 +++++++++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index 3ce68663..faca4406 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -424,7 +424,18 @@ static void *mmap_write(int fd, struct intel_buf *buf)
 {
 	void *map = NULL;
 
-	if (is_cache_coherent(fd, buf->handle)) {
+	if (gem_has_lmem(fd)) {
+		/*
+		 * set/get_caching and set_domain are no longer supported on
+		 * discrete, also the only mmap mode supportd is FIXED.
+		 */
+		map = gem_mmap_offset__fixed(fd, buf->handle, 0,
+					     buf->surface[0].size,
+					     PROT_READ | PROT_WRITE);
+		igt_assert_eq(gem_wait(fd, buf->handle, 0), 0);
+	}
+
+	if (!map && is_cache_coherent(fd, buf->handle)) {
 		map = __gem_mmap_offset__cpu(fd, buf->handle, 0, buf->surface[0].size,
 					     PROT_READ | PROT_WRITE);
 		if (!map)
@@ -455,7 +466,17 @@ static void *mmap_read(int fd, struct intel_buf *buf)
 {
 	void *map = NULL;
 
-	if (gem_has_llc(fd) || is_cache_coherent(fd, buf->handle)) {
+	if (gem_has_lmem(fd)) {
+		/*
+		 * set/get_caching and set_domain are no longer supported on
+		 * discrete, also the only supported mmap mode is FIXED.
+		 */
+		map = gem_mmap_offset__fixed(fd, buf->handle, 0,
+					     buf->surface[0].size, PROT_READ);
+		igt_assert_eq(gem_wait(fd, buf->handle, 0), 0);
+	}
+
+	if (!map && (gem_has_llc(fd) || is_cache_coherent(fd, buf->handle))) {
 		map = __gem_mmap_offset__cpu(fd, buf->handle, 0,
 					     buf->surface[0].size, PROT_READ);
 		if (!map)
-- 
2.26.3

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [Intel-gfx] [PATCH i-g-t v3 08/11] lib/ioctl_wrappers: update set_domain for discrete
  2021-07-30  8:53 [Intel-gfx] [PATCH i-g-t v3 01/11] lib/i915/gem_mman: add FIXED mmap mode Matthew Auld
                   ` (5 preceding siblings ...)
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 07/11] lib/intel_bufops: " Matthew Auld
@ 2021-07-30  8:53 ` Matthew Auld
  2021-08-02  6:24   ` Dixit, Ashutosh
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 09/11] tests/i915/module_load: update " Matthew Auld
                   ` (2 subsequent siblings)
  9 siblings, 1 reply; 16+ messages in thread
From: Matthew Auld @ 2021-07-30  8:53 UTC (permalink / raw)
  To: igt-dev; +Cc: Daniel Vetter, intel-gfx

On discrete set_domain is now gone, instead we just need to add the
wait.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ramalingam C <ramalingam.c@intel.com>
---
 lib/ioctl_wrappers.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 7e27a1b3..09eb3ce7 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -565,7 +565,12 @@ int __gem_set_domain(int fd, uint32_t handle, uint32_t read, uint32_t write)
  */
 void gem_set_domain(int fd, uint32_t handle, uint32_t read, uint32_t write)
 {
-	igt_assert_eq(__gem_set_domain(fd, handle, read, write), 0);
+	int ret = __gem_set_domain(fd, handle, read, write);
+
+	if (ret == -ENODEV && gem_has_lmem(fd))
+		igt_assert_eq(gem_wait(fd, handle, 0), 0);
+	else
+		igt_assert_eq(ret, 0);
 }
 
 /**
-- 
2.26.3

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [Intel-gfx] [PATCH i-g-t v3 09/11] tests/i915/module_load: update for discrete
  2021-07-30  8:53 [Intel-gfx] [PATCH i-g-t v3 01/11] lib/i915/gem_mman: add FIXED mmap mode Matthew Auld
                   ` (6 preceding siblings ...)
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 08/11] lib/ioctl_wrappers: update set_domain " Matthew Auld
@ 2021-07-30  8:53 ` Matthew Auld
  2021-08-02  6:25   ` Dixit, Ashutosh
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 10/11] lib/i915/gem_mman: add helper query for has_device_coherent Matthew Auld
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 11/11] tests/i915/gem_exec_fence: use device_coherent mmap Matthew Auld
  9 siblings, 1 reply; 16+ messages in thread
From: Matthew Auld @ 2021-07-30  8:53 UTC (permalink / raw)
  To: igt-dev; +Cc: Daniel Vetter, intel-gfx

The set_caching ioctl is gone for discrete, and now just returns
-ENODEV. Update the gem_sanitycheck to account for that. After this we
should be back to just having the breakage caused by missing reloc
support for the reload testcase.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ramalingam C <ramalingam.c@intel.com>
---
 tests/i915/i915_module_load.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/tests/i915/i915_module_load.c b/tests/i915/i915_module_load.c
index 98ceb5d8..4b42fe3e 100644
--- a/tests/i915/i915_module_load.c
+++ b/tests/i915/i915_module_load.c
@@ -172,17 +172,22 @@ static void gem_sanitycheck(void)
 {
 	struct drm_i915_gem_caching args = {};
 	int i915 = __drm_open_driver(DRIVER_INTEL);
+	int expected;
 	int err;
 
+	expected = -ENOENT;
+	if (gem_has_lmem(i915))
+		expected = -ENODEV;
+
 	err = 0;
 	if (ioctl(i915, DRM_IOCTL_I915_GEM_SET_CACHING, &args))
 		err = -errno;
-	if (err == -ENOENT)
+	if (err == expected)
 		store_all(i915);
 	errno = 0;
 
 	close(i915);
-	igt_assert_eq(err, -ENOENT);
+	igt_assert_eq(err, expected);
 }
 
 static void
-- 
2.26.3

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [Intel-gfx] [PATCH i-g-t v3 10/11] lib/i915/gem_mman: add helper query for has_device_coherent
  2021-07-30  8:53 [Intel-gfx] [PATCH i-g-t v3 01/11] lib/i915/gem_mman: add FIXED mmap mode Matthew Auld
                   ` (7 preceding siblings ...)
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 09/11] tests/i915/module_load: update " Matthew Auld
@ 2021-07-30  8:53 ` Matthew Auld
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 11/11] tests/i915/gem_exec_fence: use device_coherent mmap Matthew Auld
  9 siblings, 0 replies; 16+ messages in thread
From: Matthew Auld @ 2021-07-30  8:53 UTC (permalink / raw)
  To: igt-dev; +Cc: Daniel Vetter, intel-gfx

Might be useful in some tests, where we are not explicitly testing WC
maps, but rather just require something that is "device coherent", which
should also play nice on discrete platforms.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ramalingam C <ramalingam.c@intel.com>
---
 lib/i915/gem_mman.c | 39 +++++++++++++++++++++++++++++++++++++++
 lib/i915/gem_mman.h | 11 +++++++++++
 2 files changed, 50 insertions(+)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index c69dc6f5..0406a0b9 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -197,6 +197,45 @@ bool gem_mmap_offset__has_wc(int fd)
 	return has_wc > 0;
 }
 
+bool gem_mmap__has_device_coherent(int fd)
+{
+	struct drm_i915_gem_mmap_offset arg;
+	bool supported;
+
+	if (gem_mmap__has_wc(fd))
+		return true;
+
+	/* Maybe we still have GTT mmaps? */
+	memset(&arg, 0, sizeof(arg));
+	arg.handle = gem_create(fd, 4096);
+	arg.offset = 0;
+	arg.flags = I915_MMAP_OFFSET_GTT;
+	supported = igt_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP_OFFSET,
+			      &arg) == 0;
+	gem_close(fd, arg.handle);
+
+	errno = 0;
+
+	if (supported)
+		return true;
+
+	/*
+	 * Maybe this is a discrete device, which only supports fixed mmaps?
+	 * Such mappings should also be considered device coherent.
+	 */
+	memset(&arg, 0, sizeof(arg));
+	arg.handle = gem_create(fd, 4096);
+	arg.offset = 0;
+	arg.flags = I915_MMAP_OFFSET_FIXED;
+	supported = igt_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP_OFFSET,
+			      &arg) == 0;
+	gem_close(fd, arg.handle);
+
+	errno = 0;
+
+	return supported;
+}
+
 /**
  * __gem_mmap:
  * @fd: open i915 drm file descriptor
diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h
index 290c997d..5966ddb5 100644
--- a/lib/i915/gem_mman.h
+++ b/lib/i915/gem_mman.h
@@ -41,6 +41,7 @@ void *gem_mmap_offset__fixed(int fd, uint32_t handle, uint64_t offset,
 			     uint64_t size, unsigned prot);
 void *gem_mmap__device_coherent(int fd, uint32_t handle, uint64_t offset,
 				uint64_t size, unsigned prot);
+bool gem_mmap__has_device_coherent(int fd);
 void *gem_mmap__cpu_coherent(int fd, uint32_t handle, uint64_t offset,
 			     uint64_t size, unsigned prot);
 
@@ -96,6 +97,16 @@ int gem_munmap(void *ptr, uint64_t size);
  */
 #define gem_require_mmap_offset_wc(fd) igt_require(gem_mmap_offset__has_wc(fd))
 
+/**
+ * gem_require_mmap_offset_device_coherent:
+ * @fd: open i915 drm file descriptor
+ *
+ * Feature test macro to query whether direct (i.e. cpu access path, bypassing
+ * the gtt) write-combine memory mappings are available, or fixed mapping for
+ * discrete. Automatically skips through igt_require() if not.
+ */
+#define gem_require_mmap_device_coherent(fd) igt_require(gem_mmap__has_device_coherent(fd))
+
 extern const struct mmap_offset {
 	const char *name;
 	unsigned int type;
-- 
2.26.3

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [Intel-gfx] [PATCH i-g-t v3 11/11] tests/i915/gem_exec_fence: use device_coherent mmap
  2021-07-30  8:53 [Intel-gfx] [PATCH i-g-t v3 01/11] lib/i915/gem_mman: add FIXED mmap mode Matthew Auld
                   ` (8 preceding siblings ...)
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 10/11] lib/i915/gem_mman: add helper query for has_device_coherent Matthew Auld
@ 2021-07-30  8:53 ` Matthew Auld
  9 siblings, 0 replies; 16+ messages in thread
From: Matthew Auld @ 2021-07-30  8:53 UTC (permalink / raw)
  To: igt-dev; +Cc: Daniel Vetter, intel-gfx

We lost explicit WC mmaps on discrete, where we now only support FIXED,
however such mappings should be device coherent. In gem_exec_fence it
looks like we can just use mmap__device_coherent, which should also work
on discrete platforms, while still using an explicit WC mmap on
integrated platforms.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ramalingam C <ramalingam.c@intel.com>
---
 tests/i915/gem_exec_fence.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
index ef1bb0ca..620e7ac2 100644
--- a/tests/i915/gem_exec_fence.c
+++ b/tests/i915/gem_exec_fence.c
@@ -152,7 +152,7 @@ static void test_fence_busy(int fd, const intel_ctx_t *ctx,
 	obj.relocation_count = 1;
 	memset(&reloc, 0, sizeof(reloc));
 
-	batch = gem_mmap__wc(fd, obj.handle, 0, 4096, PROT_WRITE);
+	batch = gem_mmap__device_coherent(fd, obj.handle, 0, 4096, PROT_WRITE);
 	gem_set_domain(fd, obj.handle,
 		       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
 
@@ -244,7 +244,7 @@ static void test_fence_busy_all(int fd, const intel_ctx_t *ctx, unsigned flags)
 	obj.relocation_count = 1;
 	memset(&reloc, 0, sizeof(reloc));
 
-	batch = gem_mmap__wc(fd, obj.handle, 0, 4096, PROT_WRITE);
+	batch = gem_mmap__device_coherent(fd, obj.handle, 0, 4096, PROT_WRITE);
 	gem_set_domain(fd, obj.handle,
 		       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
 
@@ -353,7 +353,7 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx,
 	uint32_t *out;
 	int i;
 
-	out = gem_mmap__wc(fd, scratch, 0, 4096, PROT_WRITE);
+	out = gem_mmap__device_coherent(fd, scratch, 0, 4096, PROT_WRITE);
 	gem_set_domain(fd, scratch,
 			I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
 
@@ -617,7 +617,7 @@ static void test_parallel(int i915, const intel_ctx_t *ctx,
 	const struct intel_execution_engine2 *e2;
 	const unsigned int gen = intel_gen(intel_get_drm_devid(i915));
 	uint32_t scratch = gem_create(i915, 4096);
-	uint32_t *out = gem_mmap__wc(i915, scratch, 0, 4096, PROT_READ);
+	uint32_t *out = gem_mmap__device_coherent(i915, scratch, 0, 4096, PROT_READ);
 	uint32_t handle[I915_EXEC_RING_MASK];
 	IGT_CORK_FENCE(cork);
 	igt_spin_t *spin;
@@ -2813,7 +2813,7 @@ static void test_syncobj_timeline_chain_engines(int fd, const intel_ctx_cfg_t *c
 
 	gem_sync(fd, ctx.engine_counter_object.handle);
 
-	counter_output = gem_mmap__wc(fd, ctx.engine_counter_object.handle, 0, 4096, PROT_READ);
+	counter_output = gem_mmap__device_coherent(fd, ctx.engine_counter_object.handle, 0, 4096, PROT_READ);
 
 	for (uint32_t i = 0; i < ctx.engines.nengines; i++)
 		igt_debug("engine %i (%s)\t= %016"PRIx64"\n", i,
@@ -2879,7 +2879,7 @@ static void test_syncobj_stationary_timeline_chain_engines(int fd, const intel_c
 
 	gem_sync(fd, ctx.engine_counter_object.handle);
 
-	counter_output = gem_mmap__wc(fd, ctx.engine_counter_object.handle, 0, 4096, PROT_READ);
+	counter_output = gem_mmap__device_coherent(fd, ctx.engine_counter_object.handle, 0, 4096, PROT_READ);
 
 	for (uint32_t i = 0; i < ctx.engines.nengines; i++)
 		igt_debug("engine %i (%s)\t= %016"PRIx64"\n", i,
@@ -2940,7 +2940,7 @@ static void test_syncobj_backward_timeline_chain_engines(int fd, const intel_ctx
 
 	gem_sync(fd, ctx.engine_counter_object.handle);
 
-	counter_output = gem_mmap__wc(fd, ctx.engine_counter_object.handle, 0, 4096, PROT_READ);
+	counter_output = gem_mmap__device_coherent(fd, ctx.engine_counter_object.handle, 0, 4096, PROT_READ);
 
 	for (uint32_t i = 0; i < ctx.engines.nengines; i++)
 		igt_debug("engine %i (%s)\t= %016"PRIx64"\n", i,
@@ -2963,7 +2963,7 @@ igt_main
 		i915 = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(i915);
 		igt_require(gem_has_exec_fence(i915));
-		gem_require_mmap_wc(i915);
+		gem_require_mmap_device_coherent(i915);
 		ctx = intel_ctx_create_all_physical(i915);
 
 		gem_submission_print_method(i915);
-- 
2.26.3

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [Intel-gfx] [PATCH i-g-t v3 08/11] lib/ioctl_wrappers: update set_domain for discrete
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 08/11] lib/ioctl_wrappers: update set_domain " Matthew Auld
@ 2021-08-02  6:24   ` Dixit, Ashutosh
  0 siblings, 0 replies; 16+ messages in thread
From: Dixit, Ashutosh @ 2021-08-02  6:24 UTC (permalink / raw)
  To: Matthew Auld
  Cc: igt-dev, intel-gfx, Maarten Lankhorst, Daniel Vetter, Ramalingam C

On Fri, 30 Jul 2021 01:53:45 -0700, Matthew Auld wrote:
>
> On discrete set_domain is now gone, instead we just need to add the
> wait.

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> ---
>  lib/ioctl_wrappers.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
> index 7e27a1b3..09eb3ce7 100644
> --- a/lib/ioctl_wrappers.c
> +++ b/lib/ioctl_wrappers.c
> @@ -565,7 +565,12 @@ int __gem_set_domain(int fd, uint32_t handle, uint32_t read, uint32_t write)
>   */
>  void gem_set_domain(int fd, uint32_t handle, uint32_t read, uint32_t write)
>  {
> -	igt_assert_eq(__gem_set_domain(fd, handle, read, write), 0);
> +	int ret = __gem_set_domain(fd, handle, read, write);
> +
> +	if (ret == -ENODEV && gem_has_lmem(fd))
> +		igt_assert_eq(gem_wait(fd, handle, 0), 0);
> +	else
> +		igt_assert_eq(ret, 0);
>  }
>
>  /**
> --
> 2.26.3
>

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [Intel-gfx] [PATCH i-g-t v3 09/11] tests/i915/module_load: update for discrete
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 09/11] tests/i915/module_load: update " Matthew Auld
@ 2021-08-02  6:25   ` Dixit, Ashutosh
  0 siblings, 0 replies; 16+ messages in thread
From: Dixit, Ashutosh @ 2021-08-02  6:25 UTC (permalink / raw)
  To: Matthew Auld
  Cc: igt-dev, intel-gfx, Maarten Lankhorst, Daniel Vetter, Ramalingam C

On Fri, 30 Jul 2021 01:53:46 -0700, Matthew Auld wrote:
>
> The set_caching ioctl is gone for discrete, and now just returns
> -ENODEV. Update the gem_sanitycheck to account for that. After this we
> should be back to just having the breakage caused by missing reloc
> support for the reload testcase.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> ---
>  tests/i915/i915_module_load.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/tests/i915/i915_module_load.c b/tests/i915/i915_module_load.c
> index 98ceb5d8..4b42fe3e 100644
> --- a/tests/i915/i915_module_load.c
> +++ b/tests/i915/i915_module_load.c
> @@ -172,17 +172,22 @@ static void gem_sanitycheck(void)
>  {
>	struct drm_i915_gem_caching args = {};
>	int i915 = __drm_open_driver(DRIVER_INTEL);
> +	int expected;

If we want to reduce a couple of line of code this is:

int expected = gem_has_lmem(i915) ? -ENODEV : -ENOENT;

Otherwise this is:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

>	int err;
>
> +	expected = -ENOENT;
> +	if (gem_has_lmem(i915))
> +		expected = -ENODEV;
> +
>	err = 0;
>	if (ioctl(i915, DRM_IOCTL_I915_GEM_SET_CACHING, &args))
>		err = -errno;
> -	if (err == -ENOENT)
> +	if (err == expected)
>		store_all(i915);
>	errno = 0;
>
>	close(i915);
> -	igt_assert_eq(err, -ENOENT);
> +	igt_assert_eq(err, expected);
>  }
>
>  static void
> --
> 2.26.3
>

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [Intel-gfx] [PATCH i-g-t v3 03/11] lib/i915/gem_mman: add fixed mode to gem_mmap_offset__cpu
  2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 03/11] lib/i915/gem_mman: add fixed mode to gem_mmap_offset__cpu Matthew Auld
@ 2021-08-02  6:29   ` Dixit, Ashutosh
  2021-08-06 10:00     ` Maarten Lankhorst
  2021-08-06 10:10     ` Maarten Lankhorst
  0 siblings, 2 replies; 16+ messages in thread
From: Dixit, Ashutosh @ 2021-08-02  6:29 UTC (permalink / raw)
  To: Matthew Auld
  Cc: igt-dev, intel-gfx, Maarten Lankhorst, Daniel Vetter, Ramalingam C

On Fri, 30 Jul 2021 01:53:40 -0700, Matthew Auld wrote:
>
> On discrete we only support the new fixed mode.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> ---
>  lib/i915/gem_mman.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
> index c432bb16..563a7ccf 100644
> --- a/lib/i915/gem_mman.c
> +++ b/lib/i915/gem_mman.c
> @@ -474,8 +474,14 @@ void *gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, uns
>  void *__gem_mmap_offset__cpu(int fd, uint32_t handle, uint64_t offset,
>			     uint64_t size, unsigned prot)
>  {
> -	return __gem_mmap_offset(fd, handle, offset, size, prot,
> +	void *ptr;
> +
> +	ptr = __gem_mmap_offset(fd, handle, offset, size, prot,
>				 I915_MMAP_OFFSET_WB);
> +	if (!ptr)
> +		ptr = __gem_mmap_offset__fixed(fd, handle, offset, size, prot);
> +
> +	return ptr;

Imo there's some asymmetry here. If we are adding fixed mode to
mmap__device_coherent (in the previous patch) then we should also be adding
it to mmap__cpu_coherent (as before). Or, if we are adding fixed mode to
__gem_mmap_offset__cpu we should also be adding it to
__gem_mmap_offset__wc. Thanks.

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [Intel-gfx] [PATCH i-g-t v3 03/11] lib/i915/gem_mman: add fixed mode to gem_mmap_offset__cpu
  2021-08-02  6:29   ` Dixit, Ashutosh
@ 2021-08-06 10:00     ` Maarten Lankhorst
  2021-08-06 10:10     ` Maarten Lankhorst
  1 sibling, 0 replies; 16+ messages in thread
From: Maarten Lankhorst @ 2021-08-06 10:00 UTC (permalink / raw)
  To: Dixit, Ashutosh, Matthew Auld
  Cc: igt-dev, intel-gfx, Daniel Vetter, Ramalingam C

Op 02-08-2021 om 08:29 schreef Dixit, Ashutosh:
> On Fri, 30 Jul 2021 01:53:40 -0700, Matthew Auld wrote:
>> On discrete we only support the new fixed mode.
>>
>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
>> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
>> Cc: Ramalingam C <ramalingam.c@intel.com>
>> ---
>>  lib/i915/gem_mman.c | 8 +++++++-
>>  1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
>> index c432bb16..563a7ccf 100644
>> --- a/lib/i915/gem_mman.c
>> +++ b/lib/i915/gem_mman.c
>> @@ -474,8 +474,14 @@ void *gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, uns
>>  void *__gem_mmap_offset__cpu(int fd, uint32_t handle, uint64_t offset,
>> 			     uint64_t size, unsigned prot)
>>  {
>> -	return __gem_mmap_offset(fd, handle, offset, size, prot,
>> +	void *ptr;
>> +
>> +	ptr = __gem_mmap_offset(fd, handle, offset, size, prot,
>> 				 I915_MMAP_OFFSET_WB);
>> +	if (!ptr)
>> +		ptr = __gem_mmap_offset__fixed(fd, handle, offset, size, prot);
>> +
>> +	return ptr;
> Imo there's some asymmetry here. If we are adding fixed mode to
> mmap__device_coherent (in the previous patch) then we should also be adding
> it to mmap__cpu_coherent (as before). Or, if we are adding fixed mode to
> __gem_mmap_offset__cpu we should also be adding it to
> __gem_mmap_offset__wc. Thanks.

I've applied the patch series for now. Not sure I agree on adding it to __gem_mmap_offset__wc, but if there's a need, we could do that. :)


^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [Intel-gfx] [PATCH i-g-t v3 03/11] lib/i915/gem_mman: add fixed mode to gem_mmap_offset__cpu
  2021-08-02  6:29   ` Dixit, Ashutosh
  2021-08-06 10:00     ` Maarten Lankhorst
@ 2021-08-06 10:10     ` Maarten Lankhorst
  1 sibling, 0 replies; 16+ messages in thread
From: Maarten Lankhorst @ 2021-08-06 10:10 UTC (permalink / raw)
  To: Dixit, Ashutosh, Matthew Auld
  Cc: igt-dev, intel-gfx, Daniel Vetter, Ramalingam C

Op 02-08-2021 om 08:29 schreef Dixit, Ashutosh:
> On Fri, 30 Jul 2021 01:53:40 -0700, Matthew Auld wrote:
>> On discrete we only support the new fixed mode.
>>
>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
>> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
>> Cc: Ramalingam C <ramalingam.c@intel.com>
>> ---
>>  lib/i915/gem_mman.c | 8 +++++++-
>>  1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
>> index c432bb16..563a7ccf 100644
>> --- a/lib/i915/gem_mman.c
>> +++ b/lib/i915/gem_mman.c
>> @@ -474,8 +474,14 @@ void *gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, uns
>>  void *__gem_mmap_offset__cpu(int fd, uint32_t handle, uint64_t offset,
>> 			     uint64_t size, unsigned prot)
>>  {
>> -	return __gem_mmap_offset(fd, handle, offset, size, prot,
>> +	void *ptr;
>> +
>> +	ptr = __gem_mmap_offset(fd, handle, offset, size, prot,
>> 				 I915_MMAP_OFFSET_WB);
>> +	if (!ptr)
>> +		ptr = __gem_mmap_offset__fixed(fd, handle, offset, size, prot);
>> +
>> +	return ptr;
> Imo there's some asymmetry here. If we are adding fixed mode to
> mmap__device_coherent (in the previous patch) then we should also be adding
> it to mmap__cpu_coherent (as before). Or, if we are adding fixed mode to
> __gem_mmap_offset__cpu we should also be adding it to
> __gem_mmap_offset__wc. Thanks.

Why do we need it in __gem_mmap_offset_wc btw?

Rest of series doesn't seem to be blocked by it, so pushed for now.


^ permalink raw reply	[flat|nested] 16+ messages in thread

end of thread, other threads:[~2021-08-06 10:11 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-30  8:53 [Intel-gfx] [PATCH i-g-t v3 01/11] lib/i915/gem_mman: add FIXED mmap mode Matthew Auld
2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 02/11] lib/i915/gem_mman: add fixed mode to mmap__device_coherent Matthew Auld
2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 03/11] lib/i915/gem_mman: add fixed mode to gem_mmap_offset__cpu Matthew Auld
2021-08-02  6:29   ` Dixit, Ashutosh
2021-08-06 10:00     ` Maarten Lankhorst
2021-08-06 10:10     ` Maarten Lankhorst
2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 04/11] lib/i915/gem_mman: add fixed mode to gem_mmap__cpu Matthew Auld
2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 05/11] lib/i915/gem_mman: update mmap_offset_types with FIXED Matthew Auld
2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 06/11] lib/ioctl_wrappers: update mmap_{read, write} for discrete Matthew Auld
2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 07/11] lib/intel_bufops: " Matthew Auld
2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 08/11] lib/ioctl_wrappers: update set_domain " Matthew Auld
2021-08-02  6:24   ` Dixit, Ashutosh
2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 09/11] tests/i915/module_load: update " Matthew Auld
2021-08-02  6:25   ` Dixit, Ashutosh
2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 10/11] lib/i915/gem_mman: add helper query for has_device_coherent Matthew Auld
2021-07-30  8:53 ` [Intel-gfx] [PATCH i-g-t v3 11/11] tests/i915/gem_exec_fence: use device_coherent mmap Matthew Auld

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