intel-gfx.lists.freedesktop.org archive mirror
 help / color / mirror / Atom feed
From: Lucas De Marchi <lucas.demarchi@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v4 02/18] drm/i915/xehpsdv: Define steering tables
Date: Wed, 4 Aug 2021 13:13:46 -0700	[thread overview]
Message-ID: <20210804201346.4mo7pqr5xwmjsa3l@ldmartin-desk2> (raw)
In-Reply-To: <20210729170008.2836648-3-matthew.d.roper@intel.com>

On Thu, Jul 29, 2021 at 09:59:52AM -0700, Matt Roper wrote:
>Define and initialize the MMIO ranges for which XeHP SDV requires MSLICE
>and LNCF steering.
>
>Bspec: 66534
>Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/gt/intel_gt.c          | 19 ++++++++++++++++++-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +++++++++--
> 2 files changed, 27 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
>index 39b224600f38..8e13bfc81634 100644
>--- a/drivers/gpu/drm/i915/gt/intel_gt.c
>+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>@@ -89,6 +89,20 @@ static const struct intel_mmio_range icl_l3bank_steering_table[] = {
> 	{},
> };
>
>+static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
>+	{ 0x004000, 0x004AFF },
>+	{ 0x00C800, 0x00CFFF },
>+	{ 0x00DD00, 0x00DDFF },
>+	{ 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
>+	{},
>+};
>+
>+static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
>+	{ 0x00B000, 0x00B0FF },
>+	{ 0x00D800, 0x00D8FF },
>+	{},
>+};
>+
> static u16 slicemask(struct intel_gt *gt, int count)
> {
> 	u64 dss_mask = intel_sseu_get_subslices(&gt->info.sseu, 0);
>@@ -115,7 +129,10 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> 			(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> 			 GEN12_MEML3_EN_MASK);
>
>-	if (GRAPHICS_VER(i915) >= 11 &&
>+	if (IS_XEHPSDV(i915)) {
>+		gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
>+		gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
>+	} else if (GRAPHICS_VER(i915) >= 11 &&
> 		   GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
> 		gt->steering_table[L3BANK] = icl_l3bank_steering_table;
> 		gt->info.l3bank_mask =
>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>index f2ceabb0e2ea..8717337a6c81 100644
>--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>@@ -934,7 +934,6 @@ icl_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> 	__add_mcr_wa(i915, wal, slice, subslice);
> }
>
>-__maybe_unused
> static void
> xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> {
>@@ -1136,10 +1135,18 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> 			    VSUNIT_CLKGATE_DIS_TGL);
> }
>
>+static void
>+xehpsdv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>+{
>+	xehp_init_mcr(&i915->gt, wal);
>+}
>+
> static void
> gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> {
>-	if (IS_DG1(i915))
>+	if (IS_XEHPSDV(i915))
>+		xehpsdv_gt_workarounds_init(i915, wal);
>+	else if (IS_DG1(i915))
> 		dg1_gt_workarounds_init(i915, wal);
> 	else if (IS_TIGERLAKE(i915))
> 		tgl_gt_workarounds_init(i915, wal);
>-- 
>2.25.4
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2021-08-04 20:13 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-29 16:59 [Intel-gfx] [PATCH v4 00/18] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper
2021-07-29 16:59 ` [Intel-gfx] [PATCH v4 01/18] drm/i915/xehp: handle new steering options Matt Roper
2021-08-04 19:53   ` Lucas De Marchi
2021-07-29 16:59 ` [Intel-gfx] [PATCH v4 02/18] drm/i915/xehpsdv: Define steering tables Matt Roper
2021-08-04 20:13   ` Lucas De Marchi [this message]
2021-07-29 16:59 ` [Intel-gfx] [PATCH v4 03/18] drm/i915/dg2: Add forcewake table Matt Roper
2021-08-04  0:15   ` Souza, Jose
2021-07-29 16:59 ` [Intel-gfx] [PATCH v4 04/18] drm/i915/dg2: Update LNCF steering ranges Matt Roper
2021-08-04 20:16   ` Lucas De Marchi
2021-07-29 16:59 ` [Intel-gfx] [PATCH v4 05/18] drm/i915/dg2: Add SQIDI steering Matt Roper
2021-08-04 20:22   ` Lucas De Marchi
2021-08-05 15:11     ` Matt Roper
2021-07-29 16:59 ` [Intel-gfx] [PATCH v4 06/18] drm/i915/xehp: Loop over all gslices for INSTDONE processing Matt Roper
2021-07-29 16:59 ` [Intel-gfx] [PATCH v4 07/18] drm/i915/dg2: Report INSTDONE_GEOM values in error state Matt Roper
2021-07-29 16:59 ` [Intel-gfx] [PATCH v4 08/18] drm/i915/xehp: Changes to ss/eu definitions Matt Roper
2021-08-04  0:17   ` Souza, Jose
2021-07-29 16:59 ` [Intel-gfx] [PATCH v4 09/18] drm/i915/xehpsdv: Add maximum sseu limits Matt Roper
2021-08-04 20:26   ` Lucas De Marchi
2021-07-29 17:00 ` [Intel-gfx] [PATCH v4 10/18] drm/i915/xehpsdv: Add compute DSS type Matt Roper
2021-08-04 20:36   ` Lucas De Marchi
2021-08-04 21:00     ` Matt Roper
2021-07-29 17:00 ` [Intel-gfx] [PATCH v4 11/18] drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV Matt Roper
2021-07-29 17:00 ` [Intel-gfx] [PATCH v4 12/18] drm/i915/xehpsdv: Define MOCS table for " Matt Roper
2021-07-29 17:31   ` Lucas De Marchi
2021-07-30  7:16     ` Siddiqui, Ayaz A
2021-07-30 17:01       ` Matt Roper
2021-07-29 17:00 ` [Intel-gfx] [PATCH v4 13/18] drm/i915/dg2: Define MOCS table for DG2 Matt Roper
2021-07-29 17:00 ` [Intel-gfx] [PATCH v4 14/18] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper
2021-07-29 17:00 ` [Intel-gfx] [PATCH v4 15/18] drm/i915/xehpsdv: Read correct RP_STATE_CAP register Matt Roper
2021-07-29 17:00 ` [Intel-gfx] [PATCH v4 16/18] drm/i915/dg2: Add new LRI reg offsets Matt Roper
2021-07-29 17:00 ` [Intel-gfx] [PATCH v4 17/18] drm/i915/dg2: Maintain backward-compatible nested batch behavior Matt Roper
2021-07-29 17:00 ` [Intel-gfx] [PATCH v4 18/18] drm/i915/dg2: Configure PCON in DP pre-enable path Matt Roper
2021-07-29 20:59 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Begin enabling Xe_HP SDV and DG2 platforms (rev8) Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210804201346.4mo7pqr5xwmjsa3l@ldmartin-desk2 \
    --to=lucas.demarchi@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=matthew.d.roper@intel.com \
    --subject='Re: [Intel-gfx] [PATCH v4 02/18] drm/i915/xehpsdv: Define steering tables' \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).