From: Animesh Manna <animesh.manna@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>,
Imre Deak <imre.deak@intel.com>,
Animesh Manna <animesh.manna@intel.com>
Subject: [Intel-gfx] [PATCH 2/5] drm/i915/dp: fix TGL and ICL max source rates
Date: Wed, 1 Sep 2021 21:33:59 +0530 [thread overview]
Message-ID: <20210901160402.24816-3-animesh.manna@intel.com> (raw)
In-Reply-To: <20210901160402.24816-1-animesh.manna@intel.com>
From: Jani Nikula <jani.nikula@intel.com>
Combo phy is limited to 5.4 GHz on low-voltage SKUs. Combo phy DP is
limited to 5.4 GHz, while combo phy eDP can do 8.1 GHz.
Bspec: 20584, 20598, 49180, 49201
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7e823c02c1e9..d7486017b7f6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -291,6 +291,15 @@ static int dg2_max_source_rate(struct intel_dp *intel_dp)
return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
}
+static bool is_low_voltage_sku(struct drm_i915_private *i915, enum phy phy)
+{
+ u32 voltage;
+
+ voltage = intel_de_read(i915, ICL_PORT_COMP_DW3(phy)) & VOLTAGE_INFO_MASK;
+
+ return voltage == VOLTAGE_INFO_0_85V;
+}
+
static int icl_max_source_rate(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -298,7 +307,7 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
if (intel_phy_is_combo(dev_priv, phy) &&
- !intel_dp_is_edp(intel_dp))
+ (is_low_voltage_sku(dev_priv, phy) || !intel_dp_is_edp(intel_dp)))
return 540000;
return 810000;
--
2.29.0
next prev parent reply other threads:[~2021-09-01 16:26 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-01 16:03 [Intel-gfx] [PATCH 0/5] Fix in max source calculation for dp/edp Animesh Manna
2021-09-01 16:03 ` [Intel-gfx] [PATCH 1/5] drm/i915/dp: Fix eDP max rate for display 11+ Animesh Manna
2021-09-01 16:03 ` Animesh Manna [this message]
2021-09-01 16:04 ` [Intel-gfx] [PATCH 3/5] drm/i915/dp: fix EHL/JSL max source rates calculation Animesh Manna
2021-09-01 16:04 ` [Intel-gfx] [PATCH 4/5] drm/i915/dp: fix DG1 and RKL max source rates Animesh Manna
2021-09-01 16:04 ` [Intel-gfx] [PATCH 5/5] drm/i915/dp: fix for ADL_P/S dp/edp " Animesh Manna
2021-09-01 19:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix in max source calculation for dp/edp (rev3) Patchwork
2021-09-01 19:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-01 23:04 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-02 12:52 ` Imre Deak
2021-09-06 3:44 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2021-08-12 5:48 [Intel-gfx] [PATCH 0/5] Fix in max source calculation for dp/edp Animesh Manna
2021-08-12 5:48 ` [Intel-gfx] [PATCH 2/5] drm/i915/dp: fix TGL and ICL max source rates Animesh Manna
2021-08-12 15:12 ` Imre Deak
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