From: Lucas De Marchi <lucas.demarchi@intel.com>
To: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
Cc: intel-gfx@lists.freedesktop.org, Matt Roper <matthew.d.roper@intel.com>
Subject: Re: [Intel-gfx] [PATCH V4 2/6] drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward
Date: Thu, 2 Sep 2021 15:59:44 -0700 [thread overview]
Message-ID: <20210902225944.px4pjdwklqov73rd@ldmartin-desk2> (raw)
In-Reply-To: <20210902185635.290538-3-ayaz.siddiqui@intel.com>
On Fri, Sep 03, 2021 at 12:26:31AM +0530, Ayaz A Siddiqui wrote:
>Cache-control registers for Command Stream(CMD_CCTL) are used
>to set catchability for memory writes and reads outputted by
>Command Streamers on Gen12 onward platforms.
>
>These registers need to point un-cached(UC) MOCS index.
>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
>---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 +++++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 17 ++++++++++++++
> 2 files changed, 43 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>index 94e1937f8d296..38c66765ff94c 100644
>--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>@@ -1640,6 +1640,30 @@ void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
> i915_mmio_reg_offset(RING_NOPID(base)));
> }
>
>+/*
>+ * engine_fake_wa_init(), a place holder to program the registers
>+ * which are not part of a workaround.
>+ * Adding programming of those register inside workaround will
>+ * allow utilizing wa framework to proper application and verification.
>+ */
>+static void
>+engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>+{
>+ u8 mocs;
>+
>+ if (GRAPHICS_VER(engine->i915) >= 12) {
this is including TGL. Shouldn't TGL be the exception here?
Lucas De Marchi
next prev parent reply other threads:[~2021-09-02 22:59 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-02 18:56 [Intel-gfx] [PATCH V4 0/6] drm/i915/gt: Initialize unused MOCS entries to L3_WB Ayaz A Siddiqui
2021-09-02 18:56 ` [Intel-gfx] [PATCH V4 1/6] drm/i915/gt: Add support of mocs propagation Ayaz A Siddiqui
2021-09-02 20:19 ` Matt Roper
2021-09-02 18:56 ` [Intel-gfx] [PATCH V4 2/6] drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward Ayaz A Siddiqui
2021-09-02 20:35 ` Matt Roper
2021-09-02 22:59 ` Lucas De Marchi [this message]
2021-09-02 23:26 ` Matt Roper
2021-09-02 18:56 ` [Intel-gfx] [PATCH V4 3/6] drm/i915/gt: Set BLIT_CCTL reg to un-cached Ayaz A Siddiqui
2021-09-02 20:45 ` Matt Roper
2021-09-02 18:56 ` [Intel-gfx] [PATCH V4 4/6] drm/i915/gt: Initialize unused MOCS entries with device specific values Ayaz A Siddiqui
2021-09-02 20:51 ` Matt Roper
2021-09-02 18:56 ` [Intel-gfx] [PATCH V4 5/6] drm/i915/gt: Initialize L3CC table in mocs init Ayaz A Siddiqui
2021-09-02 21:01 ` Matt Roper
2021-09-02 18:56 ` [Intel-gfx] [PATCH V4 6/6] drm/i915/selftest: Remove Renderer class check for l3cc table read Ayaz A Siddiqui
2021-09-02 21:07 ` Matt Roper
2021-09-02 19:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/gt: Initialize unused MOCS entries to L3_WB Patchwork
2021-09-02 20:10 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-09-03 5:21 ` Siddiqui, Ayaz A
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