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From: Dave Airlie <airlied@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@linux.intel.com, Dave Airlie <airlied@redhat.com>
Subject: [Intel-gfx] [PATCH 19/25] drm/i915/display: move delay and pch values to display struct
Date: Tue,  7 Sep 2021 17:25:43 +1000	[thread overview]
Message-ID: <20210907072549.2962226-20-airlied@gmail.com> (raw)
In-Reply-To: <20210907072549.2962226-1-airlied@gmail.com>

From: Dave Airlie <airlied@redhat.com>

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 34 +++++++++----------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  4 +--
 drivers/gpu/drm/i915/display/intel_vrr.c      |  6 ++--
 drivers/gpu/drm/i915/i915_drv.h               | 14 ++++----
 4 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 60ef938aed0e..7a4100a58b48 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -632,7 +632,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
 		/* Configure frame start delay to match the CPU */
 		val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
-		val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+		val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
 		intel_de_write(dev_priv, reg, val);
 	}
 
@@ -643,7 +643,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 	if (HAS_PCH_IBX(dev_priv)) {
 		/* Configure frame start delay to match the CPU */
 		val &= ~TRANS_FRAME_START_DELAY_MASK;
-		val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+		val |= TRANS_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
 
 		/*
 		 * Make the BPC in transcoder be consistent with
@@ -688,7 +688,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
 	/* Configure frame start delay to match the CPU */
 	val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
-	val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+	val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
 	intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
 
 	val = TRANS_ENABLE;
@@ -2991,7 +2991,7 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
 
 	val = intel_de_read(dev_priv, reg);
 	val &= ~HSW_FRAME_START_DELAY_MASK;
-	val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+	val |= HSW_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
 	intel_de_write(dev_priv, reg, val);
 }
 
@@ -4463,7 +4463,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
 
 	pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
 
-	pipeconf |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+	pipeconf |= PIPECONF_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
 
 	intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
 	intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
@@ -5096,24 +5096,24 @@ static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
 	 * clock hierarchy. That would also allow us to do
 	 * clock bending finally.
 	 */
-	dev_priv->pch_ssc_use = 0;
+	dev_priv->display->pch_ssc_use = 0;
 
 	if (spll_uses_pch_ssc(dev_priv)) {
 		drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
-		dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
+		dev_priv->display->pch_ssc_use |= BIT(DPLL_ID_SPLL);
 	}
 
 	if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
 		drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
-		dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
+		dev_priv->display->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
 	}
 
 	if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
 		drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
-		dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
+		dev_priv->display->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
 	}
 
-	if (dev_priv->pch_ssc_use)
+	if (dev_priv->display->pch_ssc_use)
 		return;
 
 	if (has_fdi) {
@@ -5186,7 +5186,7 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
 
 	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
 
-	val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+	val |= PIPECONF_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
 
 	intel_de_write(dev_priv, PIPECONF(pipe), val);
 	intel_de_posting_read(dev_priv, PIPECONF(pipe));
@@ -11573,9 +11573,9 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
 	i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
 					WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
 
-	i915->framestart_delay = 1; /* 1-4 */
+	i915->display->framestart_delay = 1; /* 1-4 */
 
-	i915->window2_delay = 0; /* No DSB so no window2 delay */
+	i915->display->window2_delay = 0; /* No DSB so no window2 delay */
 
 	intel_mode_config_init(i915);
 
@@ -11915,7 +11915,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
 
 		val = intel_de_read(dev_priv, reg);
 		val &= ~HSW_FRAME_START_DELAY_MASK;
-		val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+		val |= HSW_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
 		intel_de_write(dev_priv, reg, val);
 	} else {
 		i915_reg_t reg = PIPECONF(cpu_transcoder);
@@ -11923,7 +11923,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
 
 		val = intel_de_read(dev_priv, reg);
 		val &= ~PIPECONF_FRAME_START_DELAY_MASK;
-		val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+		val |= PIPECONF_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
 		intel_de_write(dev_priv, reg, val);
 	}
 
@@ -11936,7 +11936,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
 
 		val = intel_de_read(dev_priv, reg);
 		val &= ~TRANS_FRAME_START_DELAY_MASK;
-		val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+		val |= TRANS_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
 		intel_de_write(dev_priv, reg, val);
 	} else {
 		enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
@@ -11945,7 +11945,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
 
 		val = intel_de_read(dev_priv, reg);
 		val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
-		val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+		val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
 		intel_de_write(dev_priv, reg, val);
 	}
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 11fefa6de27e..47036316fbf9 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -574,7 +574,7 @@ static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
 	 * Try to set up the PCH reference clock once all DPLLs
 	 * that depend on it have been shut down.
 	 */
-	if (dev_priv->pch_ssc_use & BIT(id))
+	if (dev_priv->display->pch_ssc_use & BIT(id))
 		intel_init_pch_refclk(dev_priv);
 }
 
@@ -592,7 +592,7 @@ static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
 	 * Try to set up the PCH reference clock once all DPLLs
 	 * that depend on it have been shut down.
 	 */
-	if (dev_priv->pch_ssc_use & BIT(id))
+	if (dev_priv->display->pch_ssc_use & BIT(id))
 		intel_init_pch_refclk(dev_priv);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index c335b1dbafcf..ce4419ee11f2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -69,9 +69,9 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
 
 	/* The hw imposes the extra scanline before frame start */
 	if (DISPLAY_VER(i915) >= 13)
-		return crtc_state->vrr.guardband + i915->framestart_delay + 1;
+		return crtc_state->vrr.guardband + i915->display->framestart_delay + 1;
 	else
-		return crtc_state->vrr.pipeline_full + i915->framestart_delay + 1;
+		return crtc_state->vrr.pipeline_full + i915->display->framestart_delay + 1;
 }
 
 int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
@@ -135,7 +135,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	if (DISPLAY_VER(i915) >= 13)
 		crtc_state->vrr.guardband =
 			crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay -
-			i915->window2_delay;
+			i915->display->window2_delay;
 	else
 		/*
 		 * FIXME: s/4/framestart_delay+1/ to get consistent
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a487686b1b71..6eba551396fc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -848,6 +848,13 @@ struct drm_i915_display {
 	unsigned int fdi_pll_freq;
 	unsigned int czclk_freq;
 
+	u8 framestart_delay;
+
+	/* Window2 specifies time required to program DSB (Window2) in number of scan lines */
+	u8 window2_delay;
+
+	u8 pch_ssc_use;
+
 	/**
 	 * Base address of where the gmbus and gpio blocks are located (either
 	 * on PCH or on SoC for platforms without PCH).
@@ -1199,13 +1206,6 @@ struct drm_i915_private {
 		struct file *mmap_singleton;
 	} gem;
 
-	u8 framestart_delay;
-
-	/* Window2 specifies time required to program DSB (Window2) in number of scan lines */
-	u8 window2_delay;
-
-	u8 pch_ssc_use;
-
 	/* For i915gm/i945gm vblank irq workaround */
 	u8 vblank_enabled;
 
-- 
2.31.1


  parent reply	other threads:[~2021-09-07  7:27 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-07  7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 01/25] drm/i915: move display funcs into a display struct. (v3) Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 02/25] drm/i915/display: move cdclk info into display Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 03/25] drm/i915: move more pll/clocks into display struct Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 04/25] drm/i915/display: move gmbus " Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 05/25] drm/i915/display: move intel_dmc " Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 06/25] drm/i915/display: move mipi_mmio_base to " Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 07/25] drm/i915/display: move pps_mmio_base " Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 08/25] drm/i915/drrs: just use some local vars to simplify drrs code Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 09/25] drm/i915/display: move drrs into display struct Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 10/25] drm/i915/display: move fbc " Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 11/25] drm/i915/display: move pipe/plane mappings to " Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 12/25] drm/i915/display: move properties into " Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 13/25] drm/i915/display: move audio related members " Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 14/25] drm/i915/display: move HDCP related items " Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 15/25] drm/i915/display: move hotplug struct to " Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 16/25] drm/i915/display: move overlay into " Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 17/25] drm/i915/display: move fbdev info to " Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 18/25] drm/i915/display: move fb_tracking " Dave Airlie
2021-09-07  7:25 ` Dave Airlie [this message]
2021-09-07  7:25 ` [Intel-gfx] [PATCH 20/25] drm/intel/display: move atomic related things to display Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 21/25] drm/i915/display: move a bunch of platform misc regs " Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 22/25] drm/i915/display: move dpll struct into display Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 23/25] drm/i915/display: move fdi_rx_config into display struct Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 24/25] drm/i915/display: move workqueues to " Dave Airlie
2021-09-07  7:25 ` [Intel-gfx] [PATCH 25/25] drm/i915/display: move pps/backlight mutexes into display Dave Airlie
2021-09-07  7:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for refactor display struct Patchwork
2021-09-07  8:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-07 10:19 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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